CN115862512A - Source driver, configuration method and electronic device - Google Patents

Abstract

The disclosure relates to a source driver, a configuration method and an electronic device. The source driver comprises at least one source driving chip, wherein the at least one source driving chip is connected with a controller through at least one group of differential signal line pairs to receive differential signals from the controller; at least one of the at least one source driver chip includes at least one termination resistor, both ends of each termination resistor are respectively connected to two signal lines of an object differential signal line pair in the at least one group of differential signal line pairs, and the termination resistors are configured to perform impedance matching on the object differential signal line pair. The source driver can improve the integrity of differential signals transmitted by the differential signal line pair.

Description

Source driver, configuration method and electronic device

Technical Field

Embodiments of the present disclosure relate to a source driver A configuration method and an electronic device.

Background

Differential transmission is a technology for transmitting signals through a differential signal line pair, and is widely applied to various interface communications, ethernet communications, optical fiber telecommunications, and the like due to the advantages of strong noise interference resistance, effective electromagnetic interference suppression, and the like.

With the development of integrated circuits and electronic technologies, the frequency of differential signals transmitted by differential signal line pairs is higher and higher.

Disclosure of Invention

At least one embodiment of the present disclosure provides a source driver, including: at least one source driver chip, wherein the at least one source driver chip is connected with a controller through at least one set of differential signal line pairs to receive differential signals from the controller; at least one of the at least one source driver chip includes at least one termination resistor, both ends of each termination resistor are respectively connected to two signal lines of an object differential signal line pair in the at least one group of differential signal line pairs, and the termination resistors are configured to perform impedance matching on the object differential signal line pair.

For example, in the source driver provided in an embodiment of the present disclosure, at least one source driver chip includes a plurality of source driver chips, the plurality of source driver chips includes a first driver chip, the at least one termination resistor includes a first termination resistor, the first driver chip includes the first termination resistor, and the first driver chip is a source driver chip to which the output terminal of the target differential signal line pair that is farthest from the controller is connected.

For example, in the source driver provided in an embodiment of the present disclosure, the plurality of source driver chips further include a second driver chip, the at least one termination resistor further includes a second termination resistor, the second driver chip includes the second termination resistor, and the second driver chip is the source driver chip connected to the output end of the target differential signal line pair closest to the controller.

For example, in the source driver provided in an embodiment of the present disclosure, each source driver chip connected to the target differential signal line pair includes one of the at least one termination resistor.

For example, in the source driver provided in an embodiment of the present disclosure, at least one source driver chip is each connected to the controller through a clock signal line to receive a clock signal from the controller and to receive the differential signal according to the clock signal.

For example, in the source driver provided in an embodiment of the present disclosure, at least one source driver chip includes a plurality of source driver chips, the plurality of source driver chips are divided into a plurality of source driver chip groups, each source driver chip group is connected to the controller through a set of differential signal line pairs, and each source driver chip in at least some of the plurality of source driver chip groups is connected to the same clock signal line.

For example, in the source driver provided in an embodiment of the present disclosure, each of the source driver chips in two source driver chip groups adjacent in physical layout is connected to the same clock signal line.

For example, in a source driver provided in an embodiment of the present disclosure, at least one set of differential signal line pairs each transmit a display signal in at least two modes in one frame display period, the display signal provided in the at least two modes includes configuration data and image data, and the configuration data is used to configure the source driver so that the source driver processes the image data according to the configuration data.

For example, in the source driver provided in an embodiment of the present disclosure, the source driver chip in which at least one terminating resistor is located includes a resistance value configuration register, and the resistance values of the at least one terminating resistor are configured through the resistance value configuration register respectively.

At least one embodiment of the present disclosure provides a configuration method applied to a source driver provided in any one of the embodiments of the present disclosure, the method including: acquiring configuration information of the at least one termination resistor; and configuring the resistance value of the at least one terminating resistor according to the configuration information.

For example, in a configuration method provided by an embodiment of the present disclosure, a source driver chip in which at least one terminating resistor is located includes a resistance value configuration register, and configuring a resistance value of the at least one terminating resistor according to the configuration information includes: and configuring the value of the resistance value configuration register according to the configuration information so as to configure the resistance value of the at least one terminating resistor.

At least one embodiment of the present disclosure provides an electronic device, including a controller, and a source driver including at least one source driving chip, wherein the at least one source driving chip is connected with the controller through at least one set of differential signal line pairs to receive a differential signal from the controller; at least one of the at least one source driver chip includes at least one termination resistor, both ends of the termination resistor are respectively connected to two signal lines of an object differential signal line pair in the at least one group of differential signal line pairs, and the termination resistor is configured to perform impedance matching on the object differential signal line pair.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 is a schematic diagram showing a connection relationship between a controller and a source driver;

FIG. 2 is a schematic diagram showing another connection between a controller and a source driver;

fig. 3 illustrates a schematic diagram of a source driver provided in at least one embodiment of the present disclosure;

FIG. 4 shows a schematic diagram of a termination resistor disposed at the ends of a differential signal line pair;

fig. 5 illustrates a schematic diagram of another source driver provided by at least one embodiment of the present disclosure;

fig. 6 illustrates a schematic diagram of another source driver provided by at least one embodiment of the present disclosure;

fig. 7 is a schematic diagram illustrating a connection relationship between another source driver and a controller according to at least one embodiment of the disclosure;

fig. 8A and 8B are signal format diagrams illustrating a data signal provided by a controller to a source driver according to at least one embodiment of the present disclosure;

FIG. 9 illustrates a flow chart of a configuration method provided by at least one embodiment of the present disclosure; and

fig. 10 illustrates a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

For example, the differential technique may be applied to a display panel. The various driving circuits of the display panel generally include a scan driving integrated circuit (also referred to as a gate driver or a G-IC), a data driving integrated circuit (also referred to as a source driver or an SD-IC), a controller, and the like. For example, the controller and the source driver are connected through at least one set of differential signal line pairs to perform data transmission through the set of differential signal lines. For another example, the controller and the gate driver may be connected through another at least one set of differential signal line pairs to perform data transmission through the set of differential signal lines.

The controller is mainly used to convert data signals, control signals, clock signals, and the like received from the outside (e.g., a signal source such as a storage device, a network modem, and the like) into data signals, gate signals, control signals, clock signals, and the like suitable for the source driver and the gate driver, so as to implement image display driving of the display panel. For example, the Controller may be a Timing Controller (TCON). The source driver is mainly used for receiving the digital signals (display signals or image signals) and control signals and the like provided by the controller, converting the digital signals into corresponding analog gray scale voltage signals through digital-to-analog conversion, and inputting the analog gray scale voltage signals into each row of pixel units of the pixel array of the display panel. The gate driver is mainly used for starting pixel units of each row of the pixel array line by line (or interlaced line), for example, and is matched with the source driver under the action of the control signal, and the required data signal is input into the corresponding pixel unit for the started pixel unit line, so that the pixel unit can display according to the data signal.

In the display process of the display panel, the video and the animation are formed by combining a plurality of pictures which are sequentially displayed according to time sequence (for example, the frame rate is 60Hz or 120Hz, and the like), each picture is a frame, namely, one frame of image refers to a complete picture displayed by the display panel. During the display of one frame of image, the gate driver sequentially turns on each row of pixel units in the pixel array from the first row to the last row to scan, and during the scanning, the source driver inputs the data signals required by each row of pixel units into the turned-on pixel units, thereby completing the scanning and display required by one frame of image. For example, due to the process of the pixel units of the display panel, the display screen needs to be continuously refreshed to obtain a clear and complete display effect with good quality, each time the display screen needs to display one frame of image, and the multiple frames of continuously displayed images form a static screen or a dynamic screen in visual effect.

Fig. 1 shows a schematic diagram of a connection relationship between a controller and a source driver.

Fig. 1 (a), (b), (c), and (d) in fig. 1 are 4 embodiments describing a connection relationship between a controller and a source driver, respectively. The controller is, for example, a timing controller TCON, and the source driver and the timing controller TCON may be connected by any connection means shown in fig. 1 (a), (b), (c), and (d).

As shown in fig. 1 (a) to (d), in the embodiments, the source driver includes a plurality of source driver chips. For example, in the example of fig. 1 (a), the source driver 10 includes at least a source driving chip SD1, a source driving chip SD2, a source driving chip SD3, a source driving chip SD4, a source driving chip SD5, a source driving chip SD6, and the like. Although a limited number of source driver chips are shown in fig. 1 (a) -1 (d), this does not mean that the source driver can only contain e.g. 6 or 12 source driver chips, in practical applications, the source driver often includes more or fewer source driver chips, and the number of the source driver chips included in the source driver can be set according to actual needs.

For example, as shown in fig. 1 (a), a plurality of source driving chips are each connected to the timing controller TCON through a set of differential signal line pairs 100 for the source driving chips to receive differential signals. For example, the Differential signal line pair is a Low-Voltage Differential signal line pair, and the Low-Voltage Differential signal line pair transmits, for example, a Low-Voltage Differential Signaling (LVDS), a mini-LVDS, or other Differential signals. In the present disclosure, the embodiments are described unless the differential signal line pair is specifically described as a low voltage differential signal line pair as an example.

In some embodiments of the present disclosure, a set of differential signal line pairs 100 includes, for example, 3 low voltage differential signal line pairs or 6 low voltage differential signal line pairs. For ease of description, only one of the pair of differential signal lines is shown in the various embodiments of fig. 1.

As shown in fig. 1 (a), each source driving chip is also connected to the timing controller TCON through a clock signal line 200. The clock signal line 200 may include only one signal line through which a single-ended signal is transmitted, or the clock signal line 200 may be a differential signal line pair formed by two differential signal lines through which a differential signal is transmitted. In the embodiment of the present disclosure, the clock signal line 200 is exemplified as a differential signal line pair formed by including two differential signal lines.

For example, the timing controller TCON and the source driver 10 are applied to a display panel for driving a pixel array in the display panel to display an image. In the example of fig. 1 (a), for example, the display panel is a Full High Definition (FHD) panel, the resolution of the display panel reaches 1920 × 1080, the refresh frequency of the display panel is 60HZ, and if the clock frequency of the clock signal is 300MHZ, the number of pins PC =1 × 2+6 × 2=14 required by the timing controller TCON, that is, 1 pair of clock signal lines (2 signal lines) for transmitting the clock signal and 6 pair of low voltage differential signal lines (12 signal lines) for transmitting the data signal are required.

Relative to the example of fig. 1 (a), the example of fig. 1 (b) increases the refresh frequency of the display panel, increasing the refresh frequency of the display panel to 120HZ. When the clock frequency is not changed (300 MHZ) and the number of low-voltage differential signal line pairs in a group of low-voltage differential signal line pairs is not changed (i.e., 6 pairs), the number of pins of the timing controller TCON needs to be increased to meet the requirement of the refresh frequency. For example, the timing controller TCON outputs data signals through two sets of low voltage differential signal line pairs (e.g., the low voltage differential signal line pair group 101 and the low voltage differential signal line pair group 102), and outputs clock signals through two clock signal lines (e.g., the clock signal line 201 and the clock signal line 202), since the number of pins PC =2 × 2+6 × 2=28 required for the timing controller TCON, that is, 2 pairs of clock signal lines (4 signal lines) for transmitting clock signals and 12 pairs of low voltage differential signal lines (i.e., 2 sets of low voltage differential signal line pairs, 24 signal lines in total) for transmitting data signals are required.

In the example of fig. 1 (c), the refresh frequency of the display panel is 60HZ and the resolution is 4096 × 2160 (i.e., 4K resolution). If the clock frequency is 300MHZ, the refresh frequency and the resolution are realized, and the number of pins of the timing controller TCON needs to be increased. For example, the timing controller TCON outputs data signals through 4 sets of low voltage differential signal line pairs (e.g., the low voltage differential signal line pair group 103, the low voltage differential signal line pair group 104, the low voltage differential signal line pair group 105, and the low voltage differential signal line pair group 106), and outputs clock signals through 4 clock signal lines (e.g., the clock signal line 203, the clock signal line 204, the clock signal line 205, and the clock signal line 206), since the number of pins PC =4 × 2+6 × 2 × 4=56 required for the timing controller TCON, that is, 4 pairs of clock signal lines (8 signal lines) for transmitting clock signals and 24 pairs of low voltage differential signal lines (i.e., 4 sets of low voltage differential signal line pairs, total 48 signal lines) for transmitting data signals are required.

In the example of fig. 1 (d), the refresh frequency of the display panel is 120HZ and the resolution is 4096 × 2160 (i.e., 4K resolution). If the clock frequency is 300MHZ, the refresh frequency and the resolution are realized, and the number of pins of the timing controller TCON needs to be increased continuously. For example, the timing controller TCON outputs data signals through 6 sets of low-voltage differential signal line pairs (e.g., the low-voltage differential signal line pair group 107, the low-voltage differential signal line pair group 108, the low-voltage differential signal line pair group 109, the low-voltage differential signal line pair group 110, the low-voltage differential signal line pair group 111, the low-voltage differential signal line pair group 112), and outputs clock signals through 6 clock signal lines (e.g., the clock signal line 207, the clock signal line 208, the clock signal line 209, the clock signal line 210, the clock signal line 211, the clock signal line 212), since the number of pins PC =6 × 2+6 × 2 × 6=84 required for the timing controller TCON, that is, 6 pairs of clock signal lines (8 signal lines) for transmitting clock signals, and 36 pairs of low-voltage differential signal lines (i.e., 6 sets of low-voltage differential signal line pairs, total 72 signal lines) for transmitting data signals.

Fig. 2 shows another connection relationship between a controller and a source driver.

In fig. 2, (a), (b), (c), and (d) are 4 embodiments describing the connection relationship between the controller and the source driver, respectively. For example, the timing controller TCON and the source driver 10 may be connected in any connection manner of (a), (b), (c), and (d).

The embodiment of fig. 2 (a) -2 (d) increases the clock frequency, for example to 600MHZ, 900MHZ or 1200MHZ, compared to the embodiment of fig. 1 (a) -1 (d). Since the clock frequency is increased, the number of low voltage differential signal line pairs for transmitting data signals can be reduced, for example, a group of low voltage differential signal line pairs includes 3 low voltage differential signal line pairs, so that the number of pins of the timing controller TCON can be reduced.

As shown in fig. 2 (a), each source driving chip is also connected to the timing controller TCON through a clock signal line 300. The clock signal line 300 may be a differential signal line pair including two differential signal lines through which a differential signal is transmitted.

For example, in the example of fig. 2 (a), for example, the display panel is a full high-definition panel, the resolution of the display panel reaches 1920 × 1080, the refresh frequency of the display panel is 60HZ, and if the clock frequency of the clock signal CLK is 600MHZ, the number of pins PC =1 × 2+3 × 2=8 required by the timing controller TCON, that is, 1 pair of clock signal lines (2 signal lines) for transmitting clock signals and 3 pair of low-voltage differential signal lines (6 signal lines) for transmitting data signals are required.

The example of fig. 2 (b) increases the refresh frequency of the display panel relative to the example of fig. 2 (a), increasing the refresh frequency of the display panel to 120HZ. When the clock frequency is not changed (600 MHZ) and the number of low-voltage differential signal line pairs in a group of low-voltage differential signal line pairs is not changed (i.e., 3 pairs), the number of pins of the timing controller TCON needs to be increased to meet the requirement of the refresh frequency. For example, the timing controller TCON outputs data signals through two sets of low voltage differential signal line pairs (e.g., the low voltage differential signal line pair group 401 and the low voltage differential signal line pair group 402) and outputs clock signals through two clock signal lines (e.g., the clock signal line 301 and the clock signal line 302), since the number of pins PC =2 × 2+3 × 2=16 required for the timing controller TCON, that is, 2 pairs of clock signal lines (4 signal lines) for transmitting clock signals and 6 pairs of low voltage differential signal lines (i.e., 2 sets of low voltage differential signal line pairs, total 12 signal lines) for transmitting data signals are required.

In the example of fig. 2 (c), the refresh frequency of the display panel is 60HZ, and the resolution is 4096 × 2160 (i.e., 4K resolution). If the clock frequency is 900MHZ, in order to achieve the refresh frequency and resolution, for example, the timing controller TCON outputs data signals through 2 sets of low voltage differential signal line pairs (e.g., the low voltage differential signal line pair set 403, the low voltage differential signal line pair set 404), and outputs clock signals through 2 clock signal lines (e.g., the clock signal line 303, the clock signal line 304), since the number of pins PC =2 × 2+3 × 2=16 required for the timing controller TCON, that is, 2 pairs of clock signal lines (4 signal lines) for transmitting clock signals and 6 pairs of low voltage differential signal lines (i.e., 2 sets of low voltage differential signal line pairs, total 12 signal lines) for transmitting data signals are required.

In the example of fig. 2 (d), the refresh frequency of the display panel is 120HZ and the resolution is 4096 × 2160 (i.e., 4K resolution). If the clock frequency is 1200MHZ, in order to achieve the refresh frequency and resolution, for example, the timing controller TCON outputs data signals through 4 sets of low voltage differential signal line pairs (e.g., the low voltage differential signal line pair group 405, the low voltage differential signal line pair group 406, the low voltage differential signal line pair group 407, and the low voltage differential signal line pair group 408), and outputs clock signals through 4 clock signal lines (e.g., the clock signal line 305, the clock signal line 306, the clock signal line 307, and the clock signal line 308), since the number of pins PC =4 × 2+3 × 2 × 4=32 required for the timing controller TCON, that is, 4 pairs of clock signal lines (8 signal lines) for transmitting clock signals and 12 pairs of low voltage differential signal lines (i.e., 4 sets of low voltage differential signal line pairs, 24 signal lines in total) for transmitting data signals are required.

As can be seen from comparing the embodiment shown in fig. 1 with the embodiment shown in fig. 2, increasing the clock frequency of the clock signal for data signal transmission can significantly reduce the number of pins on the timing controller TCON and the number of source driving chips, thereby saving the production cost.

An increase in clock frequency increases the frequency at which differential signal pairs transmit differential signals, but this tends to degrade the integrity of the differential signals.

To this end, embodiments of the present disclosure provide a source driver including at least one source driving chip connected with a controller through at least one set of differential signal line pairs to receive differential signals from the controller. At least one of the at least one source driving chip includes at least one termination resistor, both ends of each termination resistor are respectively connected to two signal lines of a subject differential signal line pair of the at least one set of differential signal line pairs, and the termination resistors are configured to impedance-match the pairs of differential split signal lines. Compared with a source driver with termination resistors arranged at the tail ends of the differential signal line pairs, the source driver has the advantages that the termination resistors are arranged in the source driving chip, so that the effect of impedance matching of the differential signal line pairs is improved, and the signal integrity is improved. In addition, the termination resistor is arranged in the source driving chip, so that the termination resistor is easier to configure, and the impedance matching effect is improved.

Fig. 3 illustrates a schematic diagram of a source driver provided in at least one embodiment of the present disclosure.

As shown in FIG. 3, the source driver 30 includes at least one source driving chip, for example, the at least one source driving chip includes a source driving chip SD-1, a source driving chip SD-2, a source driving chip SD-3, a source driving chip SD-4, and the like.

The at least one source driving chip is connected with the controller through at least one group of differential signal line pairs to receive differential signals from the controller. For example, the source driving chip SD-1, the source driving chip SD-2, the source driving chip SD-3, and the source driving chip SD-4 are each connected to the timing controller TCON through a set of low voltage differential signal line pairs 310 to receive a data signal from the timing controller TCON. The set of low voltage differential signal line pairs 310 includes, for example, 3 low voltage differential signal line pairs or 6 low voltage differential signal line pairs. In the embodiments of the present disclosure, only 1 low voltage differential signal line pair of one group of low voltage differential signal line pairs is shown for convenience of representation.

In an embodiment of the present disclosure, at least one of the at least one source driver chip includes at least one termination resistor, and both ends of each termination resistor are respectively connected to two signal lines of the subject differential signal line pair in the at least one set of differential signal line pairs.

In some embodiments of the present disclosure, the source driver chip may include the same number of termination resistors as the number of differential signal line pairs included in the set of differential signal line pairs. For example, if a group of low voltage differential signal line pairs includes 3 low voltage differential signal line pairs, the number of termination resistors included in one source driver chip may be 3. That is, the two signal lines of each low-voltage differential signal line pair are respectively connected to one terminating resistor.

In other embodiments of the present disclosure, one source driver chip may include a number of termination resistors that is greater than or less than a number of low voltage differential signal line pairs included in a group of low voltage differential signal line pairs. For example, the two signal lines of each low-voltage differential signal line pair are respectively connected to a plurality of terminating resistors.

As shown in fig. 3, the source driver chip SD-4 includes a terminating resistor R1. Both ends of the terminating resistor R1 are connected to the two signal lines of the low-voltage differential signal line pair 310, respectively. The low-voltage differential signal line pair 310 is an example of a subject differential signal line pair. For example, the subject differential signal line pair is a pair of low-voltage differential signal lines of a group of low-voltage differential signal line pairs to which the source driver chip SD-4 is connected. The subject differential signal line pair may be any pair of low voltage differential signal lines.

For example, the set of differential signal line pairs to which the source driver chip SD-4 is connected includes 3 pairs of low voltage differential signal lines (i.e., 3 pairs of low voltage differential signal lines), and the source driver chip SD-4 may include 3 termination resistors, where the 3 termination resistors and the 3 pairs of low voltage differential signal lines are connected in a one-to-one correspondence, and two ends of each termination resistor are respectively connected to two signal lines of its corresponding pair of low voltage differential signal lines.

In an embodiment of the present disclosure, the termination resistor is configured to impedance match the pair of differential split signal lines. In some embodiments of the present disclosure, for example, the terminating resistor may have a resistance value equal to a value of a differential impedance of two signal lines connected at both ends thereof, respectively. The differential impedance of the low-voltage differential signal line pair can be calculated by those skilled in the art according to ohm's law and other calculation methods.

The termination resistors are arranged so that impedance matching is achieved for the low-voltage differential signal line pairs, thereby improving the integrity of differential signal transmission.

Fig. 4 shows a schematic diagram of a termination resistor disposed at the end of a differential signal line pair.

As shown in fig. 4, the source driver 400 includes a plurality of source driving chips, for example, a source driving chip 41, a source driving chip 42, a source driving chip 43, and a source driving chip 44. Each of the source driving chips is connected to the timing controller 410. The terminating resistor R is provided at the end of the differential signal line pair 401, not in any of the source driver chips. That is, the termination resistor R is independent of any source driver chip.

As shown in fig. 4, for example, since the terminating resistor R is disposed at the end of the differential signal line pair 401, the trace pair P44 from the output end P of the low voltage differential signal line pair to the source driver chip 44 is difficult to achieve impedance matching, resulting in poor signal integrity.

In the example of fig. 4, the terminating resistor R is provided in the source driver chip SD-4, thereby improving the problem of impedance mismatch of the traces from the output ends of the low-voltage differential signal line pairs to the source driver chip, and improving signal integrity.

In some embodiments of the present disclosure, the at least one source driver chip includes a plurality of source driver chips, i.e., the source driver includes a plurality of source driver chips. The plurality of source driving chips comprise a first driving chip, at least one termination resistor comprises a first termination resistor, the first driving chip comprises a first termination resistor, and the first driving chip is connected with an output end of the object differential signal line pair, which is farthest from the controller.

In this embodiment, the termination resistor is located on the source drive chip furthest from the controller. The arrangement of the terminating resistor on the farthest source driver chip enables impedance matching of the low-voltage differential signal line pair as a whole. If the terminating resistor is arranged on the closer source driving chip and the impedance of the signal line connected with the farther source driving chip is difficult to match, the integrity of the signal obtained by the source driving chip farther from the controller is poorer. The termination resistor is arranged on the source driving chip farthest from the controller, so that the integrity of signals received by the source driving chip farthest from the controller can be improved, and the integrity of signals received by each other source driving chip can be improved.

As shown in fig. 3, the source driver chip SD-4 is the chip farthest from the timing controller TCON among the plurality of source driver chips, and the terminating resistor R1 is disposed in the source driver chip SD-4. The terminating resistor R1 is an example of a first terminating resistor, and the source driver chip SD-4 is an example of a first driver chip.

In some embodiments of the present disclosure, the plurality of source driver chips further include a second driver chip, the at least one termination resistor further includes a second termination resistor, the second driver chip includes a second termination resistor, and the second driver chip is a source driver chip connected to an output terminal of the target differential signal line pair closest to the controller. This embodiment is described below with reference to fig. 5.

Fig. 5 illustrates a schematic diagram of another source driver provided by at least one embodiment of the present disclosure.

As shown in fig. 5, the source driver 500 has a similar structure to that of the source driver shown in fig. 3, except that a termination resistor R2 is further included on the source driver chip SD-1 connected to the output terminal closest to the controller. The terminating resistor R2 is an example of a second terminating resistor, and the source driver chip SD-1 is an example of a second driver chip.

In this embodiment, the terminating resistor R2 and the terminating resistor R1 make impedance matching of the low-voltage differential signal line pair better, and also improve integrity of the signal received by the source driver chip SD-1 in a targeted manner.

Fig. 6 illustrates a schematic diagram of another source driver provided by at least one embodiment of the present disclosure.

As shown in fig. 6, the source driver 600 is similar in structure to the source driver shown in fig. 3, except that each source driver chip includes a termination resistor.

In some embodiments of the present disclosure, each source driver chip connected to the subject differential signal line pair includes one of the at least one termination resistors. For example, each of the source driver chips includes at least one termination resistor, and each of the low-voltage differential signal line pairs in the low-voltage differential signal line pair group is connected to one of the at least one termination resistors.

For example, the source driving chip SD-1 includes a terminating resistor R2, the source driving chip SD-2 includes a terminating resistor R3, the source driving chip SD-3 includes a terminating resistor R4 and the source driving chip SD-4 includes a terminating resistor R1.

Each source driving chip comprises at least one terminating resistor, so that the resistance value of the terminating resistor in the source driving chip impedance batch at each position can be adjusted according to the relative position of the source driving chip, and the signal integrity is better improved.

In some embodiments of the present disclosure, the source driver chip in which the at least one terminating resistor is located includes a resistance value configuration register, and the resistance values of the at least one terminating resistor are configured through the resistance value configuration register respectively. Because the terminating resistor is integrated in the source driving chip, the resistance value of the terminating resistor can be configured by adopting the resistance value configuration register, so that the terminating resistor is conveniently configured, and the applicability is better. For example, the terminating resistor is an adjustable resistor with adjustable resistance, for example, implemented by a resistor string, etc., and the technician can adjust the resistance of the adjustable resistor by changing the value of the resistance configuration register.

In some embodiments of the present disclosure, the improvement of the signal integrity may be the technical solution described in any one of the embodiments of fig. 3 to 6, or other technical solutions may be adopted to improve the signal integrity.

In the above-described respective embodiments, the number of clock signal lines is the same as the number of groups of differential signal line pairs, i.e., a plurality of differential signal lines correspond one-to-one to a plurality of clock signal lines.

After signal integrity is improved, a clock sharing scheme may be employed to further reduce the number of pins required for the timing controller, i.e., multiple sets of differential signal line pairs share one clock signal line.

Fig. 7 is a schematic diagram illustrating a connection relationship between another source driver and a controller according to at least one embodiment of the present disclosure.

In fig. 7, (a), (b), (c), and (d) are another 4 embodiments describing the connection relationship between the controller and the source driver, respectively. The controller is, for example, a timing controller TCON, and the source driver and the timing controller TCON may be connected by any connection means shown in fig. 7 (a) to 7 (d).

As shown in fig. 7 (a) to 7 (d), in the embodiments, the source driver includes a plurality of source driver chips. For example, in the example of fig. 7 (a), the source driver 70 includes at least a source driving chip SD71, a source driving chip SD72, a source driving chip SD73, a source driving chip SD74, and the like.

For example, as shown in fig. 7 (a), each of the plurality of source driving chips is connected to the timing controller TCON through a set of differential signal line pairs 710 for the timing controller TCON to receive a differential signal. For example, the differential signal line pair is a low voltage differential signal line pair that transmits, for example, a low voltage differential signal, mini-LVDS or other differential signal. The embodiment is illustrated by exemplifying the differential signal line pair as a low voltage differential signal line pair in the embodiment of the present disclosure.

Hereinafter, this embodiment will be described by taking an example in which the set of differential signal line pairs 710 includes 3 low-voltage differential signal line pairs.

As shown in fig. 7 (a), each source driving chip is also connected to the timing controller TCON through a clock signal line 720. The clock signal line 720 may be a differential signal line pair formed including two differential signal lines through which a differential signal is transmitted.

For example, the timing controller TCON and the source driver 70 are applied to a display panel for driving a pixel array in the display panel to display an image. In the example of fig. 7 (a), the display panel is, for example, a full high definition panel, the resolution of which is 1920 × 1080, and the refresh frequency of the display panel is 60HZ. As signal transmission techniques advance (e.g., signal integrity is improved, skew of clock and data signals is corrected, etc.), the clock frequency of the clock signal can be significantly increased. For example, the clock frequency of the clock signal CLK is supplied to 600MHZ, and the number of pins PC =1 × 2+3 × 2=8 required for the timing controller TCON in order to reach the refresh frequency 60HZ, that is, 1 pair of clock signal lines (2 signal lines) for transmitting the clock signal and 3 pair of low voltage differential signal lines (6 signal lines) for transmitting the data signal are required.

If the refresh frequency of the display panel is increased to 120HZ, the number of pins of the timing controller TCON needs to be increased to meet the requirement of the refresh frequency when the clock frequency is not changed (600 MHZ) and the number of low-voltage differential signal line pairs in a group of low-voltage differential signal line pairs is not changed (i.e., 3 pairs). Similar to the embodiment shown in fig. 2 (b), the timing controller TCON requires the number of pins PC =2 × 2+3 × 2=16, that is, 2 pairs of clock signal lines (4 signal lines) for transmitting clock signals and 6 pairs of low voltage differential signal lines (12 signal lines) for transmitting data signals.

In some embodiments of the present disclosure, if signal integrity can be greatly improved, the requirements for timing setup and hold times for clock and data signals are relatively marginal, so the present disclosure proposes clock sharing, i.e., two sets of low voltage differential signal line pairs share a clock signal line. An implementation of clock sharing provided by the embodiments of the present disclosure is described below with reference to fig. 7 (b) and 7 (c).

In some embodiments of the present disclosure, the at least one source driver chip includes a plurality of source driver chips, the plurality of source driver chips are divided into a plurality of source driver chip groups, each source driver chip group is connected to the controller through a set of differential signal line pairs, and each source driver chip in at least some of the plurality of source driver chip groups is connected to the same clock signal line.

As shown in fig. 7 (b), the source driver chips are divided into two source driver chip sets, namely a source driver chip set G1 and a source driver chip set G2. The source driving chip set G1 is connected to the timing controller TCON through the low voltage differential signal line group PG1, and the source driving chip set G2 is connected to the timing controller TCON through the low voltage differential signal line group PG 2. The source driver chipset G1 and the source driver chipset G2 share a clock signal line 770.

As shown in fig. 7 (c), the source driver chips are divided into two source driver chip groups, i.e., a source driver chip group G11 and a source driver chip group G21. The source driving chip group G11 is connected to the timing controller TCON through the low voltage differential signal line group PG11, and the source driving chip group G21 is connected to the timing controller TCON through the low voltage differential signal line group PG 21. The source driver chipset G11 and the source driver chipset G21 share the clock signal line 730.

In the examples of fig. 7 (b) and 7 (c), since the source driving chipset and the source driving chipset share the clock signal line, the pin number PC =1 × 2+3 × 2=14 of the timing controller TCON. The number of pins of the timing controller TCON is reduced compared to the embodiments of fig. 2 (b) and 2 (c).

As shown in fig. 7 (b) and 7 (c), the scheme facilitating clock sharing can further reduce the number of pins required by the timing controller, and reduce the production cost.

In some embodiments of the present disclosure, each of the source driver chips in two source driver chip groups adjacent in physical layout is connected to the same clock signal line. Being physically adjacent may for example mean that two source driver chips are located adjacently.

For example, in the example of fig. 7 (d), the resolution of the display panel is 4K, the refresh frequency is 120HZ, and the clock frequency of the clock signal is 1200MHZ, in order to make the signal transmission between the timing controller and the source driver meet the above frequency and resolution requirements and minimize the number of pins required for the timing controller TCON, a clock sharing scheme may be employed.

As shown in fig. 7 (d), the plurality of source driver chips are divided into a plurality of source driver chip groups. The source driving chipsets are a source driving chipset G3, a source driving chipset G4, a source driving chipset G5 and a source driving chipset G6.

The source driver chipset G3 and the source driver chipset G4 are adjacent in physical layout, and the source driver chipset G3 and the source driver chipset G4 share one clock signal line 740, that is, the source driver chipset G3 and the source driver chipset G4 are connected to the same clock signal line 740. The source driver chipset G5 and the source driver chipset G6 are physically adjacent, and the source driver chipset G5 and the source driver chipset G6 share one clock signal line 750, that is, the source driver chipset G5 and the source driver chipset G6 are connected to the same clock signal line 750.

In the example of fig. 7 (d), the number of pins PC =2 × 2+3 × 2 × 4=28 required for the timing controller TCON.

It should be noted that although the termination resistors are all disposed at the ends of the low voltage differential signals in the examples of fig. 7 (a) - (d), in practice, the termination resistors are disposed on the source driver chip for improving signal integrity, that is, the source driver described in any of the embodiments of fig. 3-6 can be applied to the clock sharing scheme described in fig. 7 (a) - (d).

In the embodiments of the present disclosure, the source driver chips sharing a set of differential signal line pairs are divided into one group.

Table one shows the number of pins required for the timing controller TCON in the above-described display panels of the plurality of types (respectively having different refresh rates).

Watch 1

As shown in table one, if the clock signal is transmitted between the timing controller and each source driving chip through, for example, a mini-LVDS signal line pair, and the frequency of the clock signal is typically 300MHZ, the number of pins required for the timing controller TCON in the 4 different types of display panels is 14, 28, 56, and 84, respectively.

If the clock frequency and the signal transmission frequency are increased by transmitting between the timing controller and each source driving chip through the EPmLVDS differential signal line pair (for example, please refer to the description below regarding the EPmLVDS differential signal line pair), for example, the frequency of the clock signal is increased to 600MHZ, 900MHZ, or 1200MHZ, the number of pins required for the timing controller TCON in the 4 different types of display panels is 8, 16, and 32, respectively (please refer to the description of fig. 2 in detail).

If the clock frequency and the signal transmission frequency are increased by transmitting between the timing controller and each source driving chip through the EPmLVDS differential signal line pair, and the terminating resistor is disposed on the source driving chip according to the embodiments shown in fig. 3 to 6, the signal integrity is improved, so that the clock sharing scheme can be applied.

For example, if two sets of source driver chips share one clock signal line, the number of pins required for the timing controller TCON in the 4 different types of display panels is 8, 14, and 28 (please refer to the description of fig. 7 in detail).

As can be seen from comparison, the increase of the clock frequency can reduce the number of pins required by the timing controller TCON, and the clock sharing can further reduce the number of pins required by the timing controller TCON.

In some embodiments of the present disclosure, each group of the low voltage differential signal line pairs transmits data signals to the source driver in at least two modes within one frame display period, the data signals provided by the at least two modes including configuration data and image data, the configuration data being used to configure the source driver such that the source driver processes the image data according to the configuration data. Such a low-voltage differential signal line pair that performs signal transmission in two modes is referred to as an EPmLVDS differential signal line pair in the present disclosure. The differential signal transmitted by the EPmLVDS differential signal line pair conforms to the EPmLVDS signal protocol. The EPmLVDS signaling protocol is a differential protocol proposed by the present disclosure.

Compared with the embodiment that image data is transmitted by using a group of low-voltage differential signal line pairs, the EPmLVDS signaling protocol uses the low-voltage differential signal line pairs to transmit both the image data and the configuration data, realizes the multiplexing of the low-voltage differential signal line pairs, and reduces the pin number on the timing controller and the source driving chip.

The EPmLVDS signaling protocol facilitates offset correction of clock signals and data signals, thereby facilitating the adoption of a clock sharing scheme. For example, the source driving chip acquires a clock signal and a correction signal provided by the timing controller using the low-voltage differential signal line pair; determining a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and adjusting the timing relation between the clock signal and the correction signal by using a delay unit based on the timing offset value to realize offset correction, wherein the delay unit is arranged in a clock path of the clock signal or a data path of the correction signal.

Fig. 8A and 8B are schematic signal formats of a data signal provided by a controller to a source driver according to at least one embodiment of the present disclosure. The data signal conforms to, for example, the EPmLVDS signaling protocol.

As shown in fig. 8A, in one frame display period (including an image display period and a vertical blanking period), the data signal includes a plurality of display sub-signals 801 supplied in a line configuration mode, a display sub-signal 802 supplied in a frame configuration mode, and a display sub-signal 803 supplied in a correction configuration mode.

For example, the plurality of display sub-signals 801 are supplied in a line configuration mode during image display, the display sub-signals 802 are supplied in a frame configuration mode during vertical blanking, and the display sub-signals 803 are supplied in a correction configuration mode.

As shown in fig. 8A, providing data signals to the source driver in at least two modes through the low voltage differential signal interface during one frame display period includes: and during one frame display period, sequentially providing the data signals to the source driver in at least two modes by using the low-voltage differential signal interface, and sequentially providing one or more display sub-signals to the source driver for each mode by using the low-voltage differential signal interface.

For example, in the example of fig. 8A, the plurality of display sub-signals 801 are provided to the source driver in the row configuration mode, the display sub-signals 802 are provided to the source driver in the frame configuration mode, and the display sub-signals 803 are provided to the source driver in the correction configuration mode using the low voltage differential signaling interface. For example, for a row configuration mode including multiple display sub-signals 801, the multiple display sub-signals 801 are provided to the source driver in sequence using a low voltage differential signaling interface. That is, in the example of fig. 8A, the plurality of display sub-signals 801 are provided to the source driver by the low voltage differential signal interface, the display sub-signals 802 are provided to the source driver by the low voltage differential signal interface, and the display sub-signals 803 are provided to the source driver by the low voltage differential signal interface.

As shown in fig. 8A, each display sub-signal 801 provided in the line arrangement mode includes line data LPC and image data (e.g., RGB data). As shown in fig. 8B, the line data LPC includes a pattern recognition signal a and line configuration data. For example, the mode identification signal a includes a RESET signal RESET and a row mode Start signal LPC Start. For example, the row mode start signal may be a logic inactive level, e.g., "000". For the pattern identification signal and the row configuration data of the row configuration pattern, refer to the above description.

As shown in fig. 8A, each display sub-signal 802 provided in the frame configuration mode includes frame data FPC, invalid data IDLE0, and invalid data IDLE1. The display sub-signals provided in the frame configuration mode include data signals 812 provided in the power consumption control sub-mode. As shown in fig. 8B, the frame data FPC includes a pattern recognition signal B and frame configuration data. For example, the pattern recognition signal B of the frame data FPC is a RESET signal RESET and a frame pattern Start signal FPC Start. For example, the frame mode start signal may be different from the row mode start signal, e.g., a logic active level such as "111", to distinguish between the frame configuration mode and the row configuration mode. For the pattern recognition signal and the frame configuration data of the frame configuration pattern, refer to the above description.

As shown in fig. 8A, each display sub-signal 803 provided in the correction configuration mode includes correction data ASC. As shown in fig. 8B, the correction data ASC includes a pattern recognition signal C and a correction signal. The pattern recognition signal C may be, for example, a logic inactive level. For the correction signal, refer to the above description.

As shown in fig. 8A, after the data signal for one frame display period is transmitted to the source driver, the data signal for the next frame display period continues to be transmitted to the source driver.

As shown in fig. 8A, before each display sub signal is supplied to the source driver, a trigger signal PSI for notifying the source driver to perform a transfer operation for at least two modes is supplied to the source driver.

In some embodiments of the present disclosure, the controller may transmit the data signal to the source driver through a single mode in addition to transmitting the data signal to the source driver in at least two modes.

In this embodiment, the trigger signal PSI informs the source driver of the at least two modes of transmission operations to be performed, which facilitates the source driver and the controller to be compatible with other transmission operations than the at least two modes of transmission operations, providing compatibility. For example, a single-mode transmission operation (e.g., transmission mini-LVDS) may be compatibly performed between the controller and the source driver in addition to the transmission operation through at least two modes. If the controller and the source driver execute at least two modes of transmission operation, the controller firstly provides a trigger signal PSI to the source driver as an indication signal of the at least two modes of transmission operation; if the controller and the source driver execute the single-mode transmission operation, the controller firstly provides a single-mode indication signal different from the trigger signal PSI to the source driver.

At least one embodiment of the present disclosure provides a configuration method. This configuration method is applied to any of the source drivers described in fig. 3 to 6.

Fig. 9 shows a flowchart of a configuration method provided by at least one embodiment of the present disclosure.

As shown in fig. 9, the configuration method includes steps S910 and S920.

Step S910: configuration information of at least one termination resistor is obtained.

Step S920: and configuring the resistance value of at least one terminating resistor according to the configuration information.

For step S910, the configuration information of each termination resistance is written to the source driver chip, for example. The configuration information includes the resistance value of the termination resistor. The configuration information of each terminating resistor is input to the resistance value configuration register.

For step S920, for example, the source driver chip where the at least one terminating resistor is located includes a resistance value configuration register, and configures a value of the resistance value configuration register according to the configuration information, so as to configure a resistance value of the at least one terminating resistor.

For example, if the configuration information is 1, the value of the resistance value configuration register is configured to be 1, so that the resistance value of the adjustable resistor is set to be 1. For example, the resistance value corresponding to the 1 st gear is 100 Ω, so that the resistance value of the terminating resistor is set to 100 Ω.

The method enables the resistance value of the terminating resistor to be easy to configure, technicians can flexibly set the resistance value of the terminating resistor, impedance matching is better, and signal integrity is better improved.

Fig. 10 illustrates a schematic block diagram of an electronic device 1000 provided by at least one embodiment of the present disclosure. As shown in fig. 10, the electronic device 1000 includes a controller 1010 and a source driver 1020.

The source driver 1020 includes at least one source driving chip connected with the controller through at least one set of differential signal line pairs to receive differential signals from the controller; at least one of the at least one source driving chip comprises a termination resistor, two ends of the termination resistor are respectively connected to two signal lines of the target differential signal line pair, and the target differential signal line pair is a differential signal line pair in at least one group of differential signal line pairs. Please refer to the above description for the source driver 1020.

As shown in fig. 10, the electronic device 1000 may also include a display panel 1030.

The source driver 1020, for example, performs the signal transmission method described above with respect to fig. 9. The display panel 1030 is, for example, a liquid crystal display panel, an organic light emitting diode display panel, an electronic paper display panel, or the like, and receives a driving signal (i.e., a gray-scale voltage signal) supplied from the source driver 1020 and displays an image.

The electronic device 1000 may be various electronic devices with an image display function, including but not limited to a smart phone, a tablet computer, a notebook computer, a display, a television, a smart wearable product, and the like.

The electronic equipment can enable the transmission of the data stream to be independent of the initial indication signal, thereby avoiding the influence caused by the delay of the initial indication signal in the transmission process and being beneficial to improving the frequency of signal transmission.

Although as described above, there are the following points to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims (12)

1. A source driver, comprising:

at least one source driver chip, wherein the at least one source driver chip is connected with a controller through at least one set of differential signal line pairs to receive differential signals from the controller;

wherein at least one of the at least one source driver chip includes at least one termination resistor, both ends of each termination resistor are respectively connected to two signal lines of an object differential signal line pair in the at least one group of differential signal line pairs,

wherein the termination resistance is configured to impedance match the subject differential signal line pair.

2. The source driver of claim 1, wherein the at least one source driving chip comprises a plurality of source driving chips,

the plurality of source driver chips include a first driver chip, the at least one termination resistor includes a first termination resistor, the first driver chip includes the first termination resistor,

the first driving chip is a source driving chip connected with the output end of the object differential signal line pair, which is farthest from the controller.

3. The source driver of claim 2, wherein the plurality of source driver chips further comprises a second driver chip, the at least one termination resistor further comprises a second termination resistor, the second driver chip comprises the second termination resistor,

the second driving chip is a source driving chip connected with the output end of the object differential signal line pair closest to the controller.

4. The source driver of claim 1, wherein each source driver chip to which the subject differential signal line pair is connected includes one of the at least one termination resistance.

5. The source driver of claim 1, wherein the at least one source driver chip is each connected to the controller by a clock signal line to receive a clock signal from the controller and to receive the differential signal according to the clock signal.

6. The source driver of claim 5, wherein the at least one source driver chip comprises a plurality of source driver chips divided into a plurality of source driver chip groups, each source driver chip group connected with the controller through a set of differential signal line pairs,

each source driving chip in at least part of the source driving chipsets is connected with the same clock signal line.

7. The source driver of claim 6, wherein each of the source driver chips in two source driver chip groups adjacent in physical layout is connected to a same clock signal line.

8. The source driver of any one of claims 1 to 7, wherein the at least one set of differential signal line pairs each transmit a display signal to the source driver in at least two modes within one frame display period,

wherein the display signals provided by the at least two modes include configuration data and image data, the configuration data being used to configure the source driver such that the source driver processes the image data according to the configuration data.

9. The source driver of any one of claims 1 to 7, wherein the source driver chip where the at least one termination resistor is located includes a resistance value configuration register,

the resistance values of the at least one terminating resistor are configured through the resistance value configuration register respectively.

10. A configuration method applied to the source driver according to any one of claims 1 to 7, the method comprising:

acquiring configuration information of the at least one termination resistor; and

and configuring the resistance value of the at least one terminating resistor according to the configuration information.

11. The configuration method according to claim 10, wherein the source driver chip where the at least one termination resistor is located includes a resistance value configuration register,

configuring the resistance value of the at least one terminating resistor according to the configuration information, including:

and configuring the value of the resistance value configuration register according to the configuration information so as to configure the resistance value of the at least one terminating resistor.

12. An electronic device, comprising:

a controller; and

a source driver including at least one source driver chip, wherein the at least one source driver chip is connected with the controller through at least one set of differential signal line pairs to receive differential signals from the controller;

wherein at least one of the at least one source driver chip includes at least one termination resistor, both ends of the termination resistor are respectively connected to two signal lines of an object differential signal line pair in the at least one group of differential signal line pairs,

wherein the termination resistance is configured to impedance match the subject differential signal line pair.

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