TW201314646A - Gate driver device and display therewith - Google Patents

Abstract

A gate driver device and display therewith are introduced herein. The gate driver device comprises an image signal receiving interface, an image processing unit, a timing controller, and a gate driving unit. The image signal receiving interface receives an input signal and transfers the signal to a display image signal and a display control signal. The image processing unit receives the display image signal and transfers the same into a display data. The timing controller receives the display control signal and transfers the same into a first control signal and a signal control signal. The first control signal and the display data are output to a source driver. The gate driving unit receives the second control signal to drive gate scanning lines, where the gate driving unit uses the second control signal to sequentially drive the gate scanning lines, and the source driver supplies the display data to pixels of the display according to the first control signal.

Description

Gate driver and display device having the same

The present invention relates to a driving circuit, and more particularly to a gate driver having a timing control function and a display device including the same.

Conventional display devices include a drive circuit for driving a display panel for display. FIG. 1A shows a schematic diagram of a conventional display device architecture. The display device 100 includes at least one display panel 110, a source driver 120, a gate driver 130, and a timing controller 140.

The timing controller 140 receives the display image data (Display Image Data) and the synchronization signal (Synchronous Signals) via the signal 102, and converts the display image data into a data format acceptable for the output interface, and outputs the data format to the source driver 120. In addition, the control signals required for the source driver 120 and the gate driver 130 are further generated. That is, the timing controller 140 issues a control signal to the latch circuit 150, the source driver 120, the gate driver 130, and the gray scale voltage generating circuit 160 in time series, for example, after reading the image data from the image data memory. And transferred to the latch circuit 150. The timing control circuit 140 further controls the source driver 120 and the gate driver 130 for transmitting image data to the corresponding pixels of the display panel 110 via the source data line 122 and the gate scan line 132, thereby displaying Corresponding image.

FIG. 1B is a schematic diagram showing a connection architecture of the display device of FIG. 1A including a display panel 110, a source driver 120, a gate driver 130, and a timing controller 140. The display panel 110 includes a plurality of pixels (Pixel) 112 arranged in an array. Each pixel 112 includes three primary color red (R), green (G), and blue (B) display spots, corresponding to the source driver 120. One of the source data lines 122 and one of the gate scan lines 132 are driven and displayed by the source driver 120 and the gate driver 130.

The timing controller 140 controls the source driver 120 and the gate driver 130 to control the pixels 112 via the gate scan lines 132 ₁ , 132 ₂ , . . . , 132 _m and via the source data lines 122 ₁ , 122 . ₂ , ..., 122 _3n Transfer the data of the display screen to the pixels of the display panel 110, and display the corresponding image accordingly.

For the display panel 110, the source driver 120 is disposed on one side L, and the gate driver 130 is disposed on the other side H. Generally, the length of the side L is greater than the side H, that is, the source. The number of data lines 122 ₁ , 122 ₂ , ..., 122 _3n is greater than the number of gate scan lines 132 ₁ , 132 ₂ , ..., 132 _m , i.e., 3n > m. Because the source driver 120 must drive the three display spots of the pixel 112, and the gate driver 130 controls the pixels of the parallel column through the gate scan line, the number of source data lines 122 will be greater than the gate scan. The number of lines 132.

In addition, please refer to FIG. 1C , which is a schematic diagram illustrating the assembly structure of the display device 100 of FIG. 1A . The timing controller 140 of the display device 100 is disposed on the Timing Control PCB 170 and includes an input signal port 104 for connecting to an external signal source. The timing control substrate 170 is connected to the gate driving board 172 via the signal bus 171, and the gate driving substrate 172 is provided with a plurality of gate drivers 130, and the configuration can be flexibly soft. A flexible printed circuit (FPC) is attached to the electrical connection. In addition, the timing control substrate 170 may be electrically connected to the source driving substrate 174 by a flexible flexible substrate (FPC), and the source driver 120 may be disposed on the source driving substrate 174.

The architecture and driving method of the conventional display device require a large number of source data lines, and the power consumption required for the source driver to drive the source data line is much larger than the driving gate scan line, plus the source driver. The driving circuit is complicated, and the manufacturing cost of the integrated circuit (IC) is high, resulting in an increase in manufacturing cost of the display device.

In addition, as the resolution of the flat display device increases, the operating frequency of the display device also becomes faster, and the design complexity of the required circuit increases, and the design of each IC unit is different, and the frequency of the timing cycle also increases with the complexity of the circuit. The problem of electromagnetic interference (EMI) has become serious, and in order to save energy and reduce carbon, the reduction of power consumption has always been a problem to be solved by flat display devices.

The invention provides a gate driver having a timing control function and a display device having the same. In the display device, a display panel, at least one source driver, and at least one gate driver are included. The display panel includes a plurality of pixels, each pixel being connected to at least one gate scan line and one source data line. The source drivers are respectively connected to the pixels via the source data lines.

The gate driver includes an image data receiving interface, an image processing unit, a clock control generator, and a gate driving unit. The image data receiving interface is configured to receive an input signal and divide the input signal into a display image data (Display Image Data) and a display control signal. The image processing unit is configured to receive display image data and convert it into a display material. The clock control generator receives the display control signal and converts it into a first control signal and a second control signal, wherein the first control signal and the display data are output to the source driver. The gate driving unit receives the second control signal and drives the gate scan lines accordingly. The gate driver sequentially drives the gate scan line according to the second control signal, and the source driver outputs the display data to the pixels according to the first control signal.

The above described features and advantages of the present invention will be more apparent from the following description.

In the case of a general display device, the requirements for the required components are different due to the different size of the display device. Different display devices on the market have different driving components and timing controllers. In the design of the drive element, the size is related to the cost of manufacturing. Generally, a larger display device has a larger number of output pins required for the resolution improvement IC. Therefore, the gate driving IC, the source driving IC, and the timing control IC are separately manufactured in the display device to avoid display. When the device transmits a signal, the signal is attenuated due to the long distance, which causes the signal to be wrong.

Smaller display devices, due to the shorter length of the transmitted signal, are more concerned with the size of the IC and the number of components used. It is still feasible to divide the timing controller IC, the source driver, and the gate driver into three ICs, but relatively speaking, the number of ICs and the area required to occupy the IC are large, and the cost is lost.

In one embodiment, the present invention discloses a design for integrating timing control functions into a gate driver. In another embodiment, the above-described gate driver having a timing control function has such a configuration that the planar display device drives the longer side to reduce the number of source drivers used, which can reduce the cost.

In an embodiment, the present invention proposes to integrate the function of the timing control into the design of the gate driver. Hereinafter, the gate driver including the timing control function is referred to as a smart gate driver. The advanced gate driver is placed on one side of the display device driving circuit, which is generally represented by the longer side, and is still determined by the number of driving lines required for the side of the display panel in the display device. A larger number of drive lines are required. In the above architecture, the operating frequency of the gate driver is lower than the operating frequency of the source driver, thereby reducing the number of signal lines for high frequency operation while reducing the problem of electromagnetic interference (EMI).

In an embodiment, the present invention proposes to integrate the function of the timing control into the design of the gate driver, effectively processing the synchronization signals of the signals and data timings required to be driven by the liquid crystal display, and accurately transmitting the two signals to have A suitable Common Voltage (V _COM ) display device allows the display device to operate normally.

Based on the above, the present invention proposes to integrate the function of the timing control into the design of the gate driver, which can reduce the cost, improve the electromagnetic interference (EMI) and power consumption and the like. The different embodiments of the present invention will be described below in conjunction with the drawings.

2A is a schematic structural diagram of a display device according to an embodiment of the present invention. The display device 200 includes a display panel 210, a source driver 220, and a gate driver 230 with clock control. The display panel 210 includes a plurality of pixels 212 arranged in an array. Each pixel 212 includes three primary color red (R), green (G), and blue (B) display spots, corresponding to the source driver 220. A source data line 222 and a gate scan line 232 of the gate driver 230 are respectively driven by the source driver 220 and the gate driver 230 with clock control. That is, the pixels 212 are controlled via the gate scan lines 232 ₁ , 232 ₂ , . . . , 232 _3n , and the data of the display screen is displayed via the source data lines 222 ₁ , 222 ₂ , . . . , 222 _m . The pixels are transmitted to the display panel 210, and the corresponding images are displayed accordingly.

In the display device of the present embodiment, the source driver 220 is disposed on one side H, and the gate driver 230 with clock control is disposed on the other side L, wherein the length of the side L is greater than the side H . The 3n gate scan lines 232 ₁ , 232 ₂ , . . . , 232 _3n of the gate driver 230 with clock control are respectively connected to each pixel 212 including three primary colors red (R), green (G), Blue (B) shows the light spot and is used to control the display of the light spots. The source driver 220 supplies the data of the display screen to the pixel display by the m source data lines 222 ₁ , 222 ₂ , . . . , 222 _m , wherein the number of the gate scan lines 232 is greater than The number of source data lines 222.

That is, under the same display device size and resolution requirements, the architecture proposed in this embodiment can effectively reduce the number of source drivers required, and can effectively reduce costs.

In addition, the source driver 220 is coupled to the gate driver 230 with clock control for providing display data and control signals to the source driver 220. The clock driver 230 with the clock control receives external Display Image Data and Synchronous Signals image data, and performs mapping processing on the displayed image data to convert the displayed image data. The data format is acceptable for the output interface, and is output to the source driver 220.

Further, in the architecture proposed by the embodiment, the image signal transmitted by the gate driver with the clock control and the required control signal can be transmitted to the plurality of source drivers in parallel. In the architecture proposed in this embodiment, if multiple gate drivers are used, the gate drivers can be divided into master (slave) configurations, and one or more of the gate drivers are used as the gate driver. The main gate driver, while the other gate driver acts as a slave gate driver. All actions are controlled by the master gate driver, while the other slave drivers are turned off. Based on cost considerations, the architecture proposed in this embodiment uses a two or a single smart gate driver (Smart Gate Driver) for a better cost architecture.

In addition, please refer to FIG. 2B , which is a schematic diagram illustrating the assembly structure of the display device 200 of FIG. 2A . As shown, the Timing Control PCB 270 includes an input signal port 204 for connection to an external signal source. In addition, since the timing control function is built in the gate driver 230, the timing control substrate 270 does not need to be attached with a timing control integrated circuit (IC). The control signal is transmitted to the gate driver 230 having the timing control function by, for example, being electrically connected to the gate driving board 272 by a flexible flexible substrate (FPC). The timing control signal 270 is connected to the source driver 220 via the signal bus 271 on the display panel. The present invention can be configured with a plurality of source drivers 220, which can be configured by connecting the bus bars in parallel on the display panel.

FIG. 3A is a block diagram showing the structure of a display device according to an embodiment of the present invention, relating to a timing control function built into a gate driver. FIG. The gate driver 300 can include an image data receiving interface for receiving signals via the image data link 302. The above signals include, for example, Display Image Data and display control signals, wherein the display control signals include a plurality of control information and at least one Synchronous Signals and the like.

Gate driver 300 is coupled to display panel 380 via gate scan line 304. In addition, the gate driver 300 is coupled to the source driver 370 via the data and control signal bus 306 and provides display image data and a first control signal to the source driver 370. The source driver 370 can be controlled to transmit the display image data to the display panel 380 via the source data line 372 by the control information in the first control signal. The first control information provided to the source driver 370 includes, for example, a vertical data input/output start pulse DIO_V, a vertical polarity inversion control signal (POL_V), a vertical timing pulse CKH_V (CLK_V) supplied to the source driver, and a source driver. The output is analogous to the voltage load to the load control signal Load of the display panel and so on.

The synchronous timing pulse transmitted from the gate driver 300 of the embodiment to the source driver 370 is transmitted by the period of the vertical synchronizing signal. Therefore, the vertical data input and output starting pulse DIO_V supplied to the source driver 370 is vertical. The polarity inversion control signal POL_V, the vertical timing pulse CKH_V supplied to the source driver, is different from the conventional control signal. In addition to having a gate control function for a plurality of pixels in the display panel 380, the gate driver 300 further includes a source driver 370 including image display data and control signals.

In this embodiment, the clocked gate driver 300 includes at least an image data receiving interface 310, a clock control generator 320, a video latch unit 330, a gate driving unit 350, and an output interface 360. .

After receiving the display image data and the display control signal from the image data receiving interface 310, the image data is divided into the display image data 312 and the display control signal 314. This display image material 312 is transferred to the image latch unit 330 and converted into a data format acceptable to the output interface, and output to the source driver 370. The display control signal 314 is transmitted to the clock control generator 320, wherein the display control signal 314 includes, for example, a horizontal synchronizing signal and a vertical synchronizing signal.

First, the display image data 312 is adjusted to be synchronized with the control signal via the image latching unit 330, and then the display image data 312 is converted into an acceptable arrangement of the output interface 360, and then the display data is outputted, and the signals are respectively output via the signal 332. The data is transmitted to the output interface 360, and the display data and control signals are provided to the source driver 370 via the data and control signal bus 306.

The display control signal 314 is sent to the timing control generator 320 to generate the first control signal 322 and the second control signal 324, which are respectively sent to the source driver 370 and the internal gate driving unit 350, wherein the second control signal The 324 includes a Horizontal Start Pulse (ST_H), a Gate Driver Output Enable (OE_H) signal, and a Horizontal Clock (CLK_H).

FIG. 3B is a block diagram showing a circuit of a gate driver having a timing control function according to an embodiment of the present invention. In this embodiment, the gate driving unit 350 includes a control logic unit 351, a bidirectional displacement unit 353, a level shifting unit 355, and an output buffer 357.

After the system is started, the second control signal 324 is received by the control logic unit 351. After the control logic unit 351 completes the reception, the control signal is sent to the bidirectional displacement unit 353. Then, the bidirectional displacement unit 353 determines whether the scanning direction is left or right. In the sequential scan, the level shifting unit 355 adjusts the alignment bits appropriately. Finally, the buffer 357 controls the sequential output to the display panel.

For the data processing flow of the gate driver control signal 324, as shown in FIG. 3C, after the power is connected to the overall display device, the gate driver starts the signal processing S300, and the control signal is sent from the timing control generator 320 to the gate driving unit. At 350 o'clock, the processing of the reception control signal is started. In step S302, the obtained result is sent to the control logic unit 351 for processing control logic processing. Next, the shift direction is determined by the bidirectional displacement unit 353. If the scan direction is determined to be rightward, the signal that is output to the right by the bidirectional displacement unit 353 is output, as in step S308. Otherwise, step S310 is performed to output a signal for shifting to the left to obtain a sequentially scanned signal, which is sent to the level shifting unit 355. The level shifting unit 355 performs the level adjustment. In step S312, the signal voltage level of the sequential scan is converted into a voltage required by the display device, and the scan signal is output. The buffer 357 is configured to buffer output, and sequentially output the scan signals passing through the level shifting unit, as in step S314. Finally, the output gate pulse signals are executed one by one to the gate scan lines of the display device, and finally sent to the display panel, as in step S316.

Please refer to FIG. 3D for explaining the architecture of the display device proposed in another embodiment of the present invention. The same portions of the gate driver 300A and the gate driver 300 of FIG. 3A are denoted by the same reference numerals, and different portions will be described herein. The gate driver 300A with clock control of the present embodiment also has an image data receiving interface 310, a clock control generator 320, an image latching unit 330, a gate driving unit 350, and an output interface 360. In addition, the clock driver 300A of the present embodiment further includes a memory unit 390 and an image data mapping unit 392 connected thereto.

The display image data 312 received by the image data receiving interface 310 can be applied to the source driver 370 without being converted, in an embodiment, as shown in FIG. 3A. However, in another embodiment, the received display image data 312 does not meet the requirements in the format. Therefore, further conversion of the display data is required. For example, the gate driver 300A with clock control is provided in conjunction with the embodiment. The data providing format requires an additional mapping of the image data mapping. The received display image data 312 must first be mapped and converted. In an embodiment, the image data can be transferred to the image data map via the memory unit 390. The processing performed by the unit 392 is performed, and the mapped display image data 391 is transmitted to the image latch unit 330.

Please refer to Figures 4-1 and 4-2 for a timing diagram of the conventional timing controller transmitting control signals and image display data to the source driver. In Figure 4-1, after receiving the horizontal synchronizing signal (Hsync) and the horizontal clock signal CLKi, the period during which the data is transmitted will be entered. During this period, the source driver will according to the received control signal. The display data is transferred to the corresponding data lines (Data Lines) on the panel. For example, in a horizontal interval (Horizontal Periodic), that is, the data transmission time of a data line, as shown in T1 to T2 of Figure 4-1, according to the frequency of the operation clock (CLKi), data enable (Data Enable, such as After the DE clock of the figure, during the data transmission of the horizontal synchronization signal, for example, during the period when the data enables the active pulse width, the input image RGB data is received, that is, the first column of the three primary colors on the panel (R) is provided. ), green (G), blue (B) display the data of the light spot, for example, B11, B12, . . . B1n which displays the light spot to blue (B), or G11 which displays the light spot to green (G), G12, . . . G1n, or R11, R12, . . . R1n of the red (R) display spot. In each subsequent horizontal interval (Horizontal Periodic), the display data of each column of pixels is sequentially received. In Figure 4-2, the display data of each column of pixels is successively received, and the display data is sequentially transmitted to the pixels on the corresponding Data Lines on the panel via the source driver.

Please refer to Figure 4-3 for a timing diagram of the conventional timing controller transmitting control signals to the gate drivers. According to the pulse of the vertical sync signal, it will enter the period during which the data is transmitted, for example, the period during which the data enables the active pulse width. At this time, the gate driver receives the vertical start pulse (ST_V), the gate driver output enable (Output Enable (OE_V) signal, and the vertical clock signal (Clock, CLK_V). The gate driver will not provide the gate line signal when the output enable (OE_V) signal is at the logic low level, and output the control signal to the corresponding gate line when the output enable (OE_V) signal is at the logic high level. The pulse signal is applied to each gate line to drive the corresponding pixels in the panel, such as the gate lines GL1, GL2, GL3, ... GLm.

Referring to FIG. 5-1 to FIG. 5-3, a gate driver with clock control is provided for transmitting a control signal and image display data to a source driver, and providing a pulse signal to each gate line for illustrating a gate driver according to an embodiment of the present invention. A timing diagram of the corresponding pixels in the driver panel.

Different from the conventional architecture, the control signal transmitted by the gate driver of the clock control to the gate lines is based on a vertical synchronizing signal (Vsync) and a vertical clock signal (Clock). , CLK_V) is issued in sequence, as shown in Figure 5-1. In the embodiment of the present invention, the synchronous timing pulse transmitted by the clock driver of the clock control to the source driver is transmitted by the enable period of the vertical sync signal (Vsync), and therefore, the control signal provided to the source driver includes The vertical data input and output start pulse DIO_V, the vertical polarity inversion control signal POL_V, and the vertical timing pulse CKH_V are different from the conventional control signals, as shown in Figures 5-2 and 5-3.

Referring to Figure 5-1, during the enable period of the vertical synchronizing signal (Vsync), a period during which data is transmitted, such as the period of Data Enable Active Pulse Width, is entered. . At this time, in each horizontal interval (Horizontal Periodic), the gate driver receives the Start Pulse (ST_H), the Gate Driver Output Enable (OE_H) signal, and the horizontal clock signal (Clock). , CLK_H). The gate driver will not provide the gate line signal when the output enable (OE_H) signal is at the logic low level, and the output enable signal (OE_H) signal is at the logic high level, output the control signal to the corresponding gate line, and successively transmit the pulse. The signal is given to each gate line for driving the corresponding pixels in the panel, such as the gate lines GL1, GL2, GL3, ... GL3n in the figure.

According to an embodiment of the display device according to an embodiment of the invention, the source driver is disposed on one side H, and the gate driver with clock control is disposed on the other side L, wherein the length of the side L is greater than Side H. The 3n gate scan lines of the gate driver with clock control are respectively connected to each pixel including three primary colors red (R), green (G), blue (B) display spots, and are used to control the opening of the pixels. Show light spots. The source driver supplies the display data to the pixel display through the m source data lines, wherein the number of gate scan lines is greater than the number of source data lines.

Referring to FIGS. 5-2 and 5-3, the synchronous timing pulse transmitted by the clock driver of the clock control to the source driver is transmitted by the vertical sync signal (Vsync) during the embodiment of the present invention, and therefore, is vertical. The data of the synchronous signal enables the external input of the image RGB data during the active pulse width. For example, the graphic is provided to the first column to the mth column to display the data, for example, the display data of the first column of pixels, including blue. (B) shows B11, B12, . . . B1n of the light spot, green (G) shows G11, G12, ....G1n of the light spot, and R1, R12, .. of the red (R) display spot. ..R1n. Then, the sequence is displayed until the display data of the mth column, including blue (B) showing Bm1, Bm2, .... Bmn, and green (G) showing Gm1, Gm2, .... Gmn, and red (R) show Rm1, Rm2, ....Rmn of the spot.

In the embodiment of the present invention, the gate driver having the timing control function does not need to perform data conversion if the received display image data conforms to a predetermined format. However, if the display image data does not conform to the format, an additional image data mapping conversion is required. This is the case as shown in Figure 5-2.

As shown in the figure, the received display image data is display data to be provided for each column of pixels, and the display data including the red (R) display spot is R11~R1n, R21~R2n, and up to Rm1~Rmn. Blue (B) shows the display data B11~B1n, B21~B2n of the light spot, up to Bm1~Bmn, and the display data G11~G1n, G21~G2n of the green (G) display spot to Gm1~Gmn. Due to the received display image data, as shown in the figure, the conversion is required. Therefore, the data mapping (Mapping) operation is converted to the lower half of Figure 5-2, and the data R11~R1n, R21~ will be displayed. R2n, until Rm1~Rmn is converted into the first group R11, R21, R31, the second group R41, R51, R61 arranged by the RGB data bus, until Rm1, this is only the display data of the first column. Displaying the display data of the first column of pixels for the red (R) display spot, including R11, R21, and R31 until the Rm1 transmission is completed, and then displaying the light spot for the green (G) of the first column of pixels. A list shows the data for transmission.

Similarly, the display data G11~G1n, G21~G2n are transferred from Gm1~Gmn to the data arranged by the RGB data bus, respectively, as shown in the figure, the first group G11, G21, G31, the second group G41, G51 , G61, up to Gm1, this is only the display data of the first column. Next, the display data for the blue (B) display spot of the first column of pixels is transmitted. Similarly, the display data B11~B1n, B21~B2n are transferred from Bm1~Bmn to the data arranged by the RGB data bus, respectively, as shown in the figure, the first group B11, B21, B31, the second group B41, B51 , B61, up to Bm1, this is only the display data of the first column.

Between time T1 and T2, the source driver receives the control signals according to the vertical data input and output start pulse DIO_V, the vertical polarity inversion control signal POL_V, and the vertical timing pulse CKH_V, and sequentially receives the pixels of each column. The data is displayed, and the display data is sequentially transmitted to the pixels on the corresponding data lines (Data Lines) on the panel via the source driver.

According to the above-mentioned data mapping (Mapping) conversion, and the transmission through the RGB data bus, the data of the first column to the last column can be sequentially transferred. The gate driver proposed in the embodiment of the present invention can receive image data to be displayed in addition to having a timing control function, and further converts if necessary. Then, the displayed image data and the control signal are transmitted to the source driver for display.

As shown in FIG. 5-3, the embodiment of the present invention provides a gate driver with clock control, and a synchronous timing pulse transmitted to a source driver is transmitted by an enable period of a vertical sync signal (Vsync), and thus is provided to the source. The driver signal of the pole driver includes a vertical data input and output start pulse DIO_V, a vertical polarity inversion control signal POL_V, and a vertical timing pulse CKH_V.

For the data received by the RGB data bus, taking the display data of the first column as an example, the first column of the red (R) display spot includes B11, B21, B31, B41, B51, B61, ..., Bm1 is transmitted to the display panel via the data lines SL1, SL2, SL3, ..., SLm of the source driver, respectively. Then, the first column display data about the green (G) display spot includes G11, G21, G31, G41, G51, G61, ..., Gm1, and the first column display information about the blue (B) display spot includes B11. B21, B31, B41, B51, B61, ..., Bm1 are also sequentially transmitted to the display panel via the data lines SL1, SL2, SL3, ..., SLm of the source driver.

In summary, in the display device component, since the source driver is higher in complexity than the gate driver due to the complexity of the internal circuit, and the number of components required is more than the gate driver, in terms of cost, if Increasing the number of source drivers will increase the cost a lot. However, the architecture of the present invention is such that the source driver is placed on the H side of the display with a smaller number of scan lines, and the gate driver is placed on the L side of the display with a larger number of scan lines, compared to the conventional architecture. It can achieve the effect of streamlining costs.

Furthermore, since the gate driver cost is lower than that of the source driver, and the gate driver operates at a much lower frequency than the source driver, the electromagnetic interference (EMI) problem can be greatly improved. In addition, the power consumption of the gate driver is much smaller than that of the source driver, so the overall system power can be greatly reduced, meeting the needs of environmental protection and energy-saving products. This architecture not only reduces the number of components required for the IC and its internals, but also simplifies the wiring configuration of the overall display device board, which can be quite significant for the design and manufacturing cost of small and medium-sized display devices.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Display device

102. . . Signal

110. . . Display panel

120. . . Source Driver

122. . . Source data line

130. . . Gate Driver (Gate Driver)

132. . . Gate scan line

140. . . Timing Controller

150. . . Latch circuit

112. . . Pixel

L. . . Long side

H. . . Short side

170. . . Timing Control PCB

171. . . Signal bus

172. . . Gate Driving Board

174. . . Source drive substrate

200. . . Display device

210. . . Display panel

212. . . Pixel

220. . . Source driver

222. . . Source data line

230. . . Gate driver with clock control

232. . . Gate scan line

270. . . Timing Control PCB

271. . . Signal bus

272. . . Gate Driving Board

274. . . Source drive substrate

300, 300A. . . Gate driver

302. . . Image data cable

304. . . Gate scan line

380. . . Display panel

306. . . Data and control signal bus

310. . . Image data receiving interface

312. . . Display image data

314. . . Display control signal

320. . . Clock control generator

322. . . First control signal

324. . . Second control signal

330. . . Image latch (Latch) unit

350. . . Gate drive unit

353. . . Bidirectional displacement unit

355. . . Position displacement unit

357. . . Output buffer

360. . . Output interface

370. . . Source driver

372. . . Source data line

390. . . Memory unit

392. . . Image data mapping unit

FIG. 1A shows a schematic diagram of a conventional display device architecture.

FIG. 1B is a schematic diagram showing the connection structure of the display device, the source driver, the gate driver, and the timing controller in the display device of FIG. 1A.

FIG. 1C is a schematic view showing the assembly structure of the display device of FIG. 1A.

FIG. 2A is a schematic diagram showing the structure of a display device according to an embodiment of the present invention.

FIG. 2B is a schematic view showing the assembly structure of the display device of FIG. 2A.

3A is a block diagram showing a circuit of a gate driver in an embodiment of the invention.

3B is a block diagram showing the circuit of the gate driving unit in the gate driver of FIG. 3A.

FIG. 3C is a schematic flow chart showing the data processing of the control signal in the gate driver of FIG. 3A. FIG.

3D is a block diagram showing the circuit of a gate driver in an embodiment of the invention.

Figures 4-1 and 4-2 are timing diagrams illustrating the transmission of control signals and image display data from a conventional timing controller to a source driver.

Figure 4-3 is a timing diagram illustrating the transfer of control signals from a conventional timing controller to a gate driver.

FIG. 5-1 is a timing diagram illustrating a gate driver with clock control according to an embodiment of the present invention, transmitting control signals and image display data to a source driver.

5-2 and 5-3 are timing diagrams illustrating a gate driver with clock control according to an embodiment of the present invention, which provides pulse signals to each gate line to drive corresponding pixels in the panel.

300. . . Gate driver

302. . . Image data cable

304. . . Gate scan line

306. . . Data and control signal bus

310. . . Image data receiving interface

312. . . Display image data

320. . . Clock control generator

330. . . Image latch (Latch) unit

350. . . Gate drive unit

360. . . Output interface

370. . . Source driver

372. . . Source data line

380. . . Display panel

Claims (13)

A gate driver is applicable to a panel, the gate driver includes: an image data receiving interface for receiving an input signal, thereby generating a display image data and a display control signal; and an image latching unit for Displaying the image data to generate a display data; a clock control generator receiving the display control signal to generate a first control signal and a second control signal, and during the period of enabling a vertical synchronization signal, the first The control signal and the display data are output to a source driver, wherein the source driver is disposed on a first side of the panel; and a gate driving unit is disposed on a second side of the panel The second control signal is received to drive the plurality of gate scan lines, wherein the second side is larger than the first side. The gate driver of claim 1, wherein the panel comprises a plurality of pixels respectively corresponding to one of the gate scan lines and one of the source data lines, wherein the sources The pole data line, according to the first control signal, causes the source driver to control outputting the display data to the pixels. The gate driver of claim 1, wherein the first control signal comprises a vertical data input and output start pulse, a vertical polarity inversion control signal, and a vertical timing pulse. The gate driver of claim 1, wherein the gate driving unit comprises: a control logic unit for receiving the second control signal, thereby outputting a signal; and a bidirectional displacement unit for receiving the Signal, and determine the starting direction of the scanning direction is left or right; a level shifting unit, according to the scanning direction of the bidirectional displacement unit, is used to adjust the voltage level of the signal, thereby outputting a scanning signal; And an output buffer for receiving the scan signal of the level shifting unit, and sequentially outputting the scan signal to drive the gate scan lines. The gate driver of claim 1, wherein the second control signal comprises a horizontal start pulse, a gate driver output enable signal, and a horizontal clock signal. The gate driver of claim 1, further comprising an output interface for receiving the display data and the first control signal, and outputting the signal to the source driver. The gate driver of claim 1, wherein the image data receiving interface and the image latching unit further comprise a memory unit connected to the image data receiving interface for temporarily storing the image data receiving interface Displaying image data; and an image data mapping unit connected to the memory unit for reading the display image data temporarily stored in the memory unit, and converting the image data into a mapping display image, and outputting to the image latching unit The image latching unit displays the image data according to the mapping, and generates the displayed data. A display device includes a display panel, the display panel includes a plurality of pixels connected to a gate scan line and a source data line, and the display device includes: a source driver disposed on the display panel One of the first sides is respectively connected to the pixels through the source data lines; and a gate driver is disposed on a second side of the panel, wherein the second side is larger than the first side On one side, the gate driver includes an image data receiving interface for receiving an input signal to generate a display image data and a display control signal, and an image latching unit for generating a image according to the displayed image data. Displaying data; a clock control generator receives the display control signal to generate a first control signal and a second control signal, wherein the first control signal and the display are enabled during a vertical synchronization signal enable period Data is output to the source driver, and the source driver outputs the display data to the pixels according to the first control signal; and a gate driving unit, To receive the second control signal, thereby sequentially driving the plurality of scanning lines gate. The display device of claim 8, wherein the first control signal comprises a vertical data input/output start pulse, a vertical polarity inversion control signal, and a vertical timing pulse. The display device of claim 8, wherein the gate driving unit comprises: a control logic unit, receiving the second control signal transmitted by the timing control generator, and outputting a signal; a displacement unit connected to the control logic unit for receiving the signal, thereby determining whether the start of the scan direction is left or right; and a level shifting unit for adjusting the voltage level of the signal according to the scan direction, And outputting a scan signal; and an output buffer, receiving the scan signal, and sequentially outputting the scan signal to drive the gate scan lines. The display device of claim 8, wherein the second control signal comprises at least a horizontal start pulse, a gate driver output enable signal, and a horizontal clock signal. The display device of claim 8, wherein the gate driver further comprises an output interface for receiving the display data and the first control signal, and outputting the signal to the source driver. The display device of claim 8, wherein the image data receiving interface and the image latching unit further comprise a memory unit connected to the image data receiving interface for temporarily storing the display And the image data mapping unit is connected to the memory unit for reading the display image data temporarily stored in the memory unit, and converting the image data into a mapping display image, and outputting the image data to the image latching unit. The image latching unit displays the image data according to the mapping, and generates the displayed data.