JP2001015756A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an MOSFET of an SOI structure having a gate electrode structure in which threshold can be easily controlled and low gate resistance can be easily realized, by forming a gate electrode consisting of a laminated layer containing of a titanium nitride layer and a metal layer having a high melting point. SOLUTION: The threshold of an MOSFET is determined by the work function of a TiN constituting a TiN layer and an impurity concentration of an Si layer. Since the work function of silicon is near the center of bandgap of the silicon in both the cases of NMOSFET and PMOSFET, the thresholds can be controlled to an appropriate. In this case, if the thresholds of NMOSFET and PMOSFET are 0.3 V and -0.3 V respectively, the impurity concentration of the Si layer is approximately 1×1015 cm3, and no special channel doping is required. Accordingly, this facilitates control of the threshold of the MOSFET of an SOI structure by a gate electrode having a laminated structure, and possible to reduce the gate resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of semiconductor devices, and more particularly, to a semiconductor device having an SOI structure.
It relates to OSFET.

[0002]

2. Description of the Related Art An SOI which is advantageous for reducing the power consumption and increasing the speed of a semiconductor integrated circuit.
The device is partially depleted (Partially Deployed).
eted) type and fully depleted (Fully Deplete)
d) type, and the fully depleted type has an advantage that both the short channel effect and the kink effect can be suppressed. However, it is difficult to control the threshold voltage of the fully depleted type.

Conventionally, the threshold value of a MOSFET having an SOI structure is such that channel doping and n ⁺ −
It was controlled by a combination with a PolySi gate or a p ⁺ -PolySi gate. However, when the channel doping concentration increases as the element becomes finer, the dependence of the threshold value on the channel concentration also increases, making it difficult to control the threshold value. Furthermore, the threshold also depends on the thickness of the SOI layer.

In order to solve these problems, as shown in IEICE Technical Report SDM98-129 (1998-08) p41, a material whose work function is almost at the center of the band gap of Si (mid-gap material) is used. It has been proposed to use it as a gate electrode material. SO actually manufactured
The gate electrode of the I-structure MOSFET is TiN /
There are an n ⁺ -PolySi laminated structure and a Tawith Si cap structure.

However, in the above conventional example using Ta, if a heat treatment at 800 ° C. or more is performed after the gate electrode is formed, the Ta / SiO ₂ interface reacts or Ta diffuses or permeates into SiO ₂ to reduce the carrier lifetime. And increase surface recombination. For this reason, the heat treatment temperature after forming the gate electrode is limited to 700 ° C. or less. This is a constraint on subsequent processes.

On the other hand, the above-described conventional TiN / n ⁺ -Pol
In the case of the ySi laminated structure, the diffusion and transmission of Ti into SiO ₂ can be suppressed, but there is a problem that the sheet resistance of the gate electrode is large.

Therefore, an object of the present invention is to provide a gate electrode structure which can be manufactured by high-temperature heat treatment at about 800 ° C. after formation of a gate electrode, can easily control a threshold value, and can easily realize a low gate resistance. It is to form a MOSFET having an SOI structure.

[0008]

According to the present invention, there is provided an MOI having an SOI structure.
An SFET, in which titanium nitride (Ti
A semiconductor device is provided, wherein a gate electrode is formed of a laminated film including an N) layer and a refractory metal layer on the titanium nitride layer.

In one embodiment of the present invention, the thickness of the titanium nitride layer is 10 nm or more and 50 nm or less, and the thickness of the high melting point metal layer is 100 nm or more and 250 nm or less.

In one embodiment of the present invention, the high melting point metal constituting the high melting point metal layer is any of tantalum, molybdenum and zirconium or an alloy containing the same.

In one embodiment of the present invention, the high-melting-point metal layer comprises a laminated film of a plurality of types of high-melting-point metal layers.

In one embodiment of the present invention, the titanium nitride layer protrudes laterally with respect to the refractory metal layer, and extends above the source / drain extension.

In the above structure, the TiN layer of the gate electrode serves as a mid-gap material to facilitate the control of the threshold value of the SOI MOSFET, and, based on its excellent barrier properties, the gate oxide film and the channel region of the constituent material of the upper refractory metal layer. Suppress diffusion to In addition, it is possible to prevent implanted boron from penetrating the gate oxide film during manufacturing. The refractory metal in the upper layer of the gate electrode enables the reduction of the gate resistance and the high-temperature heat treatment (~ 800
° C). In addition, high melting point metals (including alloys) such as Ta, Mo, and Zr have corrosion resistance to sulfuric acid, phosphoric acid, and acetic acid, and therefore have excellent compatibility with Co etch-off in the Co salicide process.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of a semiconductor device according to the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic sectional view showing the structure of a first embodiment of a MOSFET as a semiconductor device according to the present invention.

In FIG. 1, 1 is a Si substrate, 2 is a buried oxide film, 3 is a field oxide film, and the field oxide film 3 is in contact with the buried oxide film 2. 4
Is a Si layer (SOI layer), and 5 is a gate oxide film as a gate insulating film. Reference numeral 6 denotes a titanium nitride layer (TiN layer) made of titanium nitride (TiN), which is a mid-gap material for controlling the threshold value of the MOSFET. Reference numeral 7 denotes a refractory metal layer for reducing the resistance of the gate electrode. The refractory metal layer 7 is made of tantalum (Ta), molybdenum (Mo), zirconium (Zr), or the like. A gate electrode is constituted by a laminated film of the TiN layer 6 and the refractory metal layer 7.

Reference numeral 10 denotes a source / drain (high-concentration impurity diffusion layer), 8 denotes its extension (low-concentration impurity diffusion layer), and 9 denotes a side spacer (sidewall). 11 is a CoSi ₂ layer, and 12 is a CVD
By a SiO ₂ containing layer formed, the SiO ₂ containing layer 12 NSG, and the like BPSG. 13 is Ti
N is a barrier metal layer, 14 is a W plug, 15 is an Al wiring, 16 is an antireflection film made of TiN, and 17 is a passivation film (P-SiN) made of silicon nitride.

Next, the manufacturing process of the apparatus of this embodiment is shown in FIG.
This will be described with reference to FIGS.

First, as shown in FIG. 2, a Si substrate 1, a buried oxide film 2, a field oxide film 3, a Si layer 4, and a gate oxide film 5 are formed. TiN is formed on the oxide film 5 to a thickness of about 40 nm by sputtering or CVD to form a TiN layer 6, and then a refractory metal (Ta,
Mo, Zr, etc.) by sputtering or CVD.
The refractory metal layer 7 is formed to a thickness of about 0 nm.

The lower limit of the thickness of the TiN layer 6 is preferably 10 nm or more in order to obtain a required barrier property with TiN. In addition, the upper limit of the thickness of the TiN layer 6 is restricted in terms of the total gate electrode thickness and gate resistance including the refractory metal layer 7 and the TiN layer 6. Furthermore,
In consideration of gate etching, formation of sidewalls, and the like, the thickness of the gate electrode is preferably 200 nm or more and 250 nm or less. In terms of lowering the gate resistance, TiN
It is preferable that the layer 6 is thin and the refractory metal layer 7 is thick. These determine the upper limit of the thickness of the TiN layer. When the TiN layer 6 and the refractory metal layer 7 are selectively etched in the subsequent steps, the underlying TiN layer 6 needs to have a certain thickness. From the above points, the thickness of the TiN layer 6 is 10 n
m to 50 nm, and the thickness of the refractory metal layer 7 is 100
A combination in which the total gate electrode thickness is 200 nm or more and 250 nm or less is preferable.

Thereafter, a photoresist pattern layer 18 having a shape corresponding to a desired gate electrode shape is formed at a desired position.

Next, as shown in FIG. 3, photolithography is performed using the photoresist pattern layer 18 as a mask to form the TiN layer 6 and the refractory metal layer 7.
Is etched to form a gate electrode composed of a stacked film of the TiN layer 6 and the refractory metal layer 7. Subsequently, using the gate electrode as a mask, source / drain extensions 8
Is performed.

Next, as shown in FIG. 4, a side spacer 9 is formed, the gate oxide film at the exposed portion is removed, and impurity ions are implanted to form a source / drain 10.
After the heat treatment for activating the implanted impurity, a Co salicide process is performed. At this time, the refractory metal layer 7 is not etched by using a liquid containing phosphoric acid and acetic acid as main components as an etchant used for etching off Co.
FIG. 4 shows a state after the 1st (RTA) annealing in the Co salicide step, where 19 is a Co layer, and 20 is a TiN layer for preventing oxidation of the Co layer 19. At this stage, a CoSi (monosilicide) layer 11 is formed on the surface of the source / drain 10. The first (RTA) annealing temperature is set to a temperature at which Co and the high melting point metal do not react (4
Since the temperature is in the range of 100 to 450 ° C.), no alloy layer is formed on the gate electrode.

FIG. 5 shows a cross section after Co etching off. Thereafter, in the same manner as in the normal Si wafer process,
O ₂ -containing layer 12, barrier metal layer 13, W plug 14,
Al wiring 15, antireflection film 16, passivation film 17
To form a structure as shown in FIG.

In this embodiment, the threshold value of the MOSFET is T
It is determined by the work function of TiN constituting the iN layer 6 and the impurity concentration of the Si layer 4. Since the work function of TiN is near the center (mid gap) of the band gap of silicon, it is shown in FIG. As described above, in the case of both the NMOSFET and the PMOSFET, it is possible to control the threshold value to an appropriate value with a low concentration of impurities. In FIG. 16, Nsub is S
Vth indicates the impurity concentration (substrate impurity concentration) of the i-layer 4.
Indicates a threshold value. When the threshold values of the NMOSFET and the PMOSFET are 0.3 V and -0.3 V, respectively,
The impurity concentration (channel concentration) of the layer 4 is 1 × 10 ¹⁵ cm ^−3.
And no special channel doping is required (N
Only the formation of a well or a P well is possible).

The sheet resistance of the gate electrode is TiN
The thickness of the layer 6 is 40 nm, and the thickness of the refractory metal layer 7 is 20
0 nm, 0.3 Ω / □ when Mo is used as the high melting point metal, 0.7 Ω / □ when Ta is used, Z
When r is used, 2.2 Ω / □ can be realized.

Further, the barrier property of the TiN layer 6 can prevent boron from penetrating through the gate oxide film when performing p ⁺ source / drain ion implantation by gate self-alignment, which is a problem particularly in PMOSFET. Also, Ti
Due to the barrier property of the N layer 6, even if the refractory metal layer 7 is laminated to lower the gate resistance, it is possible to prevent the characteristic deterioration due to the subsequent heat treatment.

As described above, according to the present embodiment, Ti
By using a gate electrode having a laminated structure of the N layer 6 and the high melting point metal layer 7, the threshold control of the MOSFET having the SOI structure becomes easy for both the NMOS and the PMOS.
Gate resistance can be reduced.

(Second Embodiment) FIG. 6 is a schematic sectional view showing the structure of a MOSFET as a semiconductor device according to a second embodiment of the present invention. In this figure, the same parts as those in FIGS. 1 to 5 are denoted by the same reference numerals.

In this embodiment, an alloy layer 21 made of an alloy of a high melting point metal (Ta, Mo, Zr, etc.) and Co is formed on the high melting point metal layer 7. The refractory metal layer 7 and the alloy layer 21 constitute the refractory metal layer of the present invention.

Next, the manufacturing process of the device of this embodiment will be described with reference to FIG.
This will be described with reference to FIGS.

First, as in the first embodiment,
Photoresist pattern layer 1 of the form shown in FIG.
Steps before the formation of 8 are performed. And 1stRT
By performing the A-annealing at a temperature in the range of 450 to 550 ° C., the high-melting-point metal and Co react on the surface of the high-melting-point metal layer 7 to form the alloy layer 21.

Next, a photoresist pattern layer 18 having a shape corresponding to a desired gate electrode shape is formed at a desired position, and photolithography is performed using the photoresist pattern layer 18 as a mask to form the TiN layer 6 and the refractory metal layer. 7 and the alloy layer 21 thereon are etched,
A gate electrode including the TiN layer 6, the refractory metal layer 7, and the alloy layer 21 is formed.

Subsequently, ion implantation of source / drain extensions 8 is performed using the gate electrode as a mask.
Thereafter, by performing the same steps as those in the first embodiment, the form shown in FIG. 8 is obtained after the Co etch-off, and the structure as shown in FIG. 6 is further obtained.

In the present embodiment, since the gate electrode has the alloy layer 21 made of an alloy of a high melting point metal and Co on the upper surface, it is possible to suppress the oxidation of the gate electrode and the occlusion of hydrogen during hydrogen alloying to prevent the deterioration of the characteristics. Can be.

(Third Embodiment) FIG. 9 is a schematic sectional view showing the structure of a MOSFET as a semiconductor device according to a third embodiment of the present invention. In this figure, the same parts as those in FIGS. 1 to 8 are denoted by the same reference numerals.

In this embodiment, the gate electrode has a T
The iN layer 6 is formed larger than the refractory metal layer 7 and protrudes laterally with respect to the refractory metal layer 7, that is, has a gate overlap drain structure.

Next, the manufacturing process of the device of this embodiment is shown in FIG.
This will be described with reference to 0 to 12.

First, as in the first embodiment,
Obtain the configuration shown in FIG. Then, the high melting point metal layer 7 is etched by performing photolithography using the photoresist pattern layer 18 as a mask. At the time of this etching, the TiN layer 6 is left by using a condition with a high selectivity ratio of the refractory metal to TiN.

Next, as shown in FIG. 12, ion implantation of source / drain extensions 8 is performed using the high melting point metal layer 7 as a mask. This ion implantation
This is performed through the TiN layer 6.

Next, as shown in FIG. 11, a first sidewall 22 is formed. The thickness of the sidewall 22 is thinner than a normal sidewall. Thereafter, the TiN layer 6 is etched by dry etching or wet etching using the refractory metal layer 7 and the first sidewall 22 as a mask.

Next, as shown in FIG. 12, a second side wall 22 and a second
The side wall 23 is formed. Thereby, a part of the TiN layer 6 of the gate electrode overlaps with the source / drain extension region 8.

Thereafter, steps similar to those of the first embodiment are performed to obtain a structure as shown in FIG.

In this embodiment, the TiN layer 6 of the gate electrode
Are located above and overlap the source / drain extensions, so that the hot carrier resistance is improved and the drive capability of the MOSFET is also improved.

(Fourth Embodiment) FIG. 13 is a schematic sectional view showing the structure of a fourth embodiment of a MOSFET as a semiconductor device according to the present invention. In this figure, the same parts as those in FIGS. 1 to 12 are denoted by the same reference numerals.

In this embodiment, on the source / drain 10
Epitaxial single crystal Si layer 24 formed by selective growth
On top of which CoSi_TwoLayer 25 is formed
ing. On the high melting point metal layer 7, a high melting point metal
Id (TaSi_Two, MoSi _Two, ZrSi_TwoEtc.) Layer 2
6 is formed, and CoS is formed on the silicide layer 26.
i_TwoA layer 27 is formed.

Next, the manufacturing process of the apparatus of this embodiment is shown in FIG.
This will be described with reference to 4 to 15.

First, as in the first embodiment,
The configuration shown in FIG. 3 is obtained.

Next, as shown in FIG. 14, a side spacer 9 is formed, the gate oxide film in the exposed portion is removed, and the source / drain region and the high melting point metal layer 7 of the gate electrode are selectively formed. Grow Si. At that time, by appropriately selecting the source gas, deposition temperature, and pressure,
Single crystal Si is grown on the drain region to form a single crystal Si layer 24, and polycrystalline silicon or amorphous silicon is grown on the gate electrode to form a polycrystalline silicon layer (or amorphous silicon layer). You.

Subsequently, as shown in FIG. 15, after performing ion implantation and activation heat treatment for a high concentration region of the source / drain, a Co salicide process is performed to C on the single crystal Si layer 24
An oSi ₂ layer 25 is formed, and _two silicide layers of a refractory metal silicide layer 26 and a CoSi ₂ layer 27 are formed on the gate electrode.

Thereafter, the same steps as those in the first embodiment are performed to obtain a structure as shown in FIG.

In this embodiment, since the single-crystal Si layer 24 is formed on the source / drain 10, the thickness of the layer made of Si in the source / drain region can be increased. As a result, the CoSi ₂ layer 25 is also formed. Thick, sauce
The resistance of the drain can be reduced.

[0053]

As described above, according to the present invention,
Since the gate electrode has a laminated structure of the TiN layer and the refractory metal layer thereon, the threshold control of the MOSFET having the SOI structure becomes easy for both the NMOS and the PMOS, and the gate resistance can be reduced. Further, it can be manufactured by using a high-temperature heat treatment after forming the gate electrode.
In addition, due to the barrier properties of the TiN layer,
Can be prevented from penetrating through the gate oxide film, which is a problem in the manufacture of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing the structure of a first embodiment of a MOSFET as a semiconductor device according to the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a manufacturing process according to the first embodiment.

FIG. 3 is a schematic cross-sectional view for explaining a manufacturing process of the first embodiment.

FIG. 4 is a schematic sectional view for explaining a manufacturing process of the first embodiment.

FIG. 5 is a schematic sectional view for explaining a manufacturing process of the first embodiment.

FIG. 6 is a schematic sectional view showing a structure of a second embodiment of a MOSFET as a semiconductor device according to the present invention.

FIG. 7 is a schematic cross-sectional view for explaining a manufacturing process according to a second embodiment.

FIG. 8 is a schematic cross-sectional view for explaining a manufacturing process according to a second embodiment.

FIG. 9 is a schematic sectional view showing the structure of a third embodiment of a MOSFET as a semiconductor device according to the present invention.

FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process according to a third embodiment.

FIG. 11 is a schematic cross-sectional view for explaining a manufacturing process according to a third embodiment.

FIG. 12 is a schematic cross-sectional view for explaining a manufacturing process according to a third embodiment.

FIG. 13 is a schematic sectional view showing the structure of a fourth embodiment of a MOSFET as a semiconductor device according to the present invention.

FIG. 14 is a schematic cross-sectional view for explaining a manufacturing process according to a fourth embodiment.

FIG. 15 is a schematic cross-sectional view for explaining a manufacturing process according to a fourth embodiment.

FIG. 16 is a diagram showing a relationship between a substrate impurity concentration and a threshold value of an SOI MOSFET.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 Si substrate 2 buried oxide film 3 field oxide film 4 Si layer (SOI layer) 5 gate oxide film 6 TiN layer 7 refractory metal layer 8 extension 9 side spacer 10 source / drain 11 CoSi ₂ layer 12 SiO ₂ containing layer 13 barrier Metal layer 14 W plug 15 Al wiring 16 Antireflection film 17 Passivation film 18 Photoresist pattern layer 19 Co layer 20 TiN layer 21 Alloy layer 22 First sidewall 23 Second sidewall 24 Single crystal Si layer 25 CoSi ₂ layer 26 High Melting point metal silicide layer 27 CoSi ₂ layer 28 Polycrystalline silicon layer (or amorphous silicon layer)

Continued on front page F term (reference) 4M104 AA01 AA09 BB01 BB02 BB13 BB16 BB17 BB20 BB30 CC01 DD04 DD37 DD43 DD64 DD84 EE09 EE17 FF13 FF16 GG09 GG10 GG14 HH05 5F110 AA08 AA13 AA30 BB04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 GG02 GG12 GG13 GG34 HJ01 HJ13 HJ23 HL01 HL03 HL04 HL05 HL08 HL12 HL24 HM15 HM17 NN03 NN22 NN23 NN24 NN35 NN62 QQ11

Claims (6)

[Claims] 1. A MOSFET having an SOI structure, wherein a gate electrode formed of a laminated film including a titanium nitride layer and a refractory metal layer on the titanium nitride layer is formed on a gate insulating film. Semiconductor device. 2. The method according to claim 1, wherein the thickness of the titanium nitride layer is 10 nm or more and 50 nm or less, and the thickness of the refractory metal layer is 100 nm or less.
The semiconductor device according to claim 1, wherein the thickness is not less than 250 nm and not more than 250 nm. 3. The refractory metal constituting the refractory metal layer is one of tantalum, molybdenum and zirconium or an alloy containing the same.
3. The semiconductor device according to any one of 2. 4. The method according to claim 1, wherein the refractory metal layer comprises a laminated film of a plurality of types of refractory metal layers.
3. The semiconductor device according to any one of 3. 5. The semiconductor device according to claim 1, wherein said titanium nitride layer protrudes laterally with respect to said refractory metal layer. 6. The semiconductor device according to claim 5, wherein said titanium nitride layer extends to above a source / drain extension.