JP2001015460A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JP2001015460A
JP2001015460A JP11186990A JP18699099A JP2001015460A JP 2001015460 A JP2001015460 A JP 2001015460A JP 11186990 A JP11186990 A JP 11186990A JP 18699099 A JP18699099 A JP 18699099A JP 2001015460 A JP2001015460 A JP 2001015460A
Authority
JP
Japan
Prior art keywords
polishing
film
buried
wiring
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11186990A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001015460A5 (https=
Inventor
Takeo Kubota
壮男 窪田
Hiroyuki Yano
博之 矢野
Kenro Nakamura
賢朗 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11186990A priority Critical patent/JP2001015460A/ja
Priority to US09/606,149 priority patent/US6429134B1/en
Publication of JP2001015460A publication Critical patent/JP2001015460A/ja
Publication of JP2001015460A5 publication Critical patent/JP2001015460A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
JP11186990A 1999-06-30 1999-06-30 半導体装置の製造方法 Pending JP2001015460A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP11186990A JP2001015460A (ja) 1999-06-30 1999-06-30 半導体装置の製造方法
US09/606,149 US6429134B1 (en) 1999-06-30 2000-06-29 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11186990A JP2001015460A (ja) 1999-06-30 1999-06-30 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2001015460A true JP2001015460A (ja) 2001-01-19
JP2001015460A5 JP2001015460A5 (https=) 2006-06-22

Family

ID=16198284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11186990A Pending JP2001015460A (ja) 1999-06-30 1999-06-30 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US6429134B1 (https=)
JP (1) JP2001015460A (https=)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003001559A (ja) * 2001-06-21 2003-01-08 Mitsubishi Electric Corp 化学的機械研磨方法、化学的機械研磨装置およびスラリー供給装置
JP2005001018A (ja) * 2003-06-09 2005-01-06 Kao Corp 基板の製造方法
JP2005001019A (ja) * 2003-06-09 2005-01-06 Kao Corp 基板の製造方法
KR100467803B1 (ko) * 2002-07-23 2005-01-24 동부아남반도체 주식회사 반도체 소자 제조 방법
JP2006332437A (ja) * 2005-05-27 2006-12-07 Fujitsu Ltd 被研磨膜の研磨方法
EP1278241A3 (en) * 2001-07-17 2007-01-17 Matsushita Electric Industrial Co., Ltd. Method for planarizing deposited film
WO2008072300A1 (ja) * 2006-12-11 2008-06-19 Renesas Technology Corp. 半導体装置の製造方法、およびウェハの研磨方法
JP2008141186A (ja) * 2006-11-08 2008-06-19 Ebara Corp 研磨方法及び研磨装置
WO2010079543A1 (ja) * 2009-01-06 2010-07-15 信越半導体株式会社 半導体素子の製造方法
JP2011176342A (ja) * 2011-04-11 2011-09-08 Ebara Corp 研磨方法及び配線形成方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3860528B2 (ja) 2002-11-12 2006-12-20 株式会社東芝 半導体装置の製造方法
US7300601B2 (en) * 2002-12-10 2007-11-27 Advanced Technology Materials, Inc. Passivative chemical mechanical polishing composition for copper film planarization
US7736405B2 (en) * 2003-05-12 2010-06-15 Advanced Technology Materials, Inc. Chemical mechanical polishing compositions for copper and associated materials and method of using same
US7109117B2 (en) * 2004-01-14 2006-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method for chemical mechanical polishing of a shallow trench isolation structure
KR100614773B1 (ko) * 2004-12-28 2006-08-22 삼성전자주식회사 화학 기계적 연마 방법
KR100607763B1 (ko) * 2004-12-29 2006-08-01 동부일렉트로닉스 주식회사 두 단계의 절연막 연마 공정을 포함하는 반도체 제조 방법
US7544618B2 (en) * 2006-05-18 2009-06-09 Macronix International Co., Ltd. Two-step chemical mechanical polishing process
US20100087065A1 (en) * 2007-01-31 2010-04-08 Advanced Technology Materials, Inc. Stabilization of polymer-silica dispersions for chemical mechanical polishing slurry applications
JP4696086B2 (ja) * 2007-02-20 2011-06-08 信越半導体株式会社 シリコン単結晶ウエーハの仕上げ研磨方法及びシリコン単結晶ウエーハ
US7833893B2 (en) * 2007-07-10 2010-11-16 International Business Machines Corporation Method for forming conductive structures
JP4489108B2 (ja) * 2007-09-13 2010-06-23 株式会社東芝 半導体装置の製造方法
US8569888B2 (en) 2011-05-24 2013-10-29 International Business Machines Corporation Wiring structure and method of forming the structure
KR101673692B1 (ko) 2014-11-07 2016-11-07 현대자동차주식회사 건식 실리카 입자를 포함하는 상변이 현탁 유체 조성물 및 이의 제조방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665202A (en) * 1995-11-24 1997-09-09 Motorola, Inc. Multi-step planarization process using polishing at two different pad pressures
JPH10128655A (ja) 1996-10-31 1998-05-19 Toshiba Corp 研磨装置
US5985748A (en) * 1997-12-01 1999-11-16 Motorola, Inc. Method of making a semiconductor device using chemical-mechanical polishing having a combination-step process
US6106662A (en) * 1998-06-08 2000-08-22 Speedfam-Ipec Corporation Method and apparatus for endpoint detection for chemical mechanical polishing
US6276987B1 (en) * 1998-08-04 2001-08-21 International Business Machines Corporation Chemical mechanical polishing endpoint process control
JP3161425B2 (ja) * 1998-09-09 2001-04-25 日本電気株式会社 Ｓｔｉの形成方法
US6165052A (en) * 1998-11-16 2000-12-26 Taiwan Semiconductor Manufacturing Company Method and apparatus for chemical/mechanical planarization (CMP) of a semiconductor substrate having shallow trench isolation
US6083840A (en) * 1998-11-25 2000-07-04 Arch Specialty Chemicals, Inc. Slurry compositions and method for the chemical-mechanical polishing of copper and copper alloys

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003001559A (ja) * 2001-06-21 2003-01-08 Mitsubishi Electric Corp 化学的機械研磨方法、化学的機械研磨装置およびスラリー供給装置
EP1278241A3 (en) * 2001-07-17 2007-01-17 Matsushita Electric Industrial Co., Ltd. Method for planarizing deposited film
KR100467803B1 (ko) * 2002-07-23 2005-01-24 동부아남반도체 주식회사 반도체 소자 제조 방법
JP2005001018A (ja) * 2003-06-09 2005-01-06 Kao Corp 基板の製造方法
JP2005001019A (ja) * 2003-06-09 2005-01-06 Kao Corp 基板の製造方法
JP2006332437A (ja) * 2005-05-27 2006-12-07 Fujitsu Ltd 被研磨膜の研磨方法
JP2008141186A (ja) * 2006-11-08 2008-06-19 Ebara Corp 研磨方法及び研磨装置
WO2008072300A1 (ja) * 2006-12-11 2008-06-19 Renesas Technology Corp. 半導体装置の製造方法、およびウェハの研磨方法
WO2010079543A1 (ja) * 2009-01-06 2010-07-15 信越半導体株式会社 半導体素子の製造方法
JP2011176342A (ja) * 2011-04-11 2011-09-08 Ebara Corp 研磨方法及び配線形成方法

Also Published As

Publication number Publication date
US6429134B1 (en) 2002-08-06

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