JP2000512077A - 互い違いに配列される配線を製造するため窪んだローカル導体を使用する集積回路 - Google Patents
互い違いに配列される配線を製造するため窪んだローカル導体を使用する集積回路Info
- Publication number
- JP2000512077A JP2000512077A JP10500547A JP50054798A JP2000512077A JP 2000512077 A JP2000512077 A JP 2000512077A JP 10500547 A JP10500547 A JP 10500547A JP 50054798 A JP50054798 A JP 50054798A JP 2000512077 A JP2000512077 A JP 2000512077A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric
- wiring
- layer
- dielectric layer
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.窪んだ配線構造を形成する方法であって、 半導体基板上に実質的に同一平面にある第1の導体の組を形成するステップと 、 前記第1の導体の上に第1の誘電体層を堆積するステップと、 前記第1の誘電体層内にトレンチを形成するステップと、 前記トレンチ内に導電性材料を堆積するステップと、 前記トレンチ内の前記導電性材料の上表面が前記第1の誘電体の上表面と実質 的に同一平面となるまで、前記導電性材料を平坦化するステップと、 前記導電性材料の前記上表面が前記第1の誘電体の上表面から下にずれるまで 、前記導電性材料をエッチングするステップと、 前記導電性材料および前記第1の誘電体層の上に第2の誘電体層を形成するス テップとを含む、窪んだ配線構造を形成する方法。 2.前記第1の誘電体層を堆積するステップは、TEOS源でCVD反応チャン バ内で酸化物を堆積することを含む、請求項1に記載の窪んだ配線構造を形成す る方法。 3.前記第1の誘電体層を堆積するステップは、シラン源でCVD反応チャンバ 内で酸化物を堆積することを含む、請求項1に記載の窪んだ配線構造を形成する 方法。 4.前記導電性材料はタングステンを含む、請求項1に記載の窪んだ配線構造を 形成する方法。 5.前記導電性材料は金属または金属シリサイドを含む、請求項1に記載の窪ん だ配線構造を形成する方法。 6.実質的に平坦な上表面を作るため前記第2の誘電体を平坦化するステップを さらに含む、請求項1に記載の窪んだ配線構造を形成する方法。 7.前記第2の誘電体の前記上表面は、前記第1の誘電体の上表面と実質的に同 一平面にある、請求項6に記載の窪んだ配線構造を形成する方法。 8.前記第2の誘電体の上表面から前記導電性材料へ延びるコンタクトトンネル を形成するステップをさらに含む、請求項1に記載の窪んだ配線構造を形成する 方法。 9.前記第2の誘電体の前記上表面から前記第1の配線層に延びるコンタクト開 口部を形成するステップをさらに含む、請求項1に記載の窪んだ配線構造を形成 する方法。 10.前記第1の誘電体の上表面上に実質的に同一平面にある第2の導体の組を 形成するステップをさらに含む、請求項1に記載の窪んだ配線構造を形成する方 法。 11.多層配線構造であって、 半導体基板上に配置される第1の配線層と、 前記第1の配線層上に配置される第1の誘電体層とを含み、前記第1の誘電体 層は前記誘電体の上表面から下方向に延びるトレンチを有し、前記トレンチは、 前記導電性材料の上表面が前記第1の誘電体層の上表面より縦方向に下にくるよ う導電性材料で部分的に埋込まれ、前記導電性材料はローカルコネクタを形成し 、前記多層配線構造はさらに、 前記第2の誘電体層が前記トレンチ内に横方向に規定されるよう、前記ローカ ルコネクタ上に形成される第2の誘電体層と、 第1および第2の導体の下表面が前記ローカルコネクタの上表面より縦方向に 上にずれるよう、前記第1の誘電体層上に形成される第2の配線層の第1および 第2の導体とを含み、前記第1および第2の導体は横方向距離、前記ローカルコ ネクタから横方向にずらされ、前記ローカルコネクタは、前記横方向距離の二乗 と前記縦方向距離の二乗との合計のほぼ平方根である距離だけ前記第1および第 2の導体からずらされる、多層配線構造。 12.前記第1の誘電体層は、前記第2の配線の対の1つまたは2つ以上から前 記第1の誘電体層を通って前記第1の配線層に延びる1つまたは2つ以上のコン タクトトンネルを有する、請求項11に記載の多層配線構造。 13.前記第1の誘電体層は、前記第2の配線層の第3の導体から前記第1の誘 電体層を通って前記ローカル配線材料に延びる1つまたは2つ以上のコンタクト トンネルを有する、請求項11に記載の多層配線構造。 14.前記第1および第2の配線層はアルミニウムを含む、請求項11に記載の 多層配線構造。 15.前記導電性材料はタングステンを含む、請求項11に記載の多層配線構造 。 16.前記導電性材料は金属または金属シリサイドを含む、請求項11に記載の 多層配線構造。 17.前記第1の誘電体はシランまたはTEOS源でCVDチャンバ内で形成さ れる酸化物を含む、請求項11に記載の多層配線構造。 18.半導体装置であって、 第1の配線層の上に形成される第1の誘電体層と、 第1の誘電体層の上に配置される第2の配線層とを含み、前記第2の配線層は 、前記第2の配線層の間隔が最小の距離しか離れていない高密度レイアウト区域 を部分的に備えるよう構成され、前記高密度レイアウト区域は第1および第2の 導体を含み、前記半導体装置はさらに、 ローカル導体の上表面が前記第1および第2の導体の下表面から縦方向距離、 縦方向にずれるよう、前記第1の誘電体内に配置されるローカル導体を含み、前 記ローカル導体は前記第1および第2の導体から等間隔にその間に横方向に配置 され、前記ローカル導体は前記高密度領域の外に位置するコンタクトを通じて前 記中間導体に接続される、半導体装置。 19.前記第1および第2の配線層はアルミニウムを含む、請求項18に記載の ローカル配線。 20.前記ローカル導体はタングステンを含む、請求項18に記載のローカル配 線。 21.前記ローカル導体上に形成される第2の誘電体層をさらに含む、請求項1 8に記載のローカル配線。 22.前記第1および第2の誘電体層は、シランまたはTEOS源を使用してC VDチャンバ内で形成される酸化物を含む、請求項21に記載のローカル配線。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/660,674 | 1996-06-05 | ||
US08/660,674 US5767012A (en) | 1996-06-05 | 1996-06-05 | Method of forming a recessed interconnect structure |
PCT/US1997/002509 WO1997047039A1 (en) | 1996-06-05 | 1997-02-18 | An integrated circuit which uses a recessed local conductor for producing staggered interconnect lines |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2000512077A true JP2000512077A (ja) | 2000-09-12 |
JP2000512077A5 JP2000512077A5 (ja) | 2004-11-18 |
JP4152439B2 JP4152439B2 (ja) | 2008-09-17 |
Family
ID=24650506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50054798A Expired - Fee Related JP4152439B2 (ja) | 1996-06-05 | 1997-02-18 | 互い違いに配列される配線を製造するため窪んだローカル導体を使用する集積回路 |
Country Status (6)
Country | Link |
---|---|
US (2) | US5767012A (ja) |
EP (1) | EP0963606B1 (ja) |
JP (1) | JP4152439B2 (ja) |
KR (1) | KR100431553B1 (ja) |
DE (1) | DE69734465T2 (ja) |
WO (1) | WO1997047039A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5767012A (en) * | 1996-06-05 | 1998-06-16 | Advanced Micro Devices, Inc. | Method of forming a recessed interconnect structure |
US5854503A (en) * | 1996-11-19 | 1998-12-29 | Integrated Device Technology, Inc. | Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit |
US6022485A (en) * | 1997-10-17 | 2000-02-08 | International Business Machines Corporation | Method for controlled removal of material from a solid surface |
US6117760A (en) * | 1997-11-12 | 2000-09-12 | Advanced Micro Devices, Inc. | Method of making a high density interconnect formation |
US6081032A (en) * | 1998-02-13 | 2000-06-27 | Texas Instruments - Acer Incorporated | Dual damascene multi-level metallization and interconnection structure |
US6239491B1 (en) * | 1998-05-18 | 2001-05-29 | Lsi Logic Corporation | Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same |
US6087251A (en) * | 1998-10-30 | 2000-07-11 | United Microelectronics Corp. | Method of fabricating a dual damascene structure |
FR2786609B1 (fr) * | 1998-11-26 | 2003-10-17 | St Microelectronics Sa | Circuit integre a capacite interlignes reduite et procede de fabrication associe |
US6352916B1 (en) * | 1999-11-02 | 2002-03-05 | Micron Technology, Inc. | Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench |
TW507311B (en) * | 2001-11-06 | 2002-10-21 | Nanya Technology Corp | Capacitance prediction method of deep trench capacitor |
US6777318B2 (en) * | 2002-08-16 | 2004-08-17 | Taiwan Semiconductor Manufacturing Company | Aluminum/copper clad interconnect layer for VLSI applications |
US7012020B2 (en) * | 2003-09-12 | 2006-03-14 | Taiwan Semiconductor Manufacturing Co. Ltd. | Multi-layered metal routing technique |
TW200629466A (en) * | 2004-10-14 | 2006-08-16 | Koninkl Philips Electronics Nv | Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same |
US7268431B2 (en) * | 2004-12-30 | 2007-09-11 | Advantech Global, Ltd | System for and method of forming via holes by use of selective plasma etching in a continuous inline shadow mask deposition process |
US7361585B2 (en) * | 2004-12-23 | 2008-04-22 | Advantech Global, Ltd | System for and method of planarizing the contact region of a via by use of a continuous inline vacuum deposition |
US20060197228A1 (en) * | 2005-03-04 | 2006-09-07 | International Business Machines Corporation | Single mask process for variable thickness dual damascene structures, other grey-masking processes, and structures made using grey-masking |
US7575984B2 (en) * | 2006-05-31 | 2009-08-18 | Sandisk 3D Llc | Conductive hard mask to protect patterned features during trench etch |
US8816403B2 (en) * | 2011-09-21 | 2014-08-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Efficient semiconductor device cell layout utilizing underlying local connective features |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3974517A (en) * | 1973-11-02 | 1976-08-10 | Harris Corporation | Metallic ground grid for integrated circuits |
EP0393635B1 (en) * | 1989-04-21 | 1997-09-03 | Nec Corporation | Semiconductor device having multi-level wirings |
US5189506A (en) * | 1990-06-29 | 1993-02-23 | International Business Machines Corporation | Triple self-aligned metallurgy for semiconductor devices |
JP3074713B2 (ja) * | 1990-09-18 | 2000-08-07 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH05198691A (ja) * | 1991-11-15 | 1993-08-06 | Toshiba Corp | 半導体集積回路における多層配線構造 |
US5187121A (en) * | 1991-12-18 | 1993-02-16 | International Business Machines Corporation | Process for fabrication of a semiconductor structure and contact stud |
US5466636A (en) * | 1992-09-17 | 1995-11-14 | International Business Machines Corporation | Method of forming borderless contacts using a removable mandrel |
US5382545A (en) * | 1993-11-29 | 1995-01-17 | United Microelectronics Corporation | Interconnection process with self-aligned via plug |
JP2956571B2 (ja) * | 1996-03-07 | 1999-10-04 | 日本電気株式会社 | 半導体装置 |
US5767012A (en) * | 1996-06-05 | 1998-06-16 | Advanced Micro Devices, Inc. | Method of forming a recessed interconnect structure |
-
1996
- 1996-06-05 US US08/660,674 patent/US5767012A/en not_active Expired - Lifetime
-
1997
- 1997-02-18 EP EP97907668A patent/EP0963606B1/en not_active Expired - Lifetime
- 1997-02-18 DE DE69734465T patent/DE69734465T2/de not_active Expired - Lifetime
- 1997-02-18 KR KR10-1998-0709931A patent/KR100431553B1/ko not_active IP Right Cessation
- 1997-02-18 WO PCT/US1997/002509 patent/WO1997047039A1/en active IP Right Grant
- 1997-02-18 JP JP50054798A patent/JP4152439B2/ja not_active Expired - Fee Related
-
1998
- 1998-03-04 US US09/034,589 patent/US6031289A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69734465D1 (de) | 2005-12-01 |
KR100431553B1 (ko) | 2004-10-28 |
EP0963606B1 (en) | 2005-10-26 |
JP4152439B2 (ja) | 2008-09-17 |
KR20000016357A (ko) | 2000-03-25 |
EP0963606A1 (en) | 1999-12-15 |
US5767012A (en) | 1998-06-16 |
DE69734465T2 (de) | 2006-08-03 |
US6031289A (en) | 2000-02-29 |
WO1997047039A1 (en) | 1997-12-11 |
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