JP2000511001A5 - - Google Patents
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- Publication number
- JP2000511001A5 JP2000511001A5 JP1997541692A JP54169297A JP2000511001A5 JP 2000511001 A5 JP2000511001 A5 JP 2000511001A5 JP 1997541692 A JP1997541692 A JP 1997541692A JP 54169297 A JP54169297 A JP 54169297A JP 2000511001 A5 JP2000511001 A5 JP 2000511001A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Description
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FI962277 | 1996-05-31 | ||
| FI962277A FI962277A0 (fi) | 1996-05-31 | 1996-05-31 | Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar |
| PCT/FI1997/000331 WO1997045871A1 (en) | 1996-05-31 | 1997-05-30 | Solder alloy or tin contact bump structure for unencapsulated microcircuits as well as a process for the production thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000511001A JP2000511001A (ja) | 2000-08-22 |
| JP2000511001A5 true JP2000511001A5 (ja) | 2004-10-14 |
Family
ID=8546126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP09541692A Ceased JP2000511001A (ja) | 1996-05-31 | 1997-05-30 | カプセル化されないマイクロ回路用のはんだ合金又は錫接触バンプ構造と同時にそれを製造するための手順 |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0958606A1 (ja) |
| JP (1) | JP2000511001A (ja) |
| AU (1) | AU2964297A (ja) |
| FI (1) | FI962277A0 (ja) |
| WO (1) | WO1997045871A1 (ja) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2799578B1 (fr) | 1999-10-08 | 2003-07-18 | St Microelectronics Sa | Procede de realisation de connexions electriques sur un boitier semi-conducteur et boitier semi-conducteur |
| US6413851B1 (en) * | 2001-06-12 | 2002-07-02 | Advanced Interconnect Technology, Ltd. | Method of fabrication of barrier cap for under bump metal |
| TWI225899B (en) * | 2003-02-18 | 2005-01-01 | Unitive Semiconductor Taiwan C | Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4782380A (en) * | 1987-01-22 | 1988-11-01 | Advanced Micro Devices, Inc. | Multilayer interconnection for integrated circuit structure having two or more conductive metal layers |
| US4880708A (en) * | 1988-07-05 | 1989-11-14 | Motorola, Inc. | Metallization scheme providing adhesion and barrier properties |
| JPH07321114A (ja) * | 1994-05-23 | 1995-12-08 | Sharp Corp | 半導体装置のハンダバンプ形成の方法および構造 |
| US5587336A (en) * | 1994-12-09 | 1996-12-24 | Vlsi Technology | Bump formation on yielded semiconductor dies |
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1996
- 1996-05-31 FI FI962277A patent/FI962277A0/fi not_active Application Discontinuation
-
1997
- 1997-05-30 AU AU29642/97A patent/AU2964297A/en not_active Abandoned
- 1997-05-30 EP EP97924046A patent/EP0958606A1/en not_active Withdrawn
- 1997-05-30 WO PCT/FI1997/000331 patent/WO1997045871A1/en not_active Application Discontinuation
- 1997-05-30 JP JP09541692A patent/JP2000511001A/ja not_active Ceased