JP2001500658A5 - - Google Patents

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Publication number
JP2001500658A5
JP2001500658A5 JP1998512612A JP51261298A JP2001500658A5 JP 2001500658 A5 JP2001500658 A5 JP 2001500658A5 JP 1998512612 A JP1998512612 A JP 1998512612A JP 51261298 A JP51261298 A JP 51261298A JP 2001500658 A5 JP2001500658 A5 JP 2001500658A5
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JP
Japan
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JP1998512612A
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JP2001500658A (ja
JP3979673B2 (ja
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Priority claimed from PCT/US1996/014349 external-priority patent/WO1998010471A1/en
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Publication of JP2001500658A5 publication Critical patent/JP2001500658A5/ja
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Publication of JP3979673B2 publication Critical patent/JP3979673B2/ja
Anticipated expiration legal-status Critical
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Figure 2001500658
Figure 2001500658
Figure 2001500658
Figure 2001500658
Figure 2001500658
Figure 2001500658
JP51261298A 1996-09-05 1997-03-10 浮遊ゲートメモリデバイスにおけるプリプログラミングのためのファウラ・ノルトハイム(f―n)トンネリング Expired - Lifetime JP3979673B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
WO96/14349 1996-09-05
PCT/US1996/014349 WO1998010471A1 (en) 1996-09-05 1996-09-05 Triple well floating gate memory and operating method with isolated channel program, preprogram and erase processes
PCT/US1997/003861 WO1998010424A1 (en) 1996-09-05 1997-03-10 Fowler-nordheim (f-n) tunneling for pre-programming in a floating gate memory device

Publications (3)

Publication Number Publication Date
JP2001500658A JP2001500658A (ja) 2001-01-16
JP2001500658A5 true JP2001500658A5 (ja) 2004-12-09
JP3979673B2 JP3979673B2 (ja) 2007-09-19

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP51261298A Expired - Lifetime JP3979673B2 (ja) 1996-09-05 1997-03-10 浮遊ゲートメモリデバイスにおけるプリプログラミングのためのファウラ・ノルトハイム(f―n)トンネリング

Country Status (4)

Country Link
US (1) US5963476A (ja)
EP (2) EP0925586B1 (ja)
JP (1) JP3979673B2 (ja)
WO (2) WO1998010471A1 (ja)

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US7133313B2 (en) * 2004-04-26 2006-11-07 Macronix International Co., Ltd. Operation scheme with charge balancing for charge trapping non-volatile memory
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US7145186B2 (en) 2004-08-24 2006-12-05 Micron Technology, Inc. Memory cell with trenched gated thyristor
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US7746706B2 (en) 2006-12-15 2010-06-29 Spansion Llc Methods and systems for memory devices
US8320191B2 (en) * 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US7940572B2 (en) * 2008-01-07 2011-05-10 Mosaid Technologies Incorporated NAND flash memory having multiple cell substrates
US8984238B2 (en) * 2009-02-05 2015-03-17 Spansion Llc Fractured erase system and method
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JP2012533140A (ja) * 2009-07-10 2012-12-20 アプルス フラッシュ テクノロジー アイエヌシー 新たな高速高密度nandベース2t−norフラッシュメモリ設計
TWI755874B (zh) * 2019-09-30 2022-02-21 台灣積體電路製造股份有限公司 半導體裝置及其形成方法
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