JP2000357584A - Circuit board for luminescent element, electronic equipment and display - Google Patents
Circuit board for luminescent element, electronic equipment and displayInfo
- Publication number
- JP2000357584A JP2000357584A JP11167556A JP16755699A JP2000357584A JP 2000357584 A JP2000357584 A JP 2000357584A JP 11167556 A JP11167556 A JP 11167556A JP 16755699 A JP16755699 A JP 16755699A JP 2000357584 A JP2000357584 A JP 2000357584A
- Authority
- JP
- Japan
- Prior art keywords
- emitting element
- light emitting
- circuit board
- common electrode
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000605 extraction Methods 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 55
- 239000010408 film Substances 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 229910052715 tantalum Inorganic materials 0.000 description 9
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000005401 electroluminescence Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000011575 calcium Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、いわゆる電界発光
（Electro-Luminescence）素子を形成するために適する
回路基板の改良に関する。The present invention relates to an improvement in a circuit board suitable for forming a so-called electro-luminescence (Electro-Luminescence) element.
【０００２】[0002]
【従来の技術】電界発光素子を用いた表示装置における
基板配置に関する公知技術としては、本願出願人の発明
に係る特開平１１−２４６０４号公報に記載されるよう
なものがあった。この公報には、電界発光素子の形成領
域を取り囲んで、駆動回路を配した回路基板が開示され
ていた。2. Description of the Related Art As a known technique relating to the arrangement of substrates in a display device using an electroluminescent element, there is one disclosed in Japanese Patent Application Laid-Open No. Hei 11-24604 according to the invention of the present applicant. This publication discloses a circuit board on which a driving circuit is arranged so as to surround an electroluminescent element forming region.
【０００３】電界発光素子は電流を供給して発光させる
ものであるため、配線の抵抗が高いと電圧降下が大きく
なり、輝度が低くなり易い。これに対処するために、従
来、技術常識から抵抗率の低い金属を配線層の材料とし
て使用することが必要であった。[0003] Since the electroluminescent element supplies current and emits light, if the resistance of the wiring is high, the voltage drop increases and the luminance tends to decrease. To cope with this, conventionally, it has been necessary to use a metal having a low resistivity as a material of the wiring layer based on common sense in the art.
【０００４】[0004]
【発明が解決しようとする課題】しかし、回路基板の全
体的な電圧降下の防止について十分に考慮されていなか
った。However, sufficient consideration has not been given to the prevention of the overall voltage drop of the circuit board.
【０００５】特に、最も大きな電流が流れるのは、複数
の電界発光素子からの電流が流れる共通電極である陰極
である。この陰極パターンにおいて、抵抗率が高いと多
量の電流により大きな電圧降下を生じ、画像表示全体を
暗くしかねない。[0005] In particular, the largest current flows through the cathode, which is a common electrode through which currents from a plurality of electroluminescent elements flow. In this cathode pattern, if the resistivity is high, a large amount of current causes a large voltage drop, which may darken the entire image display.
【０００６】[0006]
【課題を解決するための手段】そこで本発明は、共通電
極における電圧降下を少なくし、明るい画像表示を可能
にするための発光素子用回路基板およびその基板を使用
した電子機器を提供することを目的とする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a circuit board for a light emitting element for reducing a voltage drop at a common electrode and enabling a bright image display, and an electronic apparatus using the board. Aim.
【０００７】本発明は、発光素子の形成に用いられる発
光素子用回路基板において、外部への取出端子が当該基
板の一辺に集積された取出端子群と、所定の共通電極が
配置される領域と前記取出端子群との間に、前記取出端
子群の一部の取出端子と前記共通電極とを電気的に接続
するコンタクトパターンと、を備えていることを特徴と
する発光素子用回路基板である。According to the present invention, there is provided a circuit board for a light emitting element used for forming a light emitting element, wherein a group of extraction terminals in which extraction terminals to the outside are integrated on one side of the substrate, and a region where a predetermined common electrode is arranged. A circuit board for a light-emitting element, comprising: a contact pattern that electrically connects a part of the extraction terminals of the extraction terminal group and the common electrode to the extraction terminal group. .
【０００８】「取出端子」は、必ずしも基板の一辺にの
み設けられることを意味しない。「回路基板」は、電界
発光素子のように多量に電流を消費する素子の例示であ
り、回路基板に設けられる回路がこれに限定されること
はない。「共通電極」は、後の工程で設けられるもので
あり、回路基板に共通電極が既に形成されていることに
限定されない。「共通電極」が形成されることになるで
あろう「領域」に対応してコンタクトパターンを設けて
あることに意味がある。したがって共通電極などの表示
に関わる構造を備えない回路基板のまま流通する態様も
考えられる。The “extraction terminal” does not necessarily mean that it is provided only on one side of the substrate. The “circuit board” is an example of an element that consumes a large amount of current, such as an electroluminescent element, and a circuit provided on the circuit board is not limited to this. The “common electrode” is provided in a later step, and is not limited to the case where the common electrode is already formed on the circuit board. It is significant that a contact pattern is provided corresponding to a “region” where a “common electrode” will be formed. Therefore, a mode in which the circuit board is not provided with a structure related to display such as a common electrode and is circulated as such may be considered.
【０００９】例えば、この回路基板は、電流を供給する
ことにより発光する発光素子の形成に用いられ、前記コ
ンタクトパターンは、前記取出端子群の一部と前記発光
素子の電流が共通して流れる共通電極とを電気的に接続
するように形成される。For example, the circuit board is used for forming a light emitting element that emits light by supplying a current, and the contact pattern is a common part in which a current of the light emitting element flows in common with a part of the extraction terminal group. It is formed so as to be electrically connected to the electrode.
【００１０】また発光素子は、有機電界発光素子などに
適用される。The light emitting device is applied to an organic electroluminescent device and the like.
【００１１】ここでコンタクトパターンは、共通電極の
有する面積の１０％以上の面積を備えていることが好ま
しい。「１０％」は一応の目安であり、これに限定され
ることはない。Here, the contact pattern preferably has an area of 10% or more of the area of the common electrode. “10%” is a tentative measure, and is not limited to this.
【００１２】上記取出端子群は、同一の形状を備えた取
出端子を連設されている。同一形態の取出端子であれ
ば、コネクタなどによる基板との接続が規格化でき経済
的かつ容易だからである。The above-mentioned terminal group is provided with a plurality of terminal terminals having the same shape. This is because if the extraction terminals are of the same form, the connection with the board by a connector or the like can be standardized, and is economical and easy.
【００１３】形成される共通電極は方形であり、前記共
通電極を介して前記コンタクトパターンと対向する領域
に、走査配線に走査信号を供給するための走査駆動回路
を備えている。The formed common electrode has a rectangular shape, and is provided with a scanning drive circuit for supplying a scanning signal to a scanning wiring in a region facing the contact pattern via the common electrode.
【００１４】またコンタクトパターンおよび走査駆動回
路が設けられる前記共通電極の周辺領域以外の領域に、
信号配線に画像信号を供給するための信号駆動回路およ
び／または周辺回路を形成する領域を備えている。信号
駆動回路や周辺回路がいずれの辺に位置するかに限定は
ない。In a region other than a peripheral region of the common electrode where a contact pattern and a scanning drive circuit are provided,
A region for forming a signal driving circuit and / or a peripheral circuit for supplying an image signal to the signal wiring is provided. There is no limitation on which side the signal drive circuit or the peripheral circuit is located.
【００１５】いずれの回路も設けられてない前記共通電
極を形成する領域の四隅にアライメントマークを備えて
いることは好ましい。共通電極の四周に設けられる回路
の間隙を有効利用する趣旨である。It is preferable that alignment marks are provided at four corners of a region where the common electrode is not provided with any circuit. The purpose is to effectively use the gap between the circuits provided on the four circumferences of the common electrode.
【００１６】本発明は、本発明の発光素子用回路基板を
備えていることを特徴とする電子機器でもある。電子機
器に限定はないが、携帯情報端末、ビューファインダ、
ヘッドマウントディスプレイ、などを含む。According to the present invention, there is also provided an electronic apparatus comprising the light emitting element circuit board of the present invention. Although there is no limitation on electronic devices, portable information terminals, viewfinders,
Including head-mounted displays.
【００１７】例えば表示装置である場合、本発明の発光
素子用回路基板と、前記回路基板上に各画素に対応して
設けられた複数の発光素子と、を備え、前記発光素子に
対する制御により画像を表示するように構成される。For example, in the case of a display device, the light emitting device includes a light emitting element circuit board of the present invention and a plurality of light emitting elements provided on the circuit board corresponding to each pixel. Is configured to be displayed.
【００１８】このような表示装置では、各画素の発光素
子に対応して当該画素の発光素子の駆動制御を行うトラ
ンジスタを備える。Such a display device includes a transistor for controlling the driving of the light emitting element of each pixel corresponding to the light emitting element of each pixel.
【００１９】発光素子が電流制御型の発光素子である場
合、各画素において、前記発光素子の制御用トランジス
タと駆動用トランジスタとを備える。When the light emitting element is a current control type light emitting element, each pixel includes a control transistor and a driving transistor for the light emitting element.
【００２０】各画素における発光素子は、画素電極と、
当該画素電極と前記共通電極との間に少なくとも有機発
光材料からなる発光層を備えている。The light emitting element in each pixel includes a pixel electrode,
A light emitting layer made of at least an organic light emitting material is provided between the pixel electrode and the common electrode.
【００２１】[0021]
【発明の実施の形態】次に本発明の好適な実施の形態
を、図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings.
【００２２】図１に本実施形態の発光表示素子用回路基
板の平面図を示す。本回路基板は、図１に示すように、
表示領域１、コンタクトパターン２、信号駆動回路３、
走査駆動回路４、周辺回路５、取出端子群６およびアラ
イメントマーク７を備えて構成される。FIG. 1 is a plan view of a light emitting display element circuit board according to the present embodiment. This circuit board, as shown in FIG.
Display area 1, contact pattern 2, signal drive circuit 3,
It comprises a scanning drive circuit 4, a peripheral circuit 5, an extraction terminal group 6, and an alignment mark 7.
【００２３】表示領域１は、複数の画素領域で構成され
ており、その上面（図面手前）には総ての画素領域を覆
って共通した電流が流れる共通電極１０が形成されてい
る。各画素領域に形成される素子に限定はないが、本実
施形態では例えば図２に示すような構造の電界発光素子
１２を例示する。共通電極１０は通常の表示装置では、
方形に形成されている。The display region 1 is composed of a plurality of pixel regions, and a common electrode 10 is formed on the upper surface (in front of the drawing) of the display region 1 so as to cover all the pixel regions and flow a common current. Although the elements formed in each pixel region are not limited, the present embodiment exemplifies an electroluminescent element 12 having a structure as shown in FIG. 2, for example. The common electrode 10 is a common display device.
It is formed in a square.
【００２４】外部端子群６は、外部への取出端子が複
数、この基板の一辺に集積されたものである。取出端子
群６は、同一の形状を備えた取出端子６１を連設するこ
とに構成されている。同一形態の取出端子であれば、端
子を実装したテープからインサートマシンなどにより纏
めて実装することができる。このためコネクタなどによ
る基板との接続が規格化でき経済的かつ容易だからであ
る。各取出端子６１は、導電性の端子が機械的に後付け
されるものでも、フォトリソグラフィなどのプロセスで
導電性材料を薄膜形成して設けられるものでもよい。The external terminal group 6 is formed by integrating a plurality of external output terminals on one side of the substrate. The extraction terminal group 6 is configured such that extraction terminals 61 having the same shape are connected in series. If the extraction terminals are of the same form, they can be mounted together from a tape on which the terminals are mounted by an insert machine or the like. This is because the connection with the board by a connector or the like can be standardized, and it is economical and easy. Each of the extraction terminals 61 may be a terminal to which a conductive terminal is mechanically attached or a terminal provided by forming a thin film of a conductive material by a process such as photolithography.
【００２５】コンタクトパターン２は、本発明に係り、
共通電極１０と取出端子群６との間に設けられ、コンタ
クト配線２１を介して取出端子群６の一部の取出端子６
１と共通電極１０とを電気的に接続するパターンとなっ
ている。コンタクト配線２１は、取出端子６１と同じ材
料で同一の層にパターニングされている。ただしコンタ
クトパターン２と各取出端子６１とを直接接続してあっ
てもよい。The contact pattern 2 according to the present invention,
A part of the extraction terminals 6 of the extraction terminal group 6 provided between the common electrode 10 and the extraction terminal group 6 via the contact wiring 21.
1 and the common electrode 10 are electrically connected. The contact wiring 21 is patterned in the same layer with the same material as the extraction terminal 61. However, the contact pattern 2 and each extraction terminal 61 may be directly connected.
【００２６】ここでコンタクトパターン２は、共通電極
の有する面積の１０％以上の面積を備えていることが好
ましい。すなわち、電界発光素子の駆動電流は１０ｍＡ
／ｃｍ２程度である。一方コンタクトパターン２の接触
抵抗は、５Ω・ｃｍ２程度である。全電界発光素子の発
光面積をＡｃｍ２とし、共通電極１０に対するコンタク
トパターンの面積比をｋとすると、コンタクトパターン
２中で生じる電圧降下Ｖdrop[mV]は、Ａ×１０・５／ｋ
Ａとなる。Here, the contact pattern 2 preferably has an area of 10% or more of the area of the common electrode. That is, the driving current of the electroluminescent element is 10 mA.
/ Cm 2 . On the other hand, the contact resistance of the contact pattern 2 is about 5 Ω · cm 2 . Assuming that the light emitting area of all the electroluminescent elements is Acm 2 and the area ratio of the contact pattern to the common electrode 10 is k, the voltage drop Vdrop [mV] generated in the contact pattern 2 is A × 10 · 5 / k
A.
【００２７】ここで電界発光素子に適する駆動電圧から
考えてコンタクトパターンで許容される電圧降下は０．
５Ｖ程度までであるので、ｋ＞＝０．１となり、画素領
域の面積に対するコンタクトパターンの面積の割合は、
１０％程度は必要となるのである。Here, considering the driving voltage suitable for the electroluminescent element, the allowable voltage drop in the contact pattern is 0.
Since it is up to about 5 V, k> = 0.1, and the ratio of the area of the contact pattern to the area of the pixel region is:
About 10% is required.
【００２８】信号駆動回路３は、表示領域１に配置され
る信号配線ｓｉｇに画像信号を供給するための駆動回路
である。信号駆動回路３は、バス配線３１により取出端
子６１の幾つかと接続されている。周辺回路５は、表示
領域１に配置される給電配線ｃｏｍに電源を供給したり
信号配線ｓｉｇの信号を検出したりするための回路群で
ある。周辺回路５は、バス配線５１により取出端子６１
の幾つかと接続されている。なお信号駆動回路３および
周辺回路５の配置はこれに限定されず、信号駆動回路３
と周辺回路５との位置が逆に配置されていても構わな
い。The signal drive circuit 3 is a drive circuit for supplying an image signal to the signal wiring sig arranged in the display area 1. The signal drive circuit 3 is connected to some of the extraction terminals 61 by the bus wiring 31. The peripheral circuit 5 is a circuit group for supplying power to the power supply wiring com arranged in the display area 1 and detecting a signal on the signal wiring sig. The peripheral circuit 5 is connected to an extraction terminal 61 by a bus
Are connected to some of them. The arrangement of the signal drive circuit 3 and the peripheral circuit 5 is not limited to this, and the signal drive circuit 3
And the position of the peripheral circuit 5 may be reversed.
【００２９】走査駆動回路４は、表示領域に配置される
走査配線ｇａｔｅに走査信号を供給するための駆動回路
である。この走査駆動回路４は、共通電極を介してコン
タクトパターンと対向する領域に設けられる。走査駆動
回路４は、バス配線４１により取出端子６１の幾つかと
接続されている。走査駆動回路４をこの位置に設けるの
は、走査配線と信号配線とを比べ信号配線方向に電源供
給のための回路をより多く必要とするため基板の信号配
線方向の端子となる二辺にその回路を設け、走査配線方
向の一辺からコンタクトパターンにより共通電極１０の
引出配線を配置するようにしたためである。このため信
号駆動回路４から取出端子群６までの距離は長くなる
が、走査信号の走査周波数が比較的遅いため、配線抵抗
の影響を少なくできるからである。また、走査駆動回路
４に必要とされるバス配線４１の本数はそれほど多くな
いので、大きな面積を占有されることはない。The scanning driving circuit 4 is a driving circuit for supplying a scanning signal to the scanning wirings gate arranged in the display area. The scanning drive circuit 4 is provided in a region facing the contact pattern via the common electrode. The scanning drive circuit 4 is connected to some of the extraction terminals 61 by a bus wiring 41. Since the scanning drive circuit 4 is provided at this position, more circuits for supplying power in the signal wiring direction are required in comparison with the scanning wiring and the signal wiring. This is because a circuit is provided, and a lead wire of the common electrode 10 is arranged by a contact pattern from one side in the scanning wiring direction. For this reason, the distance from the signal drive circuit 4 to the extraction terminal group 6 is increased, but the scanning frequency of the scanning signal is relatively slow, so that the influence of the wiring resistance can be reduced. Further, since the number of bus lines 41 required for the scanning drive circuit 4 is not so large, a large area is not occupied.
【００３０】アライメントマーク７は、これらの回路が
設けられていない共通電極１０の四隅に設けられてい
る。電界発光素子では、回路形成工程以降において蒸
着、スパッタ、インクジェットプロセス、陰極（共通電
極）蒸着やスパッタなどの各工程を経る必要がある。基
板の位置決めを正確に行うために、アライメント精度向
上のためのアライメントマークを設けることが好ましい
のである。電界発光素子の形成工程ではフォトリソグラ
フィ法が適用され、露光のためのフォトマスクの他に、
表示領域１より若干大きいフィジカルマスクを施す。ま
た、当該回路基板では、表示領域１の四周には回路が設
けられるが、その四隅は回路が存在していない。アライ
メントマーク７は、このような表示領域１の四隅であっ
てフィジカルマスクで覆われることのない位置に設けら
れる。このように配置すれば、基板スペースの効率的利
用を図ることができ、マークのために基板外形の寸法を
増加することを防止できる。The alignment marks 7 are provided at the four corners of the common electrode 10 where these circuits are not provided. In the electroluminescent device, it is necessary to go through various processes such as vapor deposition, sputtering, an inkjet process, cathode (common electrode) vapor deposition and sputtering after the circuit forming process. In order to accurately position the substrate, it is preferable to provide an alignment mark for improving alignment accuracy. In the formation process of the electroluminescent element, a photolithography method is applied, and in addition to a photomask for exposure,
A physical mask slightly larger than the display area 1 is applied. Further, in the circuit board, circuits are provided on the four circumferences of the display area 1, but no circuits exist at the four corners. The alignment marks 7 are provided at the four corners of the display area 1 and at positions that are not covered by the physical mask. With such an arrangement, it is possible to efficiently use the substrate space, and it is possible to prevent an increase in the outer shape of the substrate due to the mark.
【００３１】図２に図１のＡ−Ａ切断面における断面図
を示す。図２は一つの取出端子と画素領域について拡大
して示したものである。FIG. 2 is a sectional view taken along the line AA of FIG. FIG. 2 is an enlarged view of one extraction terminal and a pixel region.
【００３２】当該回路基板の層構造は、図２に示すよう
に、下層から順に、透明基板１００、半導体層１０１、
ゲート絶縁膜１０２、第１層間絶縁膜１０３、第２層間
絶縁膜１０４、バンク層１０５および１０６が形成され
ている。表示領域１には、さらに発光層１０７が形成さ
れている。配線に関与する層として、タンタル配線層２
０１、アルミニウム配線層２０２およびＩＴＯ層２０
３、陰極層２０４が形成されている。As shown in FIG. 2, the layer structure of the circuit board includes a transparent substrate 100, a semiconductor layer 101,
A gate insulating film 102, a first interlayer insulating film 103, a second interlayer insulating film 104, and bank layers 105 and 106 are formed. The light emitting layer 107 is further formed in the display area 1. Tantalum wiring layer 2 as a layer involved in wiring
01, aluminum wiring layer 202 and ITO layer 20
3. A cathode layer 204 is formed.
【００３３】材料に関し、透明基板１００は、光透過性
があり、一定の機械的強度を有するガラス、石英などで
形成される。半導体層１０１は、パターン化されたアモ
ルファスシリコンにエネルギーを加えることで重合化さ
せたポリシリコンで形成され、ソース・ドレインの各領
域に不純物がドーピングされている。ゲート絶縁膜１０
２、第１層間絶縁膜１０３、第２層間絶縁膜１０４は、
酸化珪素または窒化珪素で形成されている。バンク層１
０５および１０６は、酸化珪素、窒化珪素、ポリイミド
当の絶縁膜で形成されている。タンタル配線層２０１
は、主として薄膜トランジスタ（ＴＦＴ：Thin Film Tr
ansistor）のゲート配線に使う他、コンタクトパターン
２の構成材料の一つになっている。アルミニウム配線層
２０２は、主としてスルーホールおよび配線に利用され
る。この層の材料として、アルミニウムの他、タンタ
ル、モリブデン、チタン、タングステンなどを使用可能
である。ＩＴＯ電極２０３は、ＩＴＯなど光透過性と導
電性を有する材料で形成される。陰極層２０４は、共通
電極１０の配線を担う層であって、エネルギー順位から
電界発光素子の陰極として使用可能な材料、アルミニウ
ムまたはアルミニウムと他の元素（リチウムなど）の合
金、カルシウムなどで形成される。電界発光層１０７と
しては、陽極から輸送された正孔と陰極から輸送された
電子とが結合して電界発光現象を生じるような有機発光
材料などの材料であり、発光層の他に正孔輸送層および
／または電子輸送層を備えていてもよい。電界発光層１
０７は、画素ごとにパターニングされていてもよい。Regarding the material, the transparent substrate 100 is formed of glass, quartz, or the like, which has a light transmitting property and a certain mechanical strength. The semiconductor layer 101 is formed of polysilicon that is polymerized by applying energy to the patterned amorphous silicon, and the source and drain regions are doped with impurities. Gate insulating film 10
2, the first interlayer insulating film 103 and the second interlayer insulating film 104
It is formed of silicon oxide or silicon nitride. Bank layer 1
05 and 106 are formed of insulating films such as silicon oxide, silicon nitride, and polyimide. Tantalum wiring layer 201
Is primarily a thin film transistor (TFT: T hin F ilm T r
In addition to being used for the gate wiring of an anistor, it is one of the constituent materials of the contact pattern 2. Aluminum wiring layer 202 is mainly used for through holes and wiring. As a material of this layer, tantalum, molybdenum, titanium, tungsten, or the like can be used in addition to aluminum. The ITO electrode 203 is formed of a material having optical transparency and conductivity, such as ITO. The cathode layer 204 is a layer that serves as a wiring for the common electrode 10 and is formed of a material that can be used as a cathode of an electroluminescent element, aluminum, an alloy of aluminum and another element (such as lithium), calcium, or the like in terms of energy order. You. The electroluminescent layer 107 is a material such as an organic light-emitting material in which holes transported from the anode and electrons transported from the cathode combine to cause an electroluminescence phenomenon. And / or an electron transport layer. Electroluminescent layer 1
07 may be patterned for each pixel.
【００３４】一つの画素領域１１に対しては、電界発光
素子１２と駆動用トランジスタ１３と制御用トランジス
タ（制御用トランジスタは図２に図示しない）が設けら
れている。説明を簡単にするため、制御用トランジスタ
の図示を省略してある。An electroluminescent element 12, a driving transistor 13, and a control transistor (the control transistor is not shown in FIG. 2) are provided for one pixel region 11. For simplicity, the illustration of the control transistor is omitted.
【００３５】電界発光素子１２は、画素電極１２１と陰
極層２０４とで電界発光層１０７を挟み込んだ構造を備
えている。陰極層２０４は総ての画素領域１１に共通し
た連続した膜として形成されている。画素電極１２１は
陽極となっている。The electroluminescent element 12 has a structure in which the electroluminescent layer 107 is sandwiched between the pixel electrode 121 and the cathode layer 204. The cathode layer 204 is formed as a continuous film common to all the pixel regions 11. The pixel electrode 121 is an anode.
【００３６】駆動用トランジスタ１３は、薄膜トランジ
スタであり、不純物導入によりソース領域およびドレイ
ン領域が形成された半導体層１０１上に、ソース電極１
３１、ドレイン電極１３２およびゲート電極１３３を備
えて構成されている。ソース電極１３１およびドレイン
電極１３２はスルーホール３０１および３０２の開口中
にアルミニウム配線層２０２を形成して構成される。ゲ
ート電極１３３は、制御用トランジスタ１４のドレイン
に電気的に接続され、タンタル配線層２０１で形成され
ている。The driving transistor 13 is a thin film transistor, and the source electrode 1 is formed on the semiconductor layer 101 in which the source region and the drain region are formed by introducing impurities.
31, a drain electrode 132 and a gate electrode 133. The source electrode 131 and the drain electrode 132 are formed by forming an aluminum wiring layer 202 in the openings of the through holes 301 and 302. The gate electrode 133 is electrically connected to the drain of the control transistor 14, and is formed of the tantalum wiring layer 201.
【００３７】コンタクトパターン２は、層構造上、陰極
層２０４とコンタクト配線２１とを、スルーホール３０
３を介して、ＩＴＯ層２０３、アルミニウム配線層２０
２およびタンタル配線層２０１により電気的に相互に接
続された構造である。ＩＴＯ層２０３は、表示領域１側
の電界発光素子の画素電極１２１、アルミニウム配線層
２０２はソース電極１３１とドレイン電極１３２、タン
タル配線層２０１はゲート電極１３３と同じ材料からな
る層であって、これらの電極がパターニングされる際に
同時にパターン形成される。陰極層２０４とコンタクト
配線２１との接続に用いられているのは、総て導電性層
であるため、極めて低抵抗で電気的な接続をすることが
可能になっている。また、ＩＴＯ層２０３、アルミニウ
ム配線層２０２、タンタル配線層２０１のうちいずれか
の層が存在しなくてもよい。コンタクト配線２１の表示
領域１側と反対側の端部は、スルーホール３０４内でＩ
ＴＯ層２０３、アルミニウム配線層２０２およびタンタ
ル配線層２０１が積層された構造で、取出端子６１実装
テープに接続されている。The contact pattern 2 is formed by connecting the cathode layer 204 and the contact wiring 21 with each other through the through hole 30 on the layer structure.
3, the ITO layer 203 and the aluminum wiring layer 20
2 and the tantalum wiring layer 201 are electrically connected to each other. The ITO layer 203 is a layer made of the same material as the pixel electrode 121 of the electroluminescent element on the display region 1 side, the aluminum wiring layer 202 is a source electrode 131 and a drain electrode 132, and the tantalum wiring layer 201 is the same material as the gate electrode 133. The pattern is formed at the same time when the electrodes are patterned. Since the connection between the cathode layer 204 and the contact wiring 21 is entirely a conductive layer, it is possible to make an electrical connection with extremely low resistance. Further, any one of the ITO layer 203, the aluminum wiring layer 202, and the tantalum wiring layer 201 may not be present. The end of the contact wiring 21 on the side opposite to the display area 1 side has an I
It has a structure in which the TO layer 203, the aluminum wiring layer 202, and the tantalum wiring layer 201 are laminated, and is connected to the extraction terminal 61 mounting tape.
【００３８】図３に上記画素領域１１の集合である電界
発光表示素子全体回路図を示す。FIG. 3 is an overall circuit diagram of the electroluminescent display element which is a set of the pixel regions 11.
【００３９】当該電界発光表示装置において、信号配線
ｓｉｇは信号駆動回路３に接続され、バス配線３１を介
して画像信号を信号配線ｓｉｇに供給するようになって
いる。給電配線ｃｏｍは、周辺回路５に接続され一定電
圧に電流を給電配線に供給するようになっている。走査
配線ｇａｔｅは走査駆動回路４に接続され、バス配線４
１を介して走査信号を走査配線ｇａｔｅに供給するよう
になっている。信号駆動回路３および走査駆動回路４
は、Ｎ型のトランジスタとＰ型のトランジスタとで相補
型トランジスタ回路が形成されている。相補型トランジ
スタによって、駆動回路として機能させるためのシフト
レジスタ、レベルシフタ、アナログスイッチ、ラッチな
どの基本回路が構成されている。In the electroluminescent display device, the signal wiring sig is connected to the signal driving circuit 3 and supplies an image signal to the signal wiring sig via the bus wiring 31. The power supply wiring com is connected to the peripheral circuit 5 so as to supply a current to the power supply wiring to a constant voltage. The scanning wiring gate is connected to the scanning driving circuit 4 and the bus wiring 4
A scanning signal is supplied to the scanning wiring gate through the first scanning line. Signal drive circuit 3 and scan drive circuit 4
In the above, an N-type transistor and a P-type transistor form a complementary transistor circuit. A basic circuit such as a shift register, a level shifter, an analog switch, and a latch for functioning as a driving circuit is formed by the complementary transistors.
【００４０】信号配線ｓｉｇ、走査配線ｇａｔｅおよび
給電配線ｃｏｍで囲まれているのが画素領域１１であっ
て、各々が等価回路として、電界発光素子１２、駆動用
トランジスタ１３、制御用トランジスタ１４および保持
容量ｃａｐを備えている。The pixel region 11 is surrounded by the signal line sig, the scanning line gate, and the power supply line com, each of which is equivalent to an electroluminescent element 12, a driving transistor 13, a control transistor 14, and a holding transistor. It has a capacity cap.
【００４１】上記構成において、走査配線ｇａｔｅを介
して走査信号が制御用トランジスタ１４のゲートに供給
されると、制御用トランジスタ１４がオン状態になり、
信号配線ｓｉｇを介して画像信号の電位がそのドレイン
に供給される。この電位は保持容量ｃａｐにおいて保持
される。画像信号として画素を点灯させる電位が供給さ
れていると、駆動用トランジスタ１３がオン状態にな
り、ソースを介して画素電極１２１に電源電流が供給さ
れるようになる。電界発光素子１２では、電界発光層１
０７では、画素電極１２１から輸送された正孔と共通電
極１０から輸送された電子とが結合して電界発光現象を
生じ発光する。電界発光層１０７からの光は透明電極で
ある画素電極１２１を介して透明基板１００より射出さ
れる。In the above configuration, when a scanning signal is supplied to the gate of the control transistor 14 via the scanning line gate, the control transistor 14 is turned on,
The potential of the image signal is supplied to the drain via the signal wiring sig. This potential is stored in the storage capacitor cap. When a potential for lighting a pixel is supplied as an image signal, the driving transistor 13 is turned on, and a power supply current is supplied to the pixel electrode 121 via the source. In the electroluminescent element 12, the electroluminescent layer 1
At 07, the holes transported from the pixel electrode 121 and the electrons transported from the common electrode 10 combine to generate an electroluminescence phenomenon and emit light. Light from the electroluminescent layer 107 is emitted from the transparent substrate 100 via the pixel electrode 121 which is a transparent electrode.
【００４２】上記構成によれば、電界発光素子１２の陰
極は、共通電極１０となっており、コンタクトパターン
２を介して一定数の取出端子６１に接続されているの
で、陰極における抵抗値が低くなり、電圧降下を少なく
することができ、明るい画像表示が可能になる。抵抗値
の軽減により、消費電力が少なくなり発熱を抑制でき
る。According to the above configuration, the cathode of the electroluminescent element 12 is the common electrode 10 and is connected to the fixed number of extraction terminals 61 via the contact pattern 2, so that the resistance value at the cathode is low. As a result, a voltage drop can be reduced, and a bright image can be displayed. By reducing the resistance value, power consumption is reduced and heat generation can be suppressed.
【００４３】回路数の少ない走査方向の一辺から陰極パ
ターンを引き出し、走査駆動回路をその対向する辺に配
置し、他の回路を残された辺に配置したので、電流量が
大きい陰極パターンを相対的に短く配線でき、上記した
効果を奏する。また給電配線を提供する周辺回路までの
配線長を比較的短くできるので、その電圧降下を最小限
にとどめることができる。Since the cathode pattern is drawn from one side in the scanning direction with a small number of circuits, the scanning drive circuit is arranged on the opposite side, and the other circuit is arranged on the remaining side. The wiring can be shortened in a short time, and the above-described effects can be obtained. Further, since the length of the wiring to the peripheral circuit that provides the power supply wiring can be relatively short, the voltage drop can be minimized.
【００４４】また、取出端子を同一形状で形成したの
で、製造の容易化と経済化を図ることができる。その取
出端子を基板の一辺に配置したので、他の基板との接続
を容易にすることができる。Further, since the extraction terminals are formed in the same shape, the production can be facilitated and the economy can be improved. Since the extraction terminal is arranged on one side of the substrate, connection with another substrate can be facilitated.
【００４５】さらに、回路の隙間になっておりフィジカ
ルマスクの外側に相当する表示領域の四隅にアライメン
トマークを設けたので、パネル外形を大きくすることな
く、回路の隙間を有効利用して適切なアライメント配置
を提供でき、スペースの効率的利用を図ることができ
る。Further, since alignment marks are provided at the four corners of the display area corresponding to the outside of the physical mask, which are gaps between the circuits, appropriate alignment can be achieved by effectively utilizing the gaps between the circuits without enlarging the panel outer shape. An arrangement can be provided and efficient use of space can be achieved.
【００４６】なお、上記したような発光素子用回路基板
は、公知の薄膜プロセスを経て形成することが可能であ
る。つまり、酸化膜類をＣＶＤ法で形成し、フォトリソ
グラフィを適用してスルーホールを開口させ、スパッタ
法等で導電性膜を形成し、パターニングするという工程
を繰り返すことで製造される。 （その他の変形例）本発明は、上記実施形態に限定され
ることなく種々に変形して適用することが可能である。The light emitting element circuit board as described above can be formed through a known thin film process. That is, it is manufactured by repeating the steps of forming oxide films by a CVD method, applying photolithography to open through holes, forming a conductive film by a sputtering method or the like, and patterning. (Other Modifications) The present invention can be applied in various modifications without being limited to the above embodiment.
【００４７】例えば、上記表示素子は電界発光素子であ
ったが、これに限定なく、比較的大きな電流を消費する
あらゆる素子の回路配置に本発明を適用可能である。For example, the display element is an electroluminescent element. However, the present invention is not limited to this, and the present invention is applicable to any circuit arrangement of elements that consume a relatively large current.
【００４８】また、本発明の発光素子用回路基板は、あ
らゆる電子機器に適用可能である。電子機器に限定はな
いが、小型表示装置、ビューファインダ、ヘッドマウン
トディスプレイなどを含む。The light emitting element circuit board of the present invention is applicable to any electronic equipment. Although not limited to electronic devices, it includes a small display device, a viewfinder, a head mounted display, and the like.
【００４９】[0049]
【発明の効果】本発明の発光素子用回路基板によれば、
共通電極と引出端子との間にコンタクトパターンを設け
たので、電圧降下を極力少なくすることができ、複数の
発光素子を備える明るい画像表示を提供する表示装置の
基板として使用することが可能になる。According to the circuit board for a light emitting device of the present invention,
Since a contact pattern is provided between the common electrode and the extraction terminal, a voltage drop can be reduced as much as possible, and the substrate can be used as a substrate of a display device that provides a bright image display including a plurality of light-emitting elements. .
【図面の簡単な説明】[Brief description of the drawings]
【図１】実施形態の発光素子用回路基板の平面図。FIG. 1 is a plan view of a light emitting element circuit board according to an embodiment.
【図２】実施形態の発光素子用回路基板の断面図。FIG. 2 is a sectional view of a light emitting element circuit board according to the embodiment;
【図３】電界発光素子を用いた表示装置の全体回路図。FIG. 3 is an overall circuit diagram of a display device using an electroluminescent element.
１ 画素領域 ２ コンタクトパターン ３ 信号駆動回路 ４ 走査駆動回路 ５ 周辺回路 ６ 取出端子群 ６１ 取出端子 １０ 共通電極 １１ 電界発光素子 １２ 薄膜トランジスタ １０１ 半導体層（ｐ−Ｓｉ） １０２ ゲート絶縁膜 １０３、１０４ 層間絶縁膜 １０５、１０６ バンク層 １０７ 電界発光層（必要に応じて電子・正孔輸送層含
む） １２１ 画素電極 １３１ ソース電極 １３２ ドレイン電極 １３３ ゲート電極 ２０１ タンタル配線層（Ｔａ） ２０２ アルミ配線層（Ａｌ） ２０３ ＩＴＯ層 ２０４ 陰極層 ３０１〜３０４ コンタクトホールDESCRIPTION OF SYMBOLS 1 Pixel area 2 Contact pattern 3 Signal drive circuit 4 Scan drive circuit 5 Peripheral circuit 6 Extraction terminal group 61 Extraction terminal 10 Common electrode 11 Electroluminescent element 12 Thin film transistor 101 Semiconductor layer (p-Si) 102 Gate insulating film 103, 104 Interlayer insulation Films 105 and 106 Bank layer 107 Electroluminescent layer (including electron / hole transport layer if necessary) 121 Pixel electrode 131 Source electrode 132 Drain electrode 133 Gate electrode 201 Tantalum wiring layer (Ta) 202 Aluminum wiring layer (Al) 203 ITO layer 204 Cathode layer 301-304 Contact hole
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松枝 洋二郎 長野県諏訪市大和３丁目３番５号 セイコ ーエプソン株式会社内 (72)発明者 北和田 清文 長野県諏訪市大和３丁目３番５号 セイコ ーエプソン株式会社内 Ｆターム(参考） 3K007 AB00 AB05 BB07 CA01 CA02 CB01 CC00 CC05 DA00 DB03 EB00 GA00 5C094 AA02 AA21 BA27 DA09 EA05 EA07 EB02 FB01 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yojiro Matsueda 3-3-5 Yamato, Suwa-shi, Nagano Seiko Epson Corporation (72) Inventor Kiyofumi Kitawada 3-5-2-5, Yamato, Suwa-shi, Nagano Seiko -F term in Epson Corporation (reference) 3K007 AB00 AB05 BB07 CA01 CA02 CB01 CC00 CC05 DA00 DB03 EB00 GA00 5C094 AA02 AA21 BA27 DA09 EA05 EA07 EB02 FB01
Claims (13)
回路基板において、 外部への取出端子が当該基板の一辺に集積された取出端
子群と、 所定の共通電極が配置される領域と前記取出端子群との
間に、前記取出端子群の一部の取出端子と前記共通電極
とを電気的に接続するコンタクトパターンと、を備えて
いることを特徴とする発光素子用回路基板。1. A light emitting element circuit board used for forming a light emitting element, comprising: an extraction terminal group in which extraction terminals to the outside are integrated on one side of the substrate; a region where a predetermined common electrode is arranged; A circuit board for a light emitting element, comprising: a contact pattern for electrically connecting a part of the extraction terminal group and the common electrode to the terminal group.
素子の形成に用いられ、前記コンタクトパターンは、前
記取出端子群の一部と前記発光素子の電流が共通して流
れる共通電極とを電気的に接続するように形成される請
求項１に記載の発光素子用回路基板。2. The method according to claim 1, wherein the contact pattern electrically connects a part of the extraction terminal group and a common electrode through which a current of the light emitting element flows in common. The light emitting element circuit board according to claim 1, wherein the circuit board is formed so as to be connected to the light emitting element.
る請求項２に記載の発光素子用回路基板。3. The circuit board according to claim 2, wherein the light emitting device is an organic electroluminescent device.
求項１乃至請求項３のいずれか一項に記載の発光素子用
回路基板。4. The circuit board for a light emitting device according to claim 1, wherein the contact pattern has an area of 10% or more of an area of the common electrode.
乃至請求項３のいずれか一項に記載の発光素子用回路基
板。5. The extraction terminal group is provided with extraction terminals having the same shape.
A light-emitting element circuit board according to any one of claims 1 to 3.
る領域に、走査配線に走査信号を供給するための走査駆
動回路を備えている請求項１乃至請求項３のいずれか一
項に記載の発光素子用回路基板。6. A common electrode to be formed is a square, and a scan drive circuit for supplying a scan signal to a scan line is provided in a region facing the contact pattern via the common electrode. A light-emitting element circuit board according to any one of claims 1 to 3.
回路が設けられる前記共通電極の周辺領域以外の領域
に、信号配線に画像信号を供給するための信号駆動回路
および／または周辺回路を形成する領域を備えている請
求項６に記載の発光素子用回路基板。7. A region for forming a signal driving circuit and / or a peripheral circuit for supplying an image signal to a signal wiring is provided in a region other than a peripheral region of the common electrode where the contact pattern and the scanning driving circuit are provided. The light emitting element circuit board according to claim 6, wherein
電極を形成する領域の四隅にアライメントマークを備え
ている請求項５に記載の発光素子用回路基板。8. The circuit board for a light emitting device according to claim 5, wherein alignment marks are provided at four corners of a region where the common electrode is not provided with any circuit.
記載の発光素子用回路基板を備えていることを特徴とす
る電子機器。9. An electronic device comprising the light emitting element circuit board according to claim 1. Description:
に記載の発光素子用回路基板と、 前記回路基板上に各画素に対応して設けられた複数の発
光素子と、を備え、 前記発光素子に対する制御により画像を表示する表示装
置。10. A light-emitting element circuit board according to claim 1, comprising: a plurality of light-emitting elements provided on the circuit board corresponding to each pixel; A display device for displaying an image by controlling the light emitting element.
画素の発光素子の駆動制御を行うトランジスタを備える
請求項１０に記載の表示装置。11. The display device according to claim 10, further comprising a transistor corresponding to the light emitting element of each of the pixels, the transistor controlling driving of the light emitting element of the pixel.
子であり、各画素において、前記発光素子の制御用トラ
ンジスタと駆動用トランジスタとを備える請求項１１に
記載の表示装置。12. The display device according to claim 11, wherein the light emitting element is a current control type light emitting element, and each pixel includes a control transistor and a drive transistor of the light emitting element.
と、当該画素電極と前記共通電極との間に少なくとも有
機発光材料からなる発光層を備えている請求項１１また
は請求項１２のいずれかに記載の表示装置。13. The light-emitting element in each pixel, comprising: a pixel electrode; and a light-emitting layer made of at least an organic light-emitting material between the pixel electrode and the common electrode. The display device according to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16755699A JP4075028B2 (en) | 1999-06-14 | 1999-06-14 | Circuit board, display device, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16755699A JP4075028B2 (en) | 1999-06-14 | 1999-06-14 | Circuit board, display device, and electronic device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007278631A Division JP2008034405A (en) | 2007-10-26 | 2007-10-26 | Electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000357584A true JP2000357584A (en) | 2000-12-26 |
| JP4075028B2 JP4075028B2 (en) | 2008-04-16 |
Family
ID=15851922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16755699A Expired - Lifetime JP4075028B2 (en) | 1999-06-14 | 1999-06-14 | Circuit board, display device, and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4075028B2 (en) |
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