TWI386105B - Display panel - Google Patents
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- TWI386105B TWI386105B TW094122047A TW94122047A TWI386105B TW I386105 B TWI386105 B TW I386105B TW 094122047 A TW094122047 A TW 094122047A TW 94122047 A TW94122047 A TW 94122047A TW I386105 B TWI386105 B TW I386105B
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- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
- H10K50/17—Carrier injection layers
- H10K50/171—Electron injection layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/82—Cathodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/805—Electrodes
- H10K59/8052—Cathodes
- H10K59/80523—Multilayers, e.g. opaque multilayers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Illuminated Signs And Luminous Advertising (AREA)
Description
本發明相關於顯示器面板且尤其,相關於用在有機發光二極體顯示器之面板。The invention relates to display panels and in particular to panels for use in organic light emitting diode displays.
通常,一有機發光二極體(OLED)顯示器為利用激發可發光有機材料以發光而顯示影像之自身發光顯示器裝置。有機發光二極體顯示器之發光要件包含一陽極(電洞注入電極)、一陰極(電子注入電極)及一插入於其中之有機發光層。當電洞與電子係注入發光層內,它們結合並當從激態轉移至基態時發光。該有機發光層可進一步包含一或更多個電子傳輸層(ETL)與電洞傳輸層(HTL),以及電子注入層(EIL)與電洞注入層(HIL)以提升光發射。Generally, an organic light emitting diode (OLED) display is a self-luminous display device that displays an image by exciting an illuminable organic material to emit light. The light-emitting element of the organic light-emitting diode display includes an anode (hole injection electrode), a cathode (electron injection electrode), and an organic light-emitting layer inserted therein. When holes and electrons are injected into the luminescent layer, they combine and illuminate when transferred from the excited state to the ground state. The organic light emitting layer may further include one or more electron transport layer (ETL) and hole transport layer (HTL), and an electron injection layer (EIL) and a hole injection layer (HIL) to enhance light emission.
該有機發光二極體顯示器包含數個像素,且每個像素包含一陽極、一陰極與一發光層。該像素可排列成一陣列,且係可以被動陣列(或單一陣列)形式或主動陣列形式而驅動。The organic light emitting diode display comprises a plurality of pixels, and each pixel comprises an anode, a cathode and a light emitting layer. The pixels can be arranged in an array and can be driven in the form of a passive array (or a single array) or an active array.
被動陣列式有機發光二極體顯示器包含數條陽極線、數條與陽極線交叉之陰極線,以及數個像素,每一像素包含發光層。選擇一陽極線與一陰極線造成位於受選擇訊號線之交叉處的像素發光。The passive array organic light emitting diode display comprises a plurality of anode lines, a plurality of cathode lines crossing the anode lines, and a plurality of pixels, each of the pixels comprising a light emitting layer. Selecting an anode line and a cathode line causes the pixels at the intersection of the selected signal lines to illuminate.
主動陣列式有機發光二極體顯示器包含數個像素,且每個像素可包含一切換電晶體、一驅動電晶體與一儲存電容以及一陽極、一陰極與一發光層。該主動陣列式有機發光二極體顯示器進一步包含數條傳輸閘極訊號之閘極線與數條傳輸資料電壓之資料線。切換電晶體連結至一閘極線與一資料線,且其自資料線對應來自閘極線之閘極訊號傳輸資料電壓。驅動電晶體自切換電晶體接收資料電壓並驅動符合資料電壓所需之電流量。來自驅動電晶體之電流進入發光層以導致具有依據電流大小之強度的光發射。儲存電容係連結介於資料電壓與供應電壓之間以維持其壓差。該主動陣列式有機發光二極體顯示器之灰階係由控制資料電壓而達成以調整由驅動電晶體驅動之電流。該有機發光二極體顯示器以供應紅、綠與藍色發光層表示顏色。The active array organic light emitting diode display comprises a plurality of pixels, and each pixel can include a switching transistor, a driving transistor and a storage capacitor, and an anode, a cathode and a light emitting layer. The active array type organic light emitting diode display further includes a plurality of gate lines for transmitting gate signals and a plurality of data lines for transmitting data voltages. The switching transistor is coupled to a gate line and a data line, and the data line corresponds to the gate signal transmission data voltage from the gate line. The driving transistor receives the data voltage from the switching transistor and drives the amount of current required to meet the data voltage. Current from the driving transistor enters the luminescent layer to cause light emission having an intensity depending on the magnitude of the current. The storage capacitor is connected between the data voltage and the supply voltage to maintain the voltage difference. The gray scale of the active array type organic light emitting diode display is achieved by controlling the data voltage to adjust the current driven by the driving transistor. The organic light emitting diode display represents a color by supplying red, green and blue light emitting layers.
此外,有機發光二極體顯示器根據光發射方向可分為上發光式與下發光式顯示器。上發光式有機發光二極體顯示器包含通常以銦錫氧化物(ITO)或銦鋅氧化物(IZO)製成之一透明陰極,以及一不透明陽極。相反地,下發光式有機發光二極體顯示器包含一不透明陰極與一透明陽極。陽極與陰極之相關位置可依據需要而改變。In addition, the organic light emitting diode display can be classified into an upper light emitting type and a lower light emitting type display according to the light emitting direction. The upper luminescent organic light emitting diode display comprises a transparent cathode typically made of indium tin oxide (ITO) or indium zinc oxide (IZO), and an opaque anode. Conversely, the lower-emitting organic light-emitting diode display includes an opaque cathode and a transparent anode. The position of the anode and cathode can be varied as needed.
陰極係經另一導體以一般電壓提供,且介於陰極與導體間之接觸電阻為高。The cathode is supplied at a general voltage via another conductor, and the contact resistance between the cathode and the conductor is high.
本發明提供可減少介於一般電極與一般電壓線間之接觸電阻的一有機發光二極體裝置。The present invention provides an organic light emitting diode device that reduces the contact resistance between a general electrode and a general voltage line.
本發明之其他特徵係於本敘述中提出,且在某種程度上自該敘述可顯而易見,或藉由本發明實際應用而習知。Other features of the invention are set forth in this description and will be apparent from the description, or by the practical application of the invention.
本發明揭露包含數條陽極電極與以預定電壓供應之陰極電極的一有機發光顯示器面板,並包含面對陽極電極之一第一部分、接收預定電壓並具有不同於第一部分其橫截面的第二部分。數個發光組件係配置介於陽極電極與陰極電極之間,且一導線傳輸預定電壓並接觸陰極電極其第二部分。The present invention discloses an organic light emitting display panel comprising a plurality of anode electrodes and a cathode electrode supplied at a predetermined voltage, and comprising a first portion facing the anode electrode, receiving a predetermined voltage and having a second portion different from the cross section of the first portion . A plurality of light emitting components are disposed between the anode electrode and the cathode electrode, and a wire transmits a predetermined voltage and contacts the second portion of the cathode electrode.
本發明亦揭露包含數條陽極電極、數個分別配置於陽極電極上之發光組件、包括配置於發光組件上之一第一部分和與發光組件分離之第二部分的一金屬層,以及連結金屬層第二部分之一導線的一有機發光顯示器面板。該導線係配置於發光組件所在層之下方層。The invention also discloses a plurality of anode electrodes, a plurality of light-emitting components respectively disposed on the anode electrodes, a metal layer including a first portion disposed on the light-emitting assembly and a second portion separated from the light-emitting assembly, and a connecting metal layer An organic light emitting display panel of one of the wires of the second portion. The wire is disposed under the layer where the light emitting component is located.
可了解到上面敘述與下列詳細敘述皆為具模範性與解釋用意,並意圖提供如主張之本發明其進一步說明。The above description and the following detailed description are intended to be illustrative and illustrative,
係包含以對本發明提供進一步了解且係併入且構成本規格之一部分之伴隨圖示說明本發明實施例且與敘述一起用於解釋本發明之原理。The accompanying drawings, which are incorporated in and in the claims
第1圖根據本發明實施例為一有機發光二極體顯示器其方塊圖。1 is a block diagram of an organic light emitting diode display in accordance with an embodiment of the present invention.
第2圖根據本發明實施例為一有機發光二極體顯示器中一像素之等效電路圖。2 is an equivalent circuit diagram of a pixel in an organic light emitting diode display according to an embodiment of the invention.
第3圖根據本發明實施例為一有機發光二極體顯示器其顯示器面板的結構平面圖。3 is a plan view showing the structure of a display panel of an organic light emitting diode display according to an embodiment of the present invention.
第4圖為沿第3圖中顯示器面板其線段IV-IV’之截面圖。Figure 4 is a cross-sectional view taken along line IV-IV' of the display panel of Figure 3.
第5圖為第3圖中顯示器面板上像素與訊號線之佈局圖。Figure 5 is a layout diagram of the pixels and signal lines on the display panel in Figure 3.
第6圖與第7圖分別為沿第5圖中像素與訊號線其線段VI-VI’與VII-VII’之截面圖。Fig. 6 and Fig. 7 are cross-sectional views of the line segments VI-VI' and VII-VII' taken along the pixel and signal lines in Fig. 5, respectively.
第8圖根據本發明實施例為一有機發光要件之結構圖。Figure 8 is a structural view of an organic light-emitting element according to an embodiment of the present invention.
第9圖、第11圖、第13圖、第15圖、第17圖、第19圖、第21圖、第23圖與第25圖根據本發明實施例為第3圖、第4圖、第5圖、第6圖與第7圖中所示之顯示器面板在製程中間步驟之佈局圖。Fig. 9, Fig. 11, Fig. 13, Fig. 15, Fig. 17, Fig. 19, Fig. 21, Fig. 23 and Fig. 25 are diagrams 3, 4, and 4 according to an embodiment of the present invention. The layout of the display panel shown in Figure 5, Figure 6, and Figure 7 in the middle of the process.
第10A圖與第10B圖分別為沿第9圖中顯示器面板其線段XA-XA’與XB-XB’之截面圖,而第10C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。10A and 10B are cross-sectional views of the line segments XA-XA' and XB-XB' of the display panel of FIG. 9, respectively, and FIG. 10C is the line segment IV-IV' of the display panel of FIG. 3 A cross-sectional view of the steps.
第12A圖與第12B圖分別為沿第11圖中顯示器面板其線段XIIA-XIIA’與XIIB-XIIB’之截面圖,而第12C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。12A and 12B are cross-sectional views of the line segments XIIA-XIIA' and XIIB-XIIB' of the display panel of Fig. 11, respectively, and Fig. 12C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第14A圖與第14B圖分別為沿第13圖中顯示器面板其線段XIVA-XIVA’與XIVB-XIVB’之截面圖,而第14C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。14A and 14B are cross-sectional views of the line segments XIVA-XIVA' and XIVB-XIVB' of the display panel of Fig. 13, respectively, and Fig. 14C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第16A圖與第16B圖分別為沿第15圖中顯示器面板其線段XVIA-XVIA’與XVIB-XVIB’之截面圖,而第16C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。16A and 16B are cross-sectional views of the line segments XVIA-XVIA' and XVIB-XVIB' of the display panel of Fig. 15, respectively, and Fig. 16C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第18A圖與第18B圖分別為沿第17圖中顯示器面板其線段XVIIIA-XVIIIA’與XVIIIB-XVIIIB’之截面圖,而第18C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。18A and 18B are cross-sectional views of the line segments XVIIIA-XVIIIA' and XVIIIB-XVIIIB' of the display panel of Fig. 17, respectively, and Fig. 18C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第20A圖與第20B圖分別為沿第19圖中顯示器面板其線段XXA-XXA’與XXB-XXB’之截面圖,而第20C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。20A and 20B are cross-sectional views of the line segments XXA-XXA' and XXB-XXB' of the display panel of Fig. 19, respectively, and Fig. 20C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第22A圖與第22B圖分別為沿第21圖中顯示器面板其線段XXIIA-XXIIA’與XXIIB-XXIIB’之截面圖,而第22C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。22A and 22B are cross-sectional views of the line segments XXIIA-XXIIA' and XXIIB-XXIIB' of the display panel of Fig. 21, respectively, and Fig. 22C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第24A圖與第24B圖分別為沿第23圖中顯示器面板其線段XXIVA-XXIVA’與XXIVB-XXIVB’之截面圖,而第24C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。Figure 24A and Figure 24B are cross-sectional views of the line segments XXIVA-XXIVA' and XXIVB-XXIVB' of the display panel of Figure 23, respectively, and Figure 24C is the line segment IV-IV' of the display panel of Figure 3 A cross-sectional view of the steps.
第26A圖與第26B圖分別為沿第25圖中顯示器面板其線段XXVIA-XXVIA’與XXVIB-XXVIB’之截面圖,而第26C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。Figure 26A and Figure 26B are cross-sectional views of the line segments XXVIA-XXVIA' and XXVIB-XXVIB' of the display panel of Figure 25, respectively, and Figure 26C is the line segment IV-IV' of the display panel of Figure 3 A cross-sectional view of the steps.
第27A圖與第27B圖分別為沿第25圖中顯示器面板其線段XXVIA-XXVIA’與XXVIB-XXVIB’之截面圖,並說明第26A圖與第26B圖中所示步驟之下一步驟,而第27C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。Figure 27A and Figure 27B are cross-sectional views of the line segments XXVIA-XXVIA' and XXVIB-XXVIB' along the display panel of Figure 25, respectively, and illustrate the steps below the steps shown in Figures 26A and 26B, and Figure 27C is a cross-sectional view of the display panel of Figure 3 taken along line IV-IV' at this step.
本發明將參照含本發明例示實施例之伴隨圖示完全敘述。然而,本發明將以各種形式具體化且不應受限於此處實施例而說明。The invention will be fully described with reference to the accompanying drawings, in which However, the invention will be embodied in various forms and should not be construed as being limited to the embodiments herein.
圖示中,層、薄膜、面板、區域等等之厚度係誇大以便於明瞭。相同編號完全參照於相同要件。可以了解到當一要件如層、薄膜、區域或基體係稱為“另一要件”時,其可直接為“其他要件”或“干擾要件”係用以表示。相對的,當一要件係稱為“直接在另一要件上”,沒有“干擾要件”係用以表示。In the drawings, the thickness of layers, films, panels, regions, and the like are exaggerated for clarity. The same numbers are fully referenced to the same elements. It can be understood that when a component such as a layer, film, region or base system is referred to as "another requirement", it can be directly indicated as "other elements" or "interference requirements". In contrast, when a requirement is referred to as “directly on another requirement”, no “interference requirement” is used to indicate.
現在,根據本發明實施例,用於一有機發光二極體顯示器之顯示器面板與其製程將參照伴隨圖示係敘述。Now, in accordance with an embodiment of the present invention, a display panel for an organic light emitting diode display and a process thereof will be described with reference to the accompanying drawings.
第1圖根據本發明一實施例為一有機發光二極體顯示器之方塊圖,且第2圖根據本發明一實施例為一有機發光二極體顯示器中像素之等效電路圖。1 is a block diagram of an organic light emitting diode display according to an embodiment of the invention, and FIG. 2 is an equivalent circuit diagram of a pixel in an organic light emitting diode display according to an embodiment of the invention.
參照第1圖,根據本發明一實施例之一有機發光二極體顯示器包含一顯示器面板300與兩包含連結至顯示器面板300之一掃描驅動器400與一資料驅動器500的驅動器。Referring to FIG. 1, an organic light emitting diode display according to an embodiment of the present invention includes a display panel 300 and two drivers including a scan driver 400 and a data driver 500 coupled to the display panel 300.
該顯示器面板300包含數條訊號線,而數條像素PX係向訊號線連結且實質排列於陣列中。The display panel 300 includes a plurality of signal lines, and the plurality of pixels PX are connected to the signal lines and substantially arranged in the array.
訊號線包含數條用以傳輸掃描訊號之掃描線G1 -Gn 及數條用以傳輸資料訊號之資料線sD1 -Dm 。掃描線G1 -Gn 實質以“列”方向延伸且兩兩相互平行,而資料線D1 -Dm 實質以“行”方向延伸且兩兩相互平行。The signal line includes a plurality of scanning lines G 1 -G n for transmitting scanning signals and a plurality of data lines sD 1 -D m for transmitting data signals. Scan lines G 1 -G n in essence "column" direction and extend mutually parallel two by two, while the data lines D 1 -D m in essence "row" direction extending parallel two by two to each other.
參照第2圖,例如,每個像素PX係連結至一掃描線Gi 與一資料線Dj 且包含一有機發光要件LD、一驅動電晶體Qd、一電容器Cst與一切換電晶體Qs。Referring to FIG. 2, for example, each pixel PX is coupled to a scan line G i and a data line D j and includes an organic light emitting element LD, a driving transistor Qd, a capacitor Cst, and a switching transistor Qs.
驅動電晶體Qd具有一連結至切換電晶體Qs之控制終點、一連結至驅動電壓Vp之輸入終點與一連結至發光要件LD之輸出終點。The driving transistor Qd has a control end point connected to the switching transistor Qs, an input end point connected to the driving voltage Vp, and an output end point connected to the light emitting element LD.
發光要件LD具有一連結至驅動電晶體Qd之輸出終點的陽極與一連結至一般電壓Vcom的陰極。該一般電壓Vcom可小於驅動電壓Vp且為底電壓。該發光要件LD依據驅動電晶體Qd之輸出電流發出具有強度的光,且驅動電晶體Qd之輸出電流取決於驅動電晶體Qd中介於控制終點與輸入終點之電壓。The light-emitting element LD has an anode connected to the output end of the driving transistor Qd and a cathode connected to the general voltage Vcom. The general voltage Vcom can be less than the driving voltage Vp and is the bottom voltage. The light-emitting element LD emits light having intensity according to the output current of the driving transistor Qd, and the output current of the driving transistor Qd depends on the voltage between the control end point and the input end point in the driving transistor Qd.
切換電晶體Qs具有一連結至掃描線Gi 之一控制終點,一連結至資料線Dj之輸入終點與一連結至驅動電晶體Qd控制終點之輸出終點。該切換電晶體Qs對應來自掃描線Gi 之掃描訊號從資料線Dj傳輸資料訊號至驅動電晶體Qd。The switching transistor Qs has a control end point connected to the scanning line G i , an input end point connected to the data line Dj and an output end point connected to the control end point of the driving transistor Qd. The switching transistor Qs transmits a data signal from the data line Dj to the driving transistor Qd corresponding to the scanning signal from the scanning line G i .
如第2圖所示,切換電晶體Qs為N-通道場效電晶體(FET),而驅動電晶體Qd為P-通道場效電晶體。然而其種類可相交換或皆為N-通道場效電晶體或皆為P-通道場效電晶體。此例示中,介於電晶體Qs與Qd及發光要件LD間之連接係可改良。As shown in Fig. 2, the switching transistor Qs is an N-channel field effect transistor (FET), and the driving transistor Qd is a P-channel field effect transistor. However, the types may be interchanged or both N-channel field effect transistors or both P-channel field effect transistors. In this illustration, the connection between the transistors Qs and Qd and the light-emitting element LD can be improved.
電晶體Qs與Qd包含多晶矽或非晶矽。The transistors Qs and Qd contain polycrystalline germanium or amorphous germanium.
電容器Cst係連結驅動電晶體Qd之控制終點與輸入終點。電容器Cst充電並對應由驅動電晶體Qd控制終點提供之資料訊號而維持電壓。The capacitor Cst is connected to the control end point and the input end point of the driving transistor Qd. Capacitor Cst is charged and maintains the voltage corresponding to the data signal provided by the drive transistor Qd control terminal.
再參照第1圖,掃描驅動器400係連結至顯示器面板300之掃描線G1 -Gn 且形成閘極開啟電壓Von以開啟切換電晶體Qs及閘極關閉電壓Voff以關閉切換電晶體sQs進而產生掃描訊號以提供至掃描線sG1 -Gn 。Referring again to FIG.1, the scan driver 400 system coupled to the scan line display panel 300 of G 1 -G n and forming a gate on voltage Von to turn on the switching transistor Qs and the gate-off voltage Voff to turn off the switching transistor sQs thereby generating The signal is scanned to provide to the scan lines sG 1 -G n .
資料驅動器500係連結至顯示器面板300之資料線D1 -Dm 且提供資料訊號至資料線D1 -Dm 。The data driver 500 is coupled to the data lines D 1 -D m of the display panel 300 and provides data signals to the data lines D 1 -D m .
掃描驅動器400與資料驅動器500係可作為嵌入於顯示器面板300上或捲帶式封裝中附著於顯示器面板300之軟形印刷電路(FPC)薄膜上的積體電路晶片。選擇性地,它們係可整合至顯示器面板300。The scan driver 400 and the data driver 500 can be used as integrated circuit wafers embedded on the flexible printed circuit (FPC) film of the display panel 300 embedded in the display panel 300 or in a tape and reel package. Alternatively, they can be integrated into the display panel 300.
現在,根據本發明實施例用於一有機發光二極體顯示器之一顯示器面板其結構如第1圖至第2圖係將於第3圖至第8圖詳細敘述。Now, a display panel for an organic light-emitting diode display according to an embodiment of the present invention has a structure as shown in FIGS. 1 to 2 in detail in FIGS. 3 to 8.
第3圖根據本發明實施例為用於一有機發光二極體顯示器之一顯示器面板之結構平面圖,第4圖為沿第3圖中顯示器面板其線段IV-IV,之截面圖,第5圖為第3圖中顯示器面板上像素與訊號線之佈局圖,第6圖與第7圖分別為沿第5圖中像素與訊號線其線段VI-VI’與VII-VII’之截面圖,且第8圖根據本發明實施例為一有機發光要件之結構圖。3 is a plan view showing a structure of a display panel for an organic light emitting diode display according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV of the display panel of FIG. 3, FIG. Figure 3 is a cross-sectional view of the pixel and signal lines on the display panel in Fig. 3, and Fig. 6 and Fig. 7 are respectively sectional views of the line segments VI-VI' and VII-VII' along the pixel and signal lines in Fig. 5, and Figure 8 is a structural view of an organic light-emitting element according to an embodiment of the present invention.
參照第3圖,根據本發明實施例一顯示器面板300包含一顯示區域DA(由點狀長方形所包圍)與配置於顯示區域DA外之一週邊區域PA。該顯示區域DA包含數個像素PX。Referring to FIG. 3, a display panel 300 according to an embodiment of the present invention includes a display area DA (enclosed by a dot-shaped rectangle) and a peripheral area PA disposed outside the display area DA. The display area DA contains a plurality of pixels PX.
作為有機發光要件LD陰極之一般電極270,係也由顯示器面板300提供。一般電極270覆蓋顯示區域DA且包含配置於週邊區域PA內之接觸部分B以接收一般電壓Vcom。一般電極270之接觸部分B係連結至包含一般電壓觸墊279以自外部裝置接收一般電壓Vcom的一般電壓線278。The general electrode 270, which is the cathode of the organic light-emitting element LD, is also provided by the display panel 300. The general electrode 270 covers the display area DA and includes a contact portion B disposed in the peripheral area PA to receive a general voltage Vcom. Contact portion B of electrode 270 is typically coupled to a common voltage line 278 that includes a general voltage contact pad 279 to receive a general voltage Vcom from an external device.
包含掃描線G1 -Gn 與資料線D1 -Dn 之數條訊號線係也由顯示器面板300提供。訊號線包含配置於顯示區域DA之部分及配置於週邊區域內以接收包含掃描訊號及資料訊號之訊號的終點部分。Comprising scanning lines G 1 -G n and data lines D 1 -D n number of the signal line is also provided by the display panel 300. The signal line includes a portion disposed in the display area DA and disposed in the peripheral area to receive an end portion of the signal including the scan signal and the data signal.
掃描驅動器400與資料驅動器500係可配置於顯示器面板300外部,配置於週邊區域PA上,或沿像素與訊號線整合於顯示器面板300之週邊區域PA內。The scan driver 400 and the data driver 500 can be disposed outside the display panel 300, disposed on the peripheral area PA, or integrated in the peripheral area PA of the display panel 300 along the pixels and signal lines.
接著,參照第3圖、第4圖、第5圖、第6圖與第7圖,詳細之顯示器面板層結構係將敘述。Next, referring to Figs. 3, 4, 5, 6, and 7, the detailed display panel layer structure will be described.
以氧化矽或氮化矽組成之阻隔層111係形成於以透明玻璃形成之一絕緣基體110上。阻隔層111可具有雙層結構。A barrier layer 111 composed of tantalum oxide or tantalum nitride is formed on one of the insulating substrates 110 formed of transparent glass. The barrier layer 111 may have a two-layer structure.
以多晶矽或非晶矽形成之數個半導體島151a與151b係形成於阻隔薄膜111上。每個半導體島151a與151b可包含具N-型或P-型導電雜質之數個非本質區及至少一個幾乎不包含導電雜質之本質區。A plurality of semiconductor islands 151a and 151b formed of polycrystalline germanium or amorphous germanium are formed on the barrier film 111. Each of the semiconductor islands 151a and 151b may include a plurality of non-essential regions having N-type or P-type conductive impurities and at least one essential region containing almost no conductive impurities.
就用於切換薄膜電晶體(TFT)Qs之半導體島151a而論,非本質區包含一第一源極區153a,一中間區1535及已摻雜N-型雜質且兩兩分離之一第一汲極區155a,而本質區包含一對配置於非本質區153a、1535與155a之間的(第一)通道區154a1與154a2。Regarding the semiconductor island 151a for switching the thin film transistor (TFT) Qs, the non-essential region includes a first source region 153a, an intermediate region 1535 and an already doped N-type impurity and one of the two separated first The drain region 155a, and the essential region includes a pair of (first) channel regions 154a1 and 154a2 disposed between the non-essential regions 153a, 1535 and 155a.
至於用作驅動薄膜電晶體Qd之半導體島151b,非本質區包含一第二源極區153b與已摻雜P-型雜質且兩兩分離之一第二汲極區155b,而本質區包含配置介於第二源極區153b與第二汲極區155b的一通道區154b。第二源極區153b延伸以形成儲存電極區157。As for the semiconductor island 151b used as the driving thin film transistor Qd, the non-essential region includes a second source region 153b and a doped P-type impurity and one of the two is separated from the second gate region 155b, and the essential region includes the configuration. A channel region 154b between the second source region 153b and the second drain region 155b. The second source region 153b extends to form the storage electrode region 157.
非本質區可進一步包含配置介於通道區154a1、154a2與154b之微量摻雜區域(未顯示)及源極和汲極區153a、155a、153b與155b。該微量摻雜區域係可以不具雜質之支管區域取代。The non-essential region may further include a plurality of doped regions (not shown) and source and drain regions 153a, 155a, 153b, and 155b disposed between the channel regions 154a1, 154a2, and 154b. The microdoped region can be replaced by a branch region that is free of impurities.
另外,根據驅動條件,第一半導體島151a的非本質區153a與155a係可摻雜入P-型雜質,而第二半導體島151b的非本質區153b與155b係可摻雜入N-型雜質。該導電雜質包含如硼(B)與鎵(Ga)之P-型雜質和如磷(P)與砷(As)之N-型雜質。In addition, according to the driving conditions, the non-essential regions 153a and 155a of the first semiconductor island 151a may be doped with P-type impurities, and the non-essential regions 153b and 155b of the second semiconductor island 151b may be doped with N-type impurities. . The conductive impurities include P-type impurities such as boron (B) and gallium (Ga) and N-type impurities such as phosphorus (P) and arsenic (As).
半導體島151a與151b由非晶矽所製造。此例示中沒有雜質區,且歐姆接觸可形成於半導體島151a與151b上以提升半導體島151a與151b與金屬層間之接觸性質。The semiconductor islands 151a and 151b are made of amorphous germanium. There is no impurity region in this illustration, and ohmic contacts may be formed on the semiconductor islands 151a and 151b to enhance the contact property between the semiconductor islands 151a and 151b and the metal layer.
由氧化矽或氮化矽組成之閘極絕緣層140係形成於半導體島151a與151b與阻隔薄膜111上。A gate insulating layer 140 composed of hafnium oxide or tantalum nitride is formed on the semiconductor islands 151a and 151b and the barrier film 111.
數個包含數條閘極線121之閘極導體,包括數個第一閘極電極124a與第二閘極電極124b係形成於閘極絕緣層140上。A plurality of gate conductors including a plurality of gate lines 121 include a plurality of first gate electrodes 124a and second gate electrodes 124b formed on the gate insulating layer 140.
傳送閘極訊號之閘極線121實質沿水平方向延伸。每一對第一閘極電極自閘極線121向上突起,且穿越第一半導體島151a以致其與第一通道區對154a1與154a2相重疊。每一條閘極線121包含具有一大區域以與其他層或一外部驅動電路連結之一擴張末端區。該閘極線121可直接連接至閘極驅動電路以產生可合併至基體110之閘極訊號。The gate line 121 for transmitting the gate signal substantially extends in the horizontal direction. Each pair of first gate electrodes protrudes upward from the gate line 121 and traverses the first semiconductor island 151a such that it overlaps with the first channel region pair 154a1 and 154a2. Each of the gate lines 121 includes an extended end region having a large area to be coupled to other layers or an external drive circuit. The gate line 121 can be directly connected to the gate drive circuit to generate a gate signal that can be incorporated into the base 110.
第二閘極電極124b與閘極線121分隔且穿越第二半導體島151b以致其與第二通道區154b相重疊。第二閘極電極124b延伸以形成與第二半導體島151b之儲存電極區157重疊的儲存電極127,因而形成儲存電容Cst。The second gate electrode 124b is spaced apart from the gate line 121 and traverses the second semiconductor island 151b such that it overlaps the second channel region 154b. The second gate electrode 124b extends to form a storage electrode 127 overlapping the storage electrode region 157 of the second semiconductor island 151b, thus forming a storage capacitor Cst.
閘極導體121與124b可以包含鋁或鋁合金(例如,Al-Nd)、銀或銀合金、銅或銅合金等低阻抗材料製成。該閘極導體121與124b可為包含兩具不同物理特性之薄膜的多層結構。此例示中,兩薄膜之一可以低阻抗金屬如含鋁金屬、含銀金屬與含銅金屬製成以降低訊號延遲或閘極導體121與124b中電壓下降。另一薄膜可以具有良好物理、化學性質及與其他材料,如銦錫氧化物(ITO)或銦鋅氧化物(IZO)之優良電性接觸特性之材料如鉻、鉬、鉬合金、鉭或鈦等製成。層狀結構之例示包含一下層鉻薄膜與一上層鋁-釹合金薄膜和一下層鋁薄膜與一上層鉬薄膜。The gate conductors 121 and 124b may be made of a low-impedance material such as aluminum or an aluminum alloy (for example, Al-Nd), silver or a silver alloy, copper or a copper alloy. The gate conductors 121 and 124b may be a multilayer structure including two films having different physical properties. In this illustration, one of the two films can be made of a low-resistance metal such as an aluminum-containing metal, a silver-containing metal, and a copper-containing metal to reduce signal delay or voltage drop in the gate conductors 121 and 124b. The other film may have good physical and chemical properties and materials having excellent electrical contact properties with other materials such as indium tin oxide (ITO) or indium zinc oxide (IZO) such as chromium, molybdenum, molybdenum alloy, tantalum or titanium. Made. An example of the layered structure comprises a lower layer of chromium film and an upper layer of aluminum-bismuth alloy film and a lower layer of aluminum film and an upper layer of molybdenum film.
此外,閘極導體121與124b之側端可相對於在30至80度間之基體110表面而傾斜。Further, the side ends of the gate conductors 121 and 124b may be inclined with respect to the surface of the base 110 between 30 and 80 degrees.
一界絕緣層160係形成於閘極導體121與124b上。該界絕緣層160係可以具優良平坦性質之感光有機材料,以電漿輔助化學氣相沉積法(PECVD)形成之低介電絕緣材料如非晶矽:C:O與非晶矽:O:F或如氮化矽及氧化矽之無機材料所製成。A boundary insulating layer 160 is formed on the gate conductors 121 and 124b. The boundary insulating layer 160 is a photosensitive organic material having excellent flat properties, and a low dielectric insulating material such as amorphous germanium formed by plasma assisted chemical vapor deposition (PECVD): C: O and amorphous germanium: O: F or an inorganic material such as tantalum nitride and tantalum oxide.
該界絕緣層160具有多個接觸到第二閘極電極124b之接觸電洞164。此外,該界絕緣層160與閘極絕緣層140具有數個分別接觸到源極區153a與153b和汲極區155a與155b之接觸電洞163a、163b、165a及165b。The boundary insulating layer 160 has a plurality of contact holes 164 that contact the second gate electrode 124b. In addition, the boundary insulating layer 160 and the gate insulating layer 140 have a plurality of contact holes 163a, 163b, 165a, and 165b that are in contact with the source regions 153a and 153b and the drain regions 155a and 155b, respectively.
數個包含數個資料線171、數個驅動電壓線172、數個第一與第二汲極電極175a與175b及一般電壓線278之資料導體係形成於界絕緣薄膜160上。A plurality of data guiding systems including a plurality of data lines 171, a plurality of driving voltage lines 172, a plurality of first and second drain electrodes 175a and 175b, and a general voltage line 278 are formed on the boundary insulating film 160.
傳送資料訊號的資料線171實質沿垂直方向延伸並穿過閘極線121。每條資料線171包含數個穿越接觸電洞163a而連結至第一源極區153a之第一源極電極173a。每條資料線171包含一具有一大區域以與其他層或一外部驅動電路連結之一擴張末端區。該資料線171可直接連接至資料驅動電路以產生可合併至基體110上之資料訊號。The data line 171 transmitting the data signal extends substantially in the vertical direction and passes through the gate line 121. Each of the data lines 171 includes a plurality of first source electrodes 173a that are connected to the first source regions 153a through the contact holes 163a. Each data line 171 includes an extended end region having a large area to be coupled to other layers or an external drive circuit. The data line 171 can be directly connected to the data drive circuit to generate a data signal that can be incorporated onto the substrate 110.
傳送驅動電壓給驅動電晶體Qd之驅動電壓線172實質垂直延伸並穿越閘極線121。每條驅動電壓線172包含數個穿越接觸電洞163b連結至第二源極區153b之第二源極電極173b。該驅動電壓線172可相互連結。The driving voltage line 172 that transmits the driving voltage to the driving transistor Qd extends substantially vertically and passes through the gate line 121. Each of the driving voltage lines 172 includes a plurality of second source electrodes 173b connected to the second source regions 153b via the contact holes 163b. The driving voltage lines 172 can be connected to each other.
第一汲極電極175a與資料線171分離且驅動電壓線172穿越接觸電洞165a連結至第一汲極區155a及穿越接觸電洞164連結至第二閘極電極124b。The first drain electrode 175a is separated from the data line 171 and the driving voltage line 172 is coupled to the first drain region 155a through the contact hole 165a and to the second gate electrode 124b via the contact hole 164.
第二汲極電極175b與資料線171分離且驅動電壓線172穿越接觸電洞165b連結至第二汲極區155b。The second drain electrode 175b is separated from the data line 171 and the driving voltage line 172 is coupled to the second drain region 155b across the contact hole 165b.
一般電壓線278包含配置接近如第3圖所示之基體110其上邊緣的一般電壓觸墊279。該一般電壓線278係可形成於閘極線121所在之層。The general voltage line 278 includes a general voltage contact pad 279 disposed proximate the upper edge of the substrate 110 as shown in FIG. The general voltage line 278 can be formed on the layer where the gate line 121 is located.
資料導體171、172、175a、175b與278係可由包含鉻、鉬、鈦、鉭或其合金之反射金屬製成。它們具備包含低阻抗薄膜及一優良接觸膜之多層結構。多層結構之一例示包含由下層鉻薄膜與上層鋁(合金)薄膜所組成之雙層結構,由下層鉬薄膜與上層鋁(合金)薄膜所組成之雙層結構及由下層鉬薄膜、中層鋁薄膜及上層鉬薄膜所組成之三層結構。The data conductors 171, 172, 175a, 175b and 278 may be made of a reflective metal comprising chromium, molybdenum, titanium, niobium or alloys thereof. They have a multilayer structure comprising a low-resistance film and an excellent contact film. One of the multi-layer structures exemplifies a two-layer structure consisting of a lower chromium film and an upper aluminum (alloy) film, a two-layer structure composed of a lower molybdenum film and an upper aluminum (alloy) film, and a lower molybdenum film and a middle aluminum film. And a three-layer structure composed of an upper molybdenum film.
如閘極導體121與124b,資料導體171、172、175a、175b與278具有對應於基體從30至80度之傾斜角曲線。For the gate conductors 121 and 124b, the data conductors 171, 172, 175a, 175b and 278 have inclination angle curves corresponding to the substrate from 30 to 80 degrees.
一鈍態層180係形成於資料導體171、172、175a、175b與278上。該鈍態層180係可以具優良平坦性質之感光有機材料,以電漿輔助化學氣相沉積法(PECVD)形成之低介電絕緣材料如非晶矽:C:O與非晶矽:O:F或如氮化矽及氧化矽之無機材料所製成。A passivation layer 180 is formed on the data conductors 171, 172, 175a, 175b and 278. The passivation layer 180 is a photosensitive organic material having excellent flat properties, and a low dielectric insulating material such as amorphous germanium formed by plasma assisted chemical vapor deposition (PECVD): C: O and amorphous germanium: O: F or an inorganic material such as tantalum nitride and tantalum oxide.
該鈍態層180具有數個分別接觸第二汲極電極175b與一般電壓線278之接觸電洞185與188。該鈍態層180可進一步包含數個接觸資料線171末端部分之接觸電洞(未顯示),且該鈍態層180與界絕緣層160可具有數個接觸閘極線121末端部分之接觸電洞(未顯示)。當一般電壓線278係配置於界絕緣層160下方,接觸電洞188可穿透界絕緣層160。The passivation layer 180 has a plurality of contact holes 185 and 188 that contact the second drain electrode 175b and the common voltage line 278, respectively. The passivation layer 180 may further include a plurality of contact holes (not shown) contacting the end portions of the data lines 171, and the passivation layer 180 and the boundary insulating layer 160 may have contact currents of the end portions of the plurality of contact gate lines 121. Hole (not shown). When the general voltage line 278 is disposed under the boundary insulating layer 160, the contact hole 188 can penetrate the boundary insulating layer 160.
數個像素電極s190與一接觸輔助88係可形成於鈍態層180上。A plurality of pixel electrodes s190 and a contact assistant 88 may be formed on the passive layer 180.
像素電極190可作為如第2圖中發光要件LD之陽極,且它們可穿越接觸電洞185連結至第二汲極電極175b。像素電極190與接觸輔助88可由透明導體如ITO或IZO所製成。然而,像素電極190可由不透明反射導體如鋁、銀、鈣、鋇、及鎂所製成。The pixel electrode 190 can serve as an anode of the light-emitting element LD as shown in FIG. 2, and they can be coupled to the second drain electrode 175b through the contact hole 185. The pixel electrode 190 and the contact assistant 88 may be made of a transparent conductor such as ITO or IZO. However, the pixel electrode 190 may be made of an opaque reflective conductor such as aluminum, silver, calcium, barium, and magnesium.
接觸輔助88係穿越接觸電洞188連結至一般電壓線278以覆蓋一般電壓線278外露部分。接觸輔助88係可忽視,或超過一個接觸輔助係形成。Contact aid 88 is coupled across contact hole 188 to a common voltage line 278 to cover the exposed portion of general voltage line 278. Contact assist 88 can be ignored, or more than one contact aid can be formed.
數個接觸輔助或連接構件(未顯示)也係可形成於鈍態層180上以致它們係連結至閘極線121、資料線171或一般電壓觸墊279之外露末端部分。A plurality of contact aids or connecting members (not shown) may also be formed on the passive layer 180 such that they are bonded to the exposed end portions of the gate lines 121, the data lines 171, or the general voltage contact pads 279.
一分離有機發光二極體顯示器之像素的分隔物360係形成於鈍態層180與像素電極190上。該分隔物360包圍像素電極190以定義開孔365係由有機發光材料所填滿。分隔物360具有數個接觸接觸輔助88之接觸電洞368,且其由有機或無機絕緣材料製成。A spacer 360 separating the pixels of the organic light emitting diode display is formed on the passive layer 180 and the pixel electrode 190. The spacer 360 surrounds the pixel electrode 190 to define that the opening 365 is filled with the organic luminescent material. The separator 360 has a plurality of contact holes 368 that contact the contact 88 and is made of an organic or inorganic insulating material.
數個發光組件370係形成於像素電極190且配置於由分隔物360定義之開孔365中。該發光組件370可由發紅、綠及藍光之有機材料所製成。該紅、綠及藍發光組件370係規律地配置。A plurality of light emitting components 370 are formed on the pixel electrode 190 and disposed in the opening 365 defined by the spacer 360. The light-emitting assembly 370 can be made of an organic material that emits red, green, and blue light. The red, green, and blue lighting assemblies 370 are regularly configured.
一包含下層電極271的一般電極270及一上層電極272係形成於發光組件370及分隔物360上。該一般電極270係由一般電壓Vcom提供。A general electrode 270 including a lower electrode 271 and an upper electrode 272 are formed on the light-emitting assembly 370 and the spacer 360. The general electrode 270 is provided by a general voltage Vcom.
該下層電極271係可由一絕緣體如氟化鋰或鹼金屬或鹼土金屬如鋇、鈣或鋰所製成,而上層電極272係可由低阻抗金屬如鋁、銀或其合金所製成。接觸至發光組件370之下層電極271可具有低功函數以致下層電極271促使電子注入至發光組件370。該上層電極272可由對氧化阻抗之低阻抗材料所製成以致上層電極272保護下層電極271且降低一般電壓Vcom失真。The lower layer electrode 271 may be made of an insulator such as lithium fluoride or an alkali metal or alkaline earth metal such as barium, calcium or lithium, and the upper layer electrode 272 may be made of a low-resistance metal such as aluminum, silver or an alloy thereof. Contacting the lower layer electrode 271 to the light emitting assembly 370 can have a low work function such that the lower layer electrode 271 causes electrons to be injected into the light emitting assembly 370. The upper layer electrode 272 may be made of a low-impedance material that is oxidized so that the upper layer electrode 272 protects the lower layer electrode 271 and reduces the normal voltage Vcom distortion.
如第3圖與第4圖所示,上層電極272包含一穿越接觸電洞368而接觸至接觸輔助88之接觸部分B,且下層電極271並不接觸接觸輔助88。此結構降低一般電極270與接觸輔助88或一般電壓線278間之接觸電阻。詳細而言,具有低功函數如鋇或鈣之金屬可輕易地因一點點熱量而熔化如接觸部分B所生成之現象,因而提高接觸電阻。此外,一絕緣體如氟化鋰也會提高接觸電阻。隨著上述結構,上層電極272接觸了接觸輔助88但下層電極271沒有。因此,介於一般電極270與一般電壓線278間之接觸電阻係可降低。As shown in FIGS. 3 and 4, the upper electrode 272 includes a contact portion B that contacts the contact hole 88 through the contact hole 368, and the lower electrode 271 does not contact the contact assistant 88. This structure reduces the contact resistance between the general electrode 270 and the contact assistant 88 or the general voltage line 278. In detail, a metal having a low work function such as barium or calcium can be easily melted by a little heat, such as a phenomenon generated by the contact portion B, thereby increasing the contact resistance. In addition, an insulator such as lithium fluoride also increases the contact resistance. With the above structure, the upper layer electrode 272 is in contact with the contact assistant 88 but the lower layer electrode 271 is not. Therefore, the contact resistance between the general electrode 270 and the normal voltage line 278 can be reduced.
在上述之有機發光二極體顯示器中,一切換電晶體Qs包括一第一半導體島151a、一連結至閘極線121之第一閘極電極124a、一連結至資料線171之第一源極電極173a及一第一汲極電極175a。此外,一驅動電晶體包含第二半導體島151b、一連結至第一汲極電極175a之第二閘極電極124b及一連結至像素電極190之第二汲極電極175b。並且,一連結至第二源極區153b之儲存電極區157與一連結至第二閘極電極124b之儲存電極127形成一儲存電容Cst。顯示於第5圖至第7圖之例示電晶體Qs與Qd因閘極電極124a與124b係配置於半導體151a與151b上而係作為“上閘極電晶體”。In the above organic light emitting diode display, a switching transistor Qs includes a first semiconductor island 151a, a first gate electrode 124a connected to the gate line 121, and a first source connected to the data line 171. The electrode 173a and a first drain electrode 175a. In addition, a driving transistor includes a second semiconductor island 151b, a second gate electrode 124b connected to the first drain electrode 175a, and a second drain electrode 175b connected to the pixel electrode 190. Moreover, a storage electrode region 157 connected to the second source region 153b and a storage electrode 127 connected to the second gate electrode 124b form a storage capacitor Cst. The transistors Qs and Qd shown in Figs. 5 to 7 are referred to as "upper gate transistors" because the gate electrodes 124a and 124b are disposed on the semiconductors 151a and 151b.
有機發光組件370可具有如第8圖所示之多層結構。該有機發光組件370包含至少一發光層EML,且進一步包含輔助層以提升發光層EML其發光效率。輔助層可包含提升電子與電洞平衡之電子傳輸層ETL與電洞傳輸層HTL,及提升電子與電洞注入之電子注入層EIL與電洞注入層HIL。一般電極270之下層電極271可作為電子注入層EIL。The organic light emitting device 370 may have a multilayer structure as shown in FIG. The organic light emitting device 370 includes at least one light emitting layer EML, and further includes an auxiliary layer to enhance the light emitting efficiency of the light emitting layer EML. The auxiliary layer may include an electron transport layer ETL and a hole transport layer HTL for enhancing electron and hole balance, and an electron injection layer EIL and a hole injection layer HIL for enhancing electron and hole injection. The electrode 271 under the electrode 270 can be used as the electron injection layer EIL.
現在,一種顯示於第3圖至第8圖之製造顯示器面板技術係參照第9圖至第27C圖而敘述。Now, a manufacturing display panel technology shown in Figs. 3 to 8 will be described with reference to Figs. 9 to 27C.
第9圖、第11圖、第13圖、第15圖、第17圖、第19圖、第21圖、第23圖與第25圖根據本發明實施例為第3圖至第8圖中所示之顯示器面板在製程中間步驟之佈局圖。第10A圖與第10B圖分別為沿第9圖中顯示器面板其線段XA-XA’與XB-XB’之截面圖,而第10C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。第12A圖與第12B圖分別為沿第11圖中顯示器面板其線段XIIA-XIIA’與XIIB-XIIB’之截面圖,而第12C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。第14A圖與第14B圖分別為沿第13圖中顯示器面板其線段XIVA-XIVA’與XIVB-XIVB’之截面圖,而第14C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。第16A圖與第16B圖分別為沿第15圖中顯示器面板其線段XVIA-XVIA’與XVIB-XVIB’之截面圖,而第16C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。第18A圖與第18B圖分別為沿第17圖中顯示器面板其線段XVIIIA-XVIIIA’與XVIIIB-XVIIIB’之截面圖,而第18C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。第20A圖與第20B圖分別為沿第19圖中顯示器面板其線段XXA-XXA’與XXB-XXB’之截面圖,而第20C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。第22A圖與第22B圖分別為沿第21圖中顯示器面板其線段XXIIA-XXIIA’與XXIIB-XXIIB’之截面圖,而第22C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。第24A圖與第24B圖分別為沿第23圖中顯示器面板其線段XXIVA-XXIVA’與XXIVB-XXIVB’之截面圖,而第24C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。第26A圖與第26B圖分別為沿第25圖中顯示器面板其線段XXVIA-XXVIA’與XXVIB-XXVIB’之截面圖,而第26C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。第27A圖與第27B圖分別為沿第25圖中顯示器面板其線段XXVIA-XXVIA’與XXVIB-XXVIB’之截面圖,並說明第26A圖與第26B圖中所示步驟之下一步驟,而第27C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。Fig. 9, Fig. 11, Fig. 13, Fig. 15, Fig. 17, Fig. 19, Fig. 21, Fig. 23 and Fig. 25 are diagrams of Figs. 3 to 8 according to an embodiment of the present invention. The layout of the display panel in the middle of the process. 10A and 10B are cross-sectional views of the line segments XA-XA' and XB-XB' of the display panel of FIG. 9, respectively, and FIG. 10C is the line segment IV-IV' of the display panel of FIG. 3 A cross-sectional view of the steps. 12A and 12B are cross-sectional views of the line segments XIIA-XIIA' and XIIB-XIIB' of the display panel of Fig. 11, respectively, and Fig. 12C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps. 14A and 14B are cross-sectional views of the line segments XIVA-XIVA' and XIVB-XIVB' of the display panel of Fig. 13, respectively, and Fig. 14C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps. 16A and 16B are cross-sectional views of the line segments XVIA-XVIA' and XVIB-XVIB' of the display panel of Fig. 15, respectively, and Fig. 16C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps. 18A and 18B are cross-sectional views of the line segments XVIIIA-XVIIIA' and XVIIIB-XVIIIB' of the display panel of Fig. 17, respectively, and Fig. 18C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps. 20A and 20B are cross-sectional views of the line segments XXA-XXA' and XXB-XXB' of the display panel of Fig. 19, respectively, and Fig. 20C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps. 22A and 22B are cross-sectional views of the line segments XXIIA-XXIIA' and XXIIB-XXIIB' of the display panel of Fig. 21, respectively, and Fig. 22C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps. Figure 24A and Figure 24B are cross-sectional views of the line segments XXIVA-XXIVA' and XXIVB-XXIVB' of the display panel of Figure 23, respectively, and Figure 24C is the line segment IV-IV' of the display panel of Figure 3 A cross-sectional view of the steps. Figure 26A and Figure 26B are cross-sectional views of the line segments XXVIA-XXVIA' and XXVIB-XXVIB' of the display panel of Figure 25, respectively, and Figure 26C is the line segment IV-IV' of the display panel of Figure 3 A cross-sectional view of the steps. Figure 27A and Figure 27B are cross-sectional views of the line segments XXVIA-XXVIA' and XXVIB-XXVIB' along the display panel of Figure 25, respectively, and illustrate the steps below the steps shown in Figures 26A and 26B, and Figure 27C is a cross-sectional view of the display panel of Figure 3 taken along line IV-IV' at this step.
參考第9圖至第10C圖,一阻隔層111係形成於一絕緣基體110上,且以非晶矽製成之一半導體層可以低壓化學氣相沉積法(LPCVD)、電漿輔助化學氣相沉積法(PECVD)或濺鍍法沉積於阻隔層111上。Referring to FIGS. 9 to 10C, a barrier layer 111 is formed on an insulating substrate 110, and a semiconductor layer made of amorphous germanium can be subjected to low pressure chemical vapor deposition (LPCVD) or plasma assisted chemical vapor phase. A deposition method (PECVD) or sputtering is deposited on the barrier layer 111.
接著,該半導體層可結晶成多晶矽並光蝕刻成數對第一與第二半導體島151a與151b。亦或,半導體層可以非晶矽層移除。Next, the semiconductor layer may be crystallized into polysilicon and photoetched into pairs of first and second semiconductor islands 151a and 151b. Alternatively, the semiconductor layer can be removed by an amorphous layer.
參考第11圖至第12C圖,一閘極絕緣層140與一閘極金屬層實質沉積於包含第一與第二半導體島151a與151b之基體上,且一第一光阻PR1形成於上。該閘極金屬層藉由使用第一光阻PR1為蝕刻光罩係蝕刻成數個包含儲存電極127與數個閘極金屬構件120a之閘極電極124b。一P-型雜質係導入至與第一光阻PR1一樣不受閘極電極124b與閘極金屬構件120a覆蓋之第二半導體島151b部分內,以形成數個P-型非本質區153b與155b。此時,第一半導體島151a係以第一光阻PR1與閘極金屬構件120a覆蓋並避免雜質摻入。Referring to FIGS. 11 to 12C, a gate insulating layer 140 and a gate metal layer are substantially deposited on the substrate including the first and second semiconductor islands 151a and 151b, and a first photoresist PR1 is formed thereon. The gate metal layer is etched into a plurality of gate electrodes 124b including the storage electrode 127 and the plurality of gate metal members 120a by etching the mask using the first photoresist PR1. A P-type impurity is introduced into the portion of the second semiconductor island 151b which is not covered by the gate electrode 124b and the gate metal member 120a like the first photoresist PR1 to form a plurality of P-type non-essential regions 153b and 155b. . At this time, the first semiconductor island 151a is covered with the first photoresist PR1 and the gate metal member 120a to avoid impurity incorporation.
參考第13圖至第14C圖,第一光阻PR1係移除且第二光阻PR2係形成。該閘極金屬構件120a藉由使用第二光阻PR2為蝕刻光罩係蝕刻成數條包含閘極電極124a之閘極線121。一N-型雜質係注入至與第二光阻PR2一樣不受閘極線121與閘極電極124b覆蓋之第一半導體島151a部分內,以形成數個N-型非本質區153a與155a。此時,第二半導體島151b係以第二光阻PR2覆蓋並避免雜質摻入。Referring to FIGS. 13 to 14C, the first photoresist PR1 is removed and the second photoresist PR2 is formed. The gate metal member 120a is etched into a plurality of gate lines 121 including the gate electrodes 124a by etching the mask using the second photoresist PR2. An N-type impurity is implanted into the portion of the first semiconductor island 151a which is not covered by the gate line 121 and the gate electrode 124b like the second photoresist PR2 to form a plurality of N-type non-essential regions 153a and 155a. At this time, the second semiconductor island 151b is covered with the second photoresist PR2 and impurity incorporation is prevented.
參考第15圖至第16C圖,一界絕緣薄膜160係沉積且該界絕緣薄膜160與閘極絕緣層140係光蝕刻以形成與數個接觸閘極電極124b之接觸電洞164一樣之數個分別接觸非本質區153a、153b、155a與155b的接觸電洞163a、163b、165a與165b。Referring to FIGS. 15 to 16C, an interlayer insulating film 160 is deposited and the boundary insulating film 160 and the gate insulating layer 140 are photoetched to form the same number of contact holes 164 as the plurality of contact gate electrodes 124b. The contact holes 163a, 163b, 165a, and 165b of the non-essential regions 153a, 153b, 155a, and 155b are respectively contacted.
參考第17圖至第18C圖,數個包含數條資料線171,數個驅動電壓線172之資料導體,資料線171另包含第一源極電極173a而數個驅動電壓線172另包含第二源極電極173b,數個第一與第二汲極電極175a與175b及一般電壓線278,係形成於界絕緣層160上。Referring to FIGS. 17 to 18C, a plurality of data conductors including a plurality of data lines 171 and a plurality of driving voltage lines 172, the data line 171 further includes a first source electrode 173a and a plurality of driving voltage lines 172 further include a second The source electrode 173b, the plurality of first and second drain electrodes 175a and 175b, and the general voltage line 278 are formed on the boundary insulating layer 160.
參考第19圖至第20C圖,一鈍態層180係沉積且光蝕刻以形成數個分別接觸第二汲極電極175b與一般電壓線278之接觸電洞185與188。Referring to Figures 19 through 20C, a passivation layer 180 is deposited and photoetched to form a plurality of contact holes 185 and 188 that contact the second drain electrode 175b and the common voltage line 278, respectively.
參考第21圖至第22C圖,數個像素電極190與一接觸輔助88係形成於鈍態層180上。當像素電極190以反射不透明材料製成時,它們係沿資料線171形成為資料金屬層。Referring to FIGS. 21 to 22C, a plurality of pixel electrodes 190 and a contact assistant 88 are formed on the passive layer 180. When the pixel electrodes 190 are made of a reflective opaque material, they are formed as a data metal layer along the data line 171.
參考第23圖至第24C圖,一絕緣層係沉積且圖像化以形成一在像素電極190上有開孔365與在接觸輔助88上至少有一接觸電洞368之一分隔物360。Referring to Figures 23 through 24C, an insulating layer is deposited and imaged to form an opening 360 in the pixel electrode 190 and at least one contact hole 368 in the contact auxiliary 88.
參考第25圖至第26C圖,數個包含至少一發光層且可進一步具有多層之有機發光組件370係形成於利用沉積法或網印法所形成之光罩而產生的開孔365中。Referring to Figures 25 to 26C, a plurality of organic light-emitting components 370 comprising at least one light-emitting layer and further having a plurality of layers are formed in openings 365 which are formed by a photomask formed by deposition or screen printing.
參考第27A圖至第27C圖,一下層電極271利用光罩等係形成以致該下層電極271並未配置於接觸電洞368上。Referring to FIGS. 27A to 27C, the lower layer electrode 271 is formed by a photomask or the like so that the lower layer electrode 271 is not disposed on the contact hole 368.
一具有配置於接觸電洞368上之接觸部分B的上層電極272係如第3圖、第4圖、第6圖與第7圖所示形成於下層電極271上。儘管未顯示,OLED元件可以密封薄膜或一金屬封蓋密封。An upper electrode 272 having a contact portion B disposed on the contact hole 368 is formed on the lower electrode 271 as shown in Figs. 3, 4, 6, and 7. Although not shown, the OLED element can be sealed with a sealing film or a metal closure.
對熟知技藝者很明顯的本發明中不同修正與改變在不違背本發明精神或範圍下可進行。因此可了解本發明涵蓋隨申請專利範圍及同義之修正與改變。It is apparent to those skilled in the art that various modifications and changes can be made without departing from the spirit and scope of the invention. It is therefore to be understood that the invention is intended to cover the modifications and modifications
88...接觸輔助88. . . Contact assistance
110...基體110. . . Matrix
111...阻隔層111. . . Barrier layer
121...閘極線121. . . Gate line
124a...閘極電極124a. . . Gate electrode
124b...閘極電極124b. . . Gate electrode
127...儲存電極127. . . Storage electrode
140...閘極絕緣層140. . . Gate insulation
151a...半導體151a. . . semiconductor
151b...半導體151b. . . semiconductor
153a...源極區153a. . . Source area
153b...源極區153b. . . Source area
155a...汲極區155a. . . Bungee area
155b...汲極區155b. . . Bungee area
157...儲存區域157. . . Storage area
160...界絕緣薄膜160. . . Boundary insulating film
163a...接觸電洞163a. . . Contact hole
163b...接觸電洞163b. . . Contact hole
164...接觸電洞164. . . Contact hole
165a...接觸電洞165a. . . Contact hole
165b...接觸電洞165b. . . Contact hole
171...資料線171. . . Data line
172...驅動電壓線172. . . Drive voltage line
173a...源極電極173a. . . Source electrode
173b...源極電極173b. . . Source electrode
175a...汲極電極175a. . . Bipolar electrode
175b...汲極電極175b. . . Bipolar electrode
180...鈍態層180. . . Passive layer
185...接觸電洞185. . . Contact hole
188...接觸電洞188. . . Contact hole
190...像素電極190. . . Pixel electrode
270...一般電極270. . . General electrode
271...一般電極271. . . General electrode
272...一般電極272. . . General electrode
278...一般電壓線278. . . General voltage line
279...一般電壓線279. . . General voltage line
360...分隔物360. . . Separator
368...接觸電洞368. . . Contact hole
370...發光層370. . . Luminous layer
400...掃描驅動器400. . . Scan drive
500...資料驅動器500. . . Data driver
Cst...儲存電容Cst. . . Storage capacitor
PR1...光阻PR1. . . Photoresist
PR2...光阻PR2. . . Photoresist
PR3...光阻PR3. . . Photoresist
PR4...光阻PR4. . . Photoresist
Qs...切換電晶體Qs. . . Switching transistor
Qd...驅動電晶體Qd. . . Drive transistor
第1圖根據本發明實施例為一有機發光二極體顯示器其方塊圖。1 is a block diagram of an organic light emitting diode display in accordance with an embodiment of the present invention.
第2圖根據本發明實施例為一有機發光二極體顯示器中一像素之等效電路圖。2 is an equivalent circuit diagram of a pixel in an organic light emitting diode display according to an embodiment of the invention.
第3圖根據本發明實施例為一有機發光二極體顯示器其顯示器面板的結構平面圖。3 is a plan view showing the structure of a display panel of an organic light emitting diode display according to an embodiment of the present invention.
第4圖為沿第3圖中顯示器面板其線段IV-IV’之截面圖。Figure 4 is a cross-sectional view taken along line IV-IV' of the display panel of Figure 3.
第5圖為第3圖中顯示器面板上像素與訊號線之佈局圖。Figure 5 is a layout diagram of the pixels and signal lines on the display panel in Figure 3.
第6圖與第7圖分別為沿第5圖中像素與訊號線其線段VI-VI’與VII-VII’之截面圖。Fig. 6 and Fig. 7 are cross-sectional views of the line segments VI-VI' and VII-VII' taken along the pixel and signal lines in Fig. 5, respectively.
第8圖根據本發明實施例為一有機發光要件之結構圖。Figure 8 is a structural view of an organic light-emitting element according to an embodiment of the present invention.
第9圖、第11圖、第13圖、第15圖、第17圖、第19圖、第21圖、第23圖與第25圖根據本發明實施例為第3圖、第4圖、第5圖、第6圖與第7圖中所示之顯示器面板在製程中間步驟之佈局圖。Fig. 9, Fig. 11, Fig. 13, Fig. 15, Fig. 17, Fig. 19, Fig. 21, Fig. 23 and Fig. 25 are diagrams 3, 4, and 4 according to an embodiment of the present invention. The layout of the display panel shown in Figure 5, Figure 6, and Figure 7 in the middle of the process.
第10A圖與第10B圖分別為沿第9圖中顯示器面板其線段XA-XA’與XB-XB’之截面圖,而第10C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。10A and 10B are cross-sectional views of the line segments XA-XA' and XB-XB' of the display panel of FIG. 9, respectively, and FIG. 10C is the line segment IV-IV' of the display panel of FIG. 3 A cross-sectional view of the steps.
第12A圖與第12B圖分別為沿第11圖中顯示器面板其線段XIIA-XIIA’與XIIB-XIIB’之截面圖,而第12C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。12A and 12B are cross-sectional views of the line segments XIIA-XIIA' and XIIB-XIIB' of the display panel of Fig. 11, respectively, and Fig. 12C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第14A圖與第14B圖分別為沿第13圖中顯示器面板其線段XIVA-XIVA’與XIVB-XIVB’之截面圖,而第14C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。14A and 14B are cross-sectional views of the line segments XIVA-XIVA' and XIVB-XIVB' of the display panel of Fig. 13, respectively, and Fig. 14C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第16A圖與第16B圖分別為沿第15圖中顯示器面板其線段XVIA-XVIA’與XVIB-XVIB’之截面圖,而第16C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。16A and 16B are cross-sectional views of the line segments XVIA-XVIA' and XVIB-XVIB' of the display panel of Fig. 15, respectively, and Fig. 16C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第18A圖與第18B圖分別為沿第17圖中顯示器面板其線段XVIIIA-XVIIIA’與XVIIIB-XVIIIB’之截面圖,而第18C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。18A and 18B are cross-sectional views of the line segments XVIIIA-XVIIIA' and XVIIIB-XVIIIB' of the display panel of Fig. 17, respectively, and Fig. 18C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第20A圖與第20B圖分別為沿第19圖中顯示器面板其線段XXA-XXA’與XXB-XXB’之截面圖,而第20C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。20A and 20B are cross-sectional views of the line segments XXA-XXA' and XXB-XXB' of the display panel of Fig. 19, respectively, and Fig. 20C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第22A圖與第22B圖分別為沿第21圖中顯示器面板其線段XXIIA-XXIIA’與XXIIB-XXIIB’之截面圖,而第22C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。22A and 22B are cross-sectional views of the line segments XXIIA-XXIIA' and XXIIB-XXIIB' of the display panel of Fig. 21, respectively, and Fig. 22C is the line segment IV-IV' of the display panel of Fig. 3 A cross-sectional view of the steps.
第24A圖與第24B圖分別為沿第23圖中顯示器面板其線段XXIVA-XXIVA’與XXIVB-XXIVB’之截面圖,而第24C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。Figure 24A and Figure 24B are cross-sectional views of the line segments XXIVA-XXIVA' and XXIVB-XXIVB' of the display panel of Figure 23, respectively, and Figure 24C is the line segment IV-IV' of the display panel of Figure 3 A cross-sectional view of the steps.
第26A圖與第26B圖分別為沿第25圖中顯示器面板其線段XXVIA-XXVIA’與XXVIB-XXVIB’之截面圖,而第26C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。Figure 26A and Figure 26B are cross-sectional views of the line segments XXVIA-XXVIA' and XXVIB-XXVIB' of the display panel of Figure 25, respectively, and Figure 26C is the line segment IV-IV' of the display panel of Figure 3 A cross-sectional view of the steps.
第27A圖與第27B圖分別為沿第25圖中顯示器面板其線段XXVIA-XXVIA’與XXVIB-XXVIB’之截面圖,並說明第26A圖與第26B圖中所示步驟之下一步驟,而第27C圖為第3圖中顯示器面板其線段IV-IV’在此步驟時之截面圖。Figure 27A and Figure 27B are cross-sectional views of the line segments XXVIA-XXVIA' and XXVIB-XXVIB' along the display panel of Figure 25, respectively, and illustrate the steps below the steps shown in Figures 26A and 26B, and Figure 27C is a cross-sectional view of the display panel of Figure 3 taken along line IV-IV' at this step.
88...接觸輔助88. . . Contact assistance
110...基體110. . . Matrix
111...阻隔層111. . . Barrier layer
140...閘極絕緣層140. . . Gate insulation
160...界絕緣薄膜160. . . Boundary insulating film
180...鈍態層180. . . Passive layer
188...接觸電洞188. . . Contact hole
270...一般電棒270. . . General electric bar
271...一般電極271. . . General electrode
272...一般電極272. . . General electrode
278...一般電壓線278. . . General voltage line
360...分隔物360. . . Separator
368...接觸電洞368. . . Contact hole
Claims (15)
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US7414362B2 (en) | 2008-08-19 |
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US20060001366A1 (en) | 2006-01-05 |
US20080258618A1 (en) | 2008-10-23 |
CN1735302B (en) | 2010-05-05 |
TW200614134A (en) | 2006-05-01 |
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