KR100437656B1 - Organic Electroluminescent Device Having Shorting Bar for Aging and Panel Test - Google Patents

Abstract

The present invention relates to a test wiring of an organic EL device, wherein an anode layer formed on a transparent substrate includes a plurality of low pads having a predetermined length connected to each of a plurality of scan lines of the organic EL device, and the organic EL device. A plurality of column pads having a predetermined length respectively connected to a plurality of signal lines of the device, one row probing pad electrically connected to the plurality of low pads, and electrically connected to the column pads And a single column probing pad, wherein the insulating layer is formed to have a contact hole in the terminal of the row pad and the column pad, and is orthogonal to the row pad and the column pad on the insulating layer and does not cover the contact hole. A plurality of barrier ribs having a predetermined thickness and thickness, the barrier ribs, an insulation layer and contact holes between the barrier ribs and the barrier ribs, and the furnace The terminal of the right proving pad and the column proving pad is covered with a cathode layer formed with a thickness thinner than that of the partition wall to provide a test wiring structure suitable for an organic EL device that does not require a photolithography process.

Description

Organic EL device having test wirings {Organic Electroluminescent Device Having Shorting Bar for Aging and Panel Test}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic EL device, and more particularly, to a structure of test wirings capable of aging and panel testing in an entire substrate state before a scribe process.

1 is a configuration of a shorting bar of a conventional TFT-LCD panel.

In the conventional TFT-LCD panel, the shorting bar is patterned at the same time when forming the TFT array. A plurality of data lines (Odd line) 3-1 and data even lines (3-2) are sequentially formed in a plurality of data lines of a TFT array having a lattice structure. A data odd pad 1-1 and a data even pad 1-2 are respectively connected to the data odd line 3-1 and the data even line 3-2. do. The other side of the plurality of data odd pads 1-1 are all connected to the data odd shorting bar 5-1 formed in one line, and the other side of the plurality of data even pads 1-2 is one. Are all connected to a data even shorting bar 5-2 formed as a line of. At the ends of the data odd shorting bar 5-1 and the data even shorting bar 5-2, a data odd proofing pad 7-1 and a data even proofing pad 7-2 are formed.

A gate odd line 4-1 and a gate even line 4-2 are sequentially connected to a plurality of gate lines of the TFT array having a lattice structure, and the gate odd lines 4-1 are sequentially connected. ) And gate even line 4-2 are connected to gate odd pad 2-1 and gate even pad 2-2, respectively. The other sides of the plurality of gate odd pads 2-1 are all connected to the gate odd shorting bars 6-1 formed in one line, and the other side of the plurality of gate even pads 2-2 is one. It is connected to both gate even shorting bars 6-2 formed by lines of. The gate odd proving pad 8-1 and the gate even proving pad 8-2 are formed at the ends of the gate odd shorting bar 6-1 and the gate even shorting bar 6-2.

The shorting bar of the above-described conventional TFT-LCD panel is formed by a photolithography method. The current state requires the data odd shorting bar (5-1), data even shorting bar (5-2), gate odd shorting bar (6-1) and gate even shorting bar (6-2) only when testing the TFT array. And since it is not necessary in the actual product, it is formed into a dummy part and then cut and removed after the test.

However, in the organic EL device, the organic material layer formed after the anode layer is very vulnerable to moisture, so that a photolithography process cannot be used. In order to test, at least two conductive films should be formed to connect the anode layer and the cathode layer in order to distribute the desired signal to each line, but the cathode layer is formed by the organic material layer and then proceeds to the deposition process using a shadow mask. It is not possible to proceed with the photolithography process, which is a method of forming bars.

Due to the above-described problems, the organic EL device does not include a shorting bar, and therefore, aging and lighting tests for testing its reliability are generally performed after scribing and breaking & breaking processes. In other words, aging and lighting tests were performed in a panel or cell state.

In the aging and lighting inspection of the conventional organic EL device, after the scribing and breaking process is completed, the lighting state is checked by applying voltage and current to the products in the panel state by using all short jig, etc. The same jig is also attached to the aging pallet for aging for a long time. In other words, the reliability test is performed in each panel and cell state that is cut.

However, when the panel is small in size and a large number of panels are produced in one disc, it is difficult to estimate the processing capacity of the aging process and the lighting inspection process. The additional arrangement causes the production cost to rise, and if the production model is changed, an idle facility is generated.

Therefore, the present invention does not require any special equipment for the aging process and the lighting inspection process, and provides a test wiring for constructing a shorting bar without the need for a photolithography process for the organic EL device.

In order to achieve the above object, the test wiring of the organic EL device according to the present invention has an anode layer formed on a transparent substrate, and the anode layer is connected to a plurality of scan lines of the organic EL device, respectively, to have a constant length. A plurality of row pads, a plurality of column pads each having a predetermined length connected to a plurality of signal lines of the organic EL element, and one row probing electrically connected to the plurality of row pads. A pad and a column probing pad electrically connected to the column pad, an insulating layer formed to have contact holes in the terminal of the row pad and the column pad, and the row pad and the column on the insulating layer. A plurality of barrier ribs orthogonal to the pad and formed at a predetermined interval and thickness without covering the contact hole; The cathode layer includes a cathode layer formed on the insulating layer and the contact hole between the walls and the terminal portion of the row probing pad and the column probing pad and having a thickness thinner than that of the partition wall. The pad and the column pad are electrically connected to the low probing pad and the column probing pad, respectively.

1 is a configuration of a shorting bar of a conventional TFT-LCD panel

2 is a plan view of a test wiring according to a first embodiment (monochrome) of the present invention;

3A and 3B are cross-sectional views illustrating A-A 'and B-B' of FIG. 2;

4 is a plan view of a test wiring according to a second embodiment (full-color) of the present invention;

5A and 5B are cross-sectional views illustrating A-A 'and B-B' of FIG. 5;

6 is a plan view of a test wiring according to a third embodiment (monochrome) of the present invention;

7A and 7B are cross-sectional views illustrating A-A 'and B-B' of FIG. 5;

8 is a plan view of a test wiring according to the fourth embodiment (full-color) of the present invention.

9A and 9B are cross-sectional views illustrating A-A 'and B-B' of FIG. 8.

<Description of Reference Numbers for Main Parts of Drawings>

1-1: Data odd pad 1-2: Data even pad

2-1: gate odd pad 2-2: gate even pad

3-1: Data Order Line 3-2: Data Even Line

4-1: Gate odd line 4-2: Gate even line

5-1: Data odd shorting bar 5-2: Data even shorting bar

6-1: Gate Eod Shorting Bar 6-2: Gate Even Shorting Bar

7-1: Data Even Proving Pad 7-2: Data Even Proving Pad

8-1: Gate Eid Proving Pad 8-2: Gate Even Proving Pad

11: Low pad 11-1: Eau low pad

11-2: Even row pad 12: Column pad

12-1: Red Pad 12-2: Green Pad

12-3: Blue Pad 12-4: Aether Column Pad

12-5: Even column pad 13: Low shorting bar

13-1: Aude Low Shorting Bar 13-2: Even Low Shorting Bar

14: column shorting bar 14-1: red shorting bar

14-2: Green Shorting Bar 14-3: Blue Shorting Bar

14-4: Aude Column Shorting Bar 14-5: Even Column Shorting Bar

15: Low Probing Pad 15-1: Eau De Probing Pad

15-2: Even low probe pad 16: Column probe pad

16-1: red proofing pad 16-2: green proofing pad

16-3: blue proofing pad 16-4: aude column proofing pad

16-5: Even column probe pad 21: Anode layer

22: insulating layer 23: partition

24: cathode layer 25: transparent substrate

31: contact hole 41: cutting line

42: organic EL panel portion 43: test dummy portion

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]

2 is a plan view of a test wiring according to the first embodiment (monochrome) of the present invention, and FIGS. 3A and 3B are sectional views showing A-A 'and B-B' of FIG.

The first embodiment is applied to a mono color organic electroluminescent display device.

In the test wiring of the organic EL device according to the first embodiment of the present invention, the anode layer 21 is formed of ITO on the transparent substrate 25. At this time, the anode layer 21 is formed to have a pattern as follows. Row pads 11 connected to a plurality of scan lines of an organic EL element (hereinafter, OELD) are formed to have the same length, and column pads are respectively connected to a plurality of signal lines of the OELD. 12 is formed to have a length different from that of the low pad 11, and a row proving pad 15 to be electrically connected to the low pad 11 is formed at one side and electrically connected to the column pad 12. The column probe pad 16 is formed.

An insulating layer 22 is formed on the row pad 11 and the column pad 12, wherein the insulating layer 22 has a contact hole 31 in each of the row pad 11 and the column pad 12. ) Is patterned.

On the insulating layer 22, a partition wall 23 having a predetermined thickness orthogonal to the row pad 11 and the column pad 12 and covering the contact hole 31 is formed to have a predetermined thickness (2 to 10 μm).

On the partition 23, the insulating layer 22 between the partition 23 and the partition 23 and the contact hole 31, the terminals of the low probing pad 15 and the column probing pad 16. The cathode layer 24 is patterned to cover the additional portion. At this time, the cathode layer 24 is formed to have a significantly thinner thickness than the partition wall (23).

In FIG. 3A, the patterned cathode layer 24 is electrically connected to the row pad 11 and the column pad 12 of the anode layer 21 through the contact hole 31 of the insulating layer 22. In addition, since the insulating layer 22 is not formed on the low probing pad 15 and the column probing pad 16, it is directly connected to the negative electrode layer 24 at one side. Therefore, the cathode layer 24 formed serves as the row shorting bar 13 and the column shorting bar 14.

In FIG. 3B, the row shorting bar 13 and the column shorting bar 14 are electrically separated by the partition 23.

The test panel of the OELD formed as described above may apply the appropriate signal for operating the OELD panel to the low probing pad 15 and the column probing pad 16 through a probe to perform a lighting test and an aging process.

After the test process as described above is cut along the cutting line 41 is divided into the OELD panel 42 and the test panel 43 is separated from the test panel 43 in the actual product.

Second Embodiment

4 is a plan view of a test wiring according to a second embodiment (full-color) of the present invention, and FIGS. 5A and 5B are cross-sectional views illustrating A-A 'and B-B' of FIG. 4.

The second embodiment is a case where it is applied to a full color OELD.

In the test wiring of the OELD according to the second embodiment of the present invention, the anode layer 21 is formed of ITO on the transparent substrate 25. At this time, the anode layer 21 is formed to have a pattern as follows. The row pads 11 connected to each of the plurality of scan line waves of the OELD are formed to have the same length, and the red pads respectively connected to the plurality of signal lines representing respective colors of the OELD ( 12-1, the green pad 12-2 and the blue pad 12-3 are formed to have different lengths from the low pad 11, and the low probing pad to be electrically connected to the low pad 11. 15) is formed on one side,

A red probing pad 16-1 to be electrically connected to the red pad 12-1, a green probing pad 16-2 and a blue pad 12-3 to be electrically connected to the green pad 12-2; A blue proving pad 16-3 to be electrically connected is formed.

An insulating layer 22 is formed on the low pad 11, the red pad 12-1, the green pad 12-2, and the blue pad 12-3, wherein the low pad 11 and the red pad are respectively formed. The insulating layer 22 is patterned to have contact holes 31 in the terminals 12-1, the green pads 12-2, and the blue pads 12-3.

The insulating layer 22 is orthogonal to the low pad 11, the red pad 12-1, the green pad 12-2, and the blue pad 12-3, and has a predetermined interval without covering the contact hole 31. The partition 23 is formed to have a constant thickness (2 to 10 µm).

On the barrier 23, on the insulating layer 22 between the barrier 23 and the barrier 23 and the contact hole 31, the low proving pad 15 and the red proving pad 16-1. The cathode layer 24 is patterned to cover the terminal portions of the green probing pad 16-2 and the blue probing pad 16-3. At this time, the cathode layer 24 is formed to have a significantly thinner thickness than the partition wall (23).

In FIG. 5A, the cathode layer 24 to be patterned is connected to the low pad 11, the red pad 12-1, and the green pad 12-of the anode layer 21 through the contact holes 31 of the insulating layer 22. 2) and the blue pad 12-3. In addition, the insulating layer 22 is not formed on the low probing pad 15, the red probing pad 16-1, the green probing pad 16-2, and the blue probing pad 16-3. It is electrically connected to the cathode layer 24 directly at the side. Therefore, the cathode layer 24 formed serves as a low shorting bar 13, a red shorting bar 14-1, a green shorting bar 14-2, and a blue shorting bar 14-3.

In FIG. 5B, the row shorting bar 13, the red shorting bar 14-1, the green shorting bar 14-2, and the blue shorting bar 14-3 are electrically separated by the partition 23. .

Since the test procedure is similar to Example 1, the description thereof is omitted.

Third Embodiment

FIG. 6 is a plan view of a test wiring according to a third embodiment (monochrome) of the present invention, and FIGS. 7A and 7B are sectional views showing A-A 'and B-B' of FIG.

The third embodiment is a case where the mono color OELD is applied.

In the test wiring of the OELD according to the third embodiment of the present invention, the anode layer 21 is formed of ITO on the transparent substrate 25. At this time, the anode layer 21 is formed to have a pattern as follows. The odd low pads 11-1 and the even low pads 11-2 are formed to have different lengths and are divided into odd-numbered and even-numbered scan lines of the OELD, respectively. The odd column pads 12-4 and the even column pads 12-5, which are divided into odd-numbered and even-numbered lines of the two signal lines, are formed to have different lengths, and the odd row pads 11-1. ) Is electrically connected to the odd row proving pad 15-1 to be electrically connected to the even row proving pad 15-2 and the odd column pad 12-1 to be electrically connected to the even row pad 11-2. An even column probing pad 16-5 to be electrically connected to the odd column probing pad 16-4 and the even column pad 12-2 to be connected is formed at one side.

An insulating layer 22 is formed on the odd row pad 11-1, the even row pad 11-1, the odd column pad 12-1, and the even column pad 12-2. The insulating layer 22 to have contact holes 31 in the terminals of the low pad 11-1, the even low pad 11-2, the odd column pad 12-1, and the even column pad 12-2. This is patterned.

The contact layer 31 is orthogonal to the lower row pad 11-1, the even row pad 11-2, the odd column pad 12-1, and the even column pad 12-2 on the insulating layer 22. The barrier rib 23 having a predetermined interval is not formed to have a predetermined thickness (2 to 10㎛).

On the barrier 23, on the insulating layer 22 between the barrier 23 and the barrier 23, and the contact hole 31, the odd low proving pad 15-1 and the even low probing pad ( 15-2), the cathode layer 24 is patterned so as to cover the terminal portions of the odd column probe pad 16-4 and the even column probe pad 16-5. At this time, the cathode layer 24 is formed to have a significantly thinner thickness than the partition wall (23).

In FIG. 7A, the cathode layer 24 to be patterned has an odd low pad 11-1, an even low pad 11-2, and an odd layer of the anode layer 21 through the contact hole 31 of the insulating layer 22. It is electrically connected to the column pad 12-1 and the even column pad 12-2. In addition, the insulating layer 22 is formed on the odd row probe pad 15-1, the even row probe pad 15-2, the odd column probe pad 16-4, and the even column probe pad 16-5. Since it is not formed is directly connected to the negative electrode layer 24 on one side. Therefore, the cathode layer 24 formed serves as the row shorting bar 13 and the column shorting bar 14.

In FIG. 7B, the barrier 23 has an odd row shorting bar 13-1, an even row shorting bar 13-2, an odd column shorting bar 14-4, and an even column shorting bar 14-5. It is electrically isolated.

Thus, if the row shorting bar and the column shorting bar are divided into odd and even numbers, the shorting state of adjacent lines in the OELD panel part can be checked during the test process.

[Example 4]

8 is a plan view of a test wiring according to a fourth embodiment (full-color) of the present invention, and FIGS. 9A and 9B are cross-sectional views illustrating A-A 'and B-B' of FIG. 4.

The fourth embodiment is a case where it is applied to a full color OELD.

In the test wiring of the OELD according to the fourth embodiment of the present invention, an odd low pad 11-1 and an even low pad 11- 11 are divided into odd-numbered and even-numbered scan lines of the OELD, respectively. 2) are formed to have different lengths, and even low probing to be electrically connected to the odd low probing pad 15-1 and the even low pad 11-2 to be electrically connected to the odd low pad 11-1. Each of the pads 15-2 is configured differently from the second embodiment, and all other configurations are the same.

If the low shorting bar is divided into odd-numbered and even-numbered lines, the short-circuit state of adjacent lines in the OELD panel part can be checked during the test process.

Referring to the above embodiment, the configuration in more combinations can be easily configured by those skilled in the art.

Accordingly, the present invention provides a test wiring structure suitable for organic EL devices to which the photolithography process cannot be applied, so that the test can be performed before the scribing and breaking & breaking process, thereby reducing the processing capacity of the aging and lighting test. It does not need to add equipment to increase and additional arrangement of workers, which reduces the production cost.

Claims (7)

In the monochromatic organic EL device, The anode layer formed on the transparent substrate A plurality of low pads each having a predetermined length connected to a plurality of scan lines of the organic EL element, A plurality of column pads each having a predetermined length connected to a plurality of signal lines of the organic EL device; A low probing pad electrically connected to the plurality of low pads, An insulating layer formed in a pattern including one column probing pad electrically connected to the column pad, the insulating layer formed to have a predetermined contact hole on the row pad and the column pad of the anode layer; A plurality of partition walls orthogonal to the row pads and the column pads on the insulating layer, the barrier ribs having a predetermined interval and a thickness without covering the contact holes; A cathode layer formed on the barrier rib, the insulation layer between the barrier rib and the barrier rib, and a contact hole, and a terminal portion of the low probing pad and the column probing pad, wherein the cathode layer is formed to be thinner than the barrier rib. And the cathode layer electrically connects the row pad and the column pad to the row proving pad and the column proving pad, respectively, through the contact hole of the insulating layer. The method according to claim 1, The column pads are divided into odd-numbered and even-numbered lines of the plurality of signal lines of the EL element, and each of the column pads includes a plurality of odd column pads and even column pads having different lengths. Test wiring. The method according to claim 1, The column probing pad includes an organic column probe pad electrically connected to the odd column pad and an even column probe pad electrically connected to the even column pad. Test wiring. In a full-color organic EL device, The anode layer formed on the transparent substrate includes a plurality of low pads each having a constant length connected to a plurality of scan lines of the full-color organic EL device, A red pad, a green pad, and a blue pad each connected to a plurality of signal lines representing colors of each of the full-color organic EL elements, each having a different length and formed in pairs; A low probing pad electrically connected to the plurality of low pads, One red probing pad electrically connected to the plurality of red pads, And a green probing pad electrically connected to the plurality of green pads, and a blue probing pad electrically connected to the plurality of blue pads. An insulating layer having contact holes formed on the low pads, the red pads, the green pads, and the blue pads of the anode layer; A plurality of partition walls formed on the insulating layer at right angles to the low pads, the red pads, the green pads, and the blue pads, and having a predetermined interval and thickness without covering the contact holes; A cathode formed on the barrier rib, the insulating layer between the barrier rib and the barrier rib, and the upper portion of the terminal of the low probing pad, the red probing pad, the green probing pad, and the blue probing pad are covered and thinner than the bulkhead. With layers, The cathode layer electrically connects the low pad, red pad, green pad, and blue pad with the low probe pad, red probe pad, green probe pad, and blue probe pad, respectively, through the contact hole of the insulating layer. The test wiring of the organic electroluminescent element characterized by the above-mentioned. The method according to claim 1 or 4, And the cathode layer is electrically separated by the partition wall, and is configured of different shorting bars, respectively. The method according to claim 1 or 4, The low pad is divided into a plurality of scan lines of the organic EL device in odd and even numbers, respectively, and has an odd low pad and an even low pad having different lengths. Test wiring. The method according to claim 1 or 4, The low probing pad may include an odd low probing pad electrically connected to the odd low pad, and an even low probing pad electrically connected to the even low pad. .