JP2000353709A - Semiconductor device and electronic component using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device, where a semiconductor substrate is fixed to a mounting member. SOLUTION: A semiconductor substrate 1 and a mounting member 2 are fixed by a solder material, consisting of a kind of substance selected at least from among a group of Sn, Ag, Cu, Ni, P, Bi, Zn, Au and In, and the Pi layer provided on the surface to be fixed of the semiconductor substrate 1 and a solder material are fixed directly. Since the excessive reaction between metals on the fixing surface can be prevented by a Pt layer, reliability of the junction between the semiconductor substrate 1 and the mounting member can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure in which a semiconductor element substrate is fixed to a mounting member with a brazing material, and an electronic device using the same.

[0002]

2. Description of the Related Art A semiconductor element substrate is bonded to a metal mounting member of a semiconductor device by a brazing material having a relatively low melting point.
For example, Japanese Unexamined Patent Publication No. 4-49630 as a first prior art discloses a Sn-Sb alloy brazing alloy, which contains both Ni, Cu and P, and is used for assembling semiconductor devices. ing. In this case, the mechanical strength of the brazing material itself is increased by adding Sb to Sn, and Ni-Sn or Cu-Sn is added to the interface between the solder layer and the surface of the member to be bonded.
It is said that the production of n intermetallic compounds is suppressed, thereby improving the reliability of the semiconductor device.

Japanese Patent Publication No. Hei 3-3937 as a second prior art example discloses a semiconductor device in which a semiconductor element and a mounting member for supporting the semiconductor element are brazed with a brazing material. 87-92.4% tin with a weight ratio of 7.0-10.
A semiconductor device composed of 0% antimony and 0.6 to 3.0% by weight of nickel is disclosed. According to this technique, it is said that the mechanical strength of the brazing material is high, the formation of an alloy of copper and tin is suppressed, and the reliability of the semiconductor device is improved.

[0004]

In the case where the heat value of the semiconductor device is small and the required reliability is not so high, the semiconductor substrate is bonded to the metal mounting member by using any kind of brazing material. No problem. However, when a large amount of heat is generated and high reliability is required, a brazing material to be applied must be selected. From such a viewpoint, a Sn-5 wt% Sb-based solder material having high rigidity and high breaking strength is selected as the brazing material for die bonding.
At this time, the die bonding surface of the semiconductor substrate is made of Cr-Ni-A having an adhesive property with the brazing material and the semiconductor substrate.
g or a multilayer metal layer such as Ti-Cu-Au. Here, the outermost surface metal such as Ag or Au dissolves in the brazing material and disappears from the bonding interface, but Ni or Cu
The intermediate metal layer as described above remains at the interface without being dissolved in the brazing material, and plays a role as a barrier for suppressing the reaction between the brazing material and the lowermost metal such as Cr or Ti. The reason why the intermediate metal layer having such a role is provided is that, when a structure in which the lowermost metal and the brazing material are in direct contact with each other is used, it is considered that (a) bonding is impossible because the two are not metallurgically bonded. I was
Alternatively, it is based on the assumption that (b) the lowermost metal is eroded by the brazing material and disappears due to the reaction between the two, and a strong adhesive force cannot be obtained.

[0005] The Sn-Sb alloy brazing alloy containing Ni, Cu and P disclosed in the first prior art example and the 87-92.4 wt% Sn-7.0-0.7% disclosed in the second prior art example. 1
Each of the 0.0 wt% Sb-0.6 to 3.0 wt% Ni brazing material contains an overwhelmingly large amount of Sn. These brazing materials actively react with other metals in a molten state, and this metal is melted into the molten brazing materials. Therefore, not only the outermost layer metal such as Ag or Au in the above-described multilayer metal layer but also the intermediate metal layer such as Ni or Cu dissolves in the brazing material and disappears from the bonding interface. As a result, the brazing material comes into direct contact with the lowermost metal such as Cr or Ti, and the reaction between the two is promoted, and the adhesive strength between the semiconductor substrate and the brazing material is reduced. In particular, when thermal or mechanical stress is applied to the semiconductor device, breakage such as a crack is easily generated between the semiconductor substrate and the brazing material. The die bonding interface of the semiconductor substrate often also serves as one conductive path or heat radiation path of the semiconductor device, and to maintain its performance, destruction of the die bonding interface must be avoided.

On the other hand, a solder material containing Pb, which has been conventionally used in many semiconductor devices, is required from the viewpoint of environmental protection.
Approaches have been made to avoid its use. The Sn—Sb-based brazing material disclosed in the first and second prior art examples is S
n simple substance metal, Sn-3.5wt% Ag, Sn-3wt%
Ag—Sn—Ag represented by 0.8 wt% Cu
System, Sn-B as represented by Sn-58wt% Bi
i-based, Sn as represented by Sn-0.7 wt% Cu
-S such as Cu-based, Sn-52wt% In
n-In based, S-9 as represented by Sn-9wt% Zn
Along with the n-Zn system, the In-Ag system typified by In-10 wt% Ag, and the An-Sn system typified by Au-20 wt% Sn, the material for the purpose of environmental protection described above. Can be However, when any of the above brazing materials is in a molten state, the interface disappears due to the dissolution of the intermediate metal layer and the reaction between the brazing material and the lowermost metal is promoted, and the adhesive strength at the die bonding interface is reduced.

The present invention has been made in consideration of the above-mentioned problems, and provides a semiconductor device and an electronic device having high manufacturing yield or high reliability.

[0008]

According to a semiconductor device of the present invention, a semiconductor substrate and a member on which the semiconductor substrate is mounted are made of Sb,
A Pt layer fixed to at least one material selected from the group consisting of Ag, Cu, Ni, P, Bi, Zn, Au and In with a brazing material made of Sn and provided on the surface to be fixed of the semiconductor substrate; It has an adhesive structure in which the solder material is directly fixed.

In an electronic device using a semiconductor device according to the present invention, a semiconductor substrate and a member on which the semiconductor substrate is mounted are made of Sn,
At least one material selected from the group consisting of Sb, Ag, Cu, Ni, P, Bi, Zn, Au and In is fixed by a brazing material made of Sn and Pt provided on the surface to be fixed of the semiconductor substrate. A semiconductor device having an adhesive structure in which a layer and the brazing material are directly fixed is incorporated in a device for supplying power to a load.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device 30 according to the present invention
It has a form like a bird's-eye view and a sectional view shown in FIG. First, look at the bird's-eye view of (a). IGBT (Insulated Gate Bipo) as a power semiconductor substrate made of Si
lar Transistor) Chip 1 has a thickness as a mounting member:
It is fixed on a mounting member or a circuit board (hereinafter referred to as Cu base plate) 2 which is a 1 mm Cu base plate by a brazing material 3 (not shown). At this time, brazing is performed by heating to about 270 ° C. in a reducing atmosphere. Ni plating (not shown, thickness: 3 to 7 μm) on the surface of the Cu base plate 2
Is given. On the Cu base plate 2, a thick film C
An alumina ceramics substrate 5 provided with u wiring (not shown) 4 is attached by a silicone resin adhesive (not shown). A thick film resistor 11 and an IC chip substrate 1 are provided between the thick Cu wirings 4 of the alumina ceramic substrate 5.
2, chip components such as a capacitor chip 13 and a glass sleeve type Zener diode chip 14 are fixed by a brazing material 3 '(not shown), and a circuit 10 for controlling the IGBT chip 1 is formed. IGBT
The emitter electrode and gate electrode of chip 1 have a diameter of 300 μm.
It is electrically connected to the control circuit 10 by m Al wires 6. The collector electrode of the IGBT chip 1 is electrically connected to the terminal 7 via the Cu base plate 2 and the Al wire 6 '. The control circuit 10 is also electrically connected to the terminal 7 by the Al wire 6 '. The terminal 7 is made of the same material as the Cu base plate 2, and its surface is plated with Ni (not shown, thickness: 3 to 7 μm). When the base material of the mounting member is a Cu material, the base material may be exposed on the surface, but it is preferable to perform plating of Ni, Au, Ag, or the like to maintain higher quality.

An assembly having the above-described schematic structure is as follows:
As shown by the broken line in the cross-sectional view shown in (b), the mounting portion of the IGBT chip 1, the mounting portion of the alumina substrate 5 to which the chip components are attached, and the Al wines 6 and 6 'are completely sealed. The mold including the Cu base plate 2 and a part of the terminal 7 is molded with the epoxy resin 8.

FIG. 2 is a schematic sectional view of the IGBT chip mounting portion. The IGBT chip 1 has an S on the Cu base plate 2.
n-5wt% Sb-0.6wt% Ni-0.05wt% P
And is fixed by a brazing material 3 having a thickness of 200 μm. The IGBT chip 1 before fixation is provided with Ti by an evaporation method.
A multilayer metal layer composed of (0.1 μm) -Pt (0.2 μm) -Au (0.1 μm) was formed. Here, the outermost layer 1C
Au melts into the brazing material 3 and disappears from the bonding interface, but the Pt intermediate metal layer 1B does not melt into the brazing material but remains at the interface and is in direct contact with the brazing material 3. This is a characteristic point of the present invention. Further, the Ti lowermost layer metal 1A is maintained in a state before fixing without reacting with the brazing material 3 due to the reaction suppressing action of the Pt intermediate metal layer 1B. FIG. 3 is a metal depth profile in the IGBT chip mounting portion. This profile is SIMS
It was obtained by analysis (Secondary Ion Mass Spectroscopy). Si is a base material of the IGBT chip, and T
i is the lowermost metal layer 1A, Pt is the intermediate metal layer 1B, and S
n is a main component of the brazing material 3. Ti and Pt located in the middle of the region of Si and Sn as the brazing material 3 have independent peaks, respectively. From this profile, the Pt layer 1B is not eroded by Sn,
Then, it can be confirmed that there is no evidence of a reaction between the lowermost metal 1A as the Ti layer and Sn or Si. As described above, the intermediate metal layer 1B remains at the interface without being dissolved in the brazing material even after being fixed, and the Ti lowermost metal 1A and the brazing material 3
And plays an original role as the intermediate metal layer 1B. This is an effect of selecting Pt having low solubility in Sn as the intermediate metal layer 1B.

[0013] Sn-5 wt% Sb- as brazing material 3
0.6wt% Ni-0.05wt% P is Sn simple metal,
Other Sn-Sb represented by Sn-5wt% Sb
System, Sn-3.5wt% Ag, Sn-3wt% Ag-
Sn-Ag based such as 0.8 wt% Cu, S
a Sn-Bi system represented by n-58 wt% Bi,
Sn-Cu represented by Sn-0.7 wt% Cu
System, Sn-I as represented by Sn-52wt% In
n-type, Sn-Z represented by Sn-9wt% Zn
n-type, In-10 represented by In-10 wt% Ag
It can be replaced with an Ag-based material and an Au-Sn-based material represented by Au-20wt% Sn. Each of these alloy materials has a property of easily dissolving a metal. However, the Pt layer as the intermediate metal layer 1B has excellent reaction suppression performance with respect to any of the brazing materials described above. As a result, the lowermost metal 1A is Ti, Cr, M
In the case of any metal selected from the group consisting of o, W, Al, Zr, and Hf, the reaction between the lowermost metal 1A and the brazing material 3 is suppressed, and the adhesion of the IGBT chip fixing portion is maintained strong. This effect is due to the fact that the brazing material 3 has the Sn-Sb
System, Sn-Ag system, Sn-Bi system, Sn-Cu system, Sn
-In system, Sn-Zn system, In-Ag system and Au-S
It does not change even when the alloy is an n-type alloy with the third and fourth trace metals added.

An IGBT chip 1 as a power semiconductor substrate includes a transistor, a thyristor, a diode, and a MOSFET.
It is possible to replace with a semiconductor element substrate having an electrical function other than an IGBT element such as a transistor, and even if these elements are made of a material other than Si (for example, a compound semiconductor such as GaAs or SiC), The effect obtained is as follows.

The Cu base plate 2 as a mounting member has N
It is not essential to apply i-plating. Further, the Cu base plate 2 can be replaced with an Al plate. In this case, in order to impart wettability to the brazing material, Ni,
It is desirable to perform plating of Au, Ag, or the like.

On the other hand, FIG. 4 is for comparison, and Ti (0.1
7 is a depth profile of metal in an IGBT chip mounting portion provided with a multilayer metal layer composed of (μm) -Ni (0.6 μm) -Ag (0.2 μm). Ti as the lowermost metal is broadly distributed in the IGBT chip region, the intermediate metal layer region, and the brazing material region. Also, Ni as the intermediate metal layer 1B is broadly distributed in the lowermost metal and brazing material regions. Sn as a brazing material has not only penetrated into the intermediate metal layer region and the lowermost metal region but also reached the Si region. This suggests that it is difficult for the intermediate metal layer in the comparative sample to play the original role of this layer. Even when the Ni layer as the intermediate metal layer is replaced with another metal such as Cu or Pd, it is difficult to fulfill the role of the intermediate metal layer as in the case of Ni.

The chip parts 12, 13, 1 of the control circuit 10
4 and the like are fixed on the alumina substrate 5 by a brazing material 3 'made of Sn-3wt% Ag-0.8wt% Cu.
The brazing material 3 ′ is made of Sn simple metal,
Sn-5wt% Sb, Sn-5wt% Sb-0.6wt
% Ni-0.05 wt% P
-Sb-based, Sn-Ag-based as represented by Sn-3.5 wt% Ag, Sn-Bi-based represented by Sn-58 wt% Bi, and Sn-0.7 wt% Cu. Sn-Cu-based, Sn-In-based as typified by Sn-52 wt% In, Sn-Zn-based typified by Sn-9 wt% Zn, In-like typified by In-10 wt% Ag -Ag based and Au-20wt% Sn
Can be replaced with an Au-Sn system as represented by

The alumina substrate 5 has chip components 12, 1
If the heat released from 3, 3, or the like is excessive, it may be replaced with a high thermal conductive ceramic such as AlN or SiC to facilitate heat radiation. At this time, the thick film Cu wiring 4 is made of Ag-P
It can be replaced with a t-type thick film conductor. The reason for this is that the electric function of the control circuit 10 can be normally maintained by suppressing the melting (in other words, disappearance) of the wiring 4 into the brazing material 3 ′ due to melting. When the heat emitted from the chip components 12, 13, 14 and the like is small, the alumina substrate 5 may be made of bismuthimide triazine (BT) resin containing glass cloth, glass epoxy resin, epoxy resin, bakelite resin, polyimide resin, or the like. It is also possible to use a material in which metal wiring such as a copper foil layer is provided on an insulating substrate as a base material. At this time, Ni, A
u, Ag or the like may be plated. IGBT chip 1
Epoxy resin 8 for sealing the control circuit 10 and the like
Is a phenol-curable epoxy resin to which SiO ₂ (fused silica, crystalline silica) or ZnO powder is added as a filler. In this case, the addition amount of the filler is 50 to 90% depending on the desired coefficient of thermal expansion and the mold processing temperature.
Can be selected. Further, a rubber-modified epoxy resin may be used. These resins are
It is desirable to use the transfer mold method from the viewpoint of productivity and economy. However, the desired water resistance, electrical performance,
As long as reliability and the like are satisfied, it is also possible to seal by a potting method.

FIG. 5 shows the residual thickness when the metal layer comes into contact with the molten brazing material. 28 for metal layer with initial thickness of 5 μm
The brazing material 3, which is a molten Sn-5 wt% Sb material at 0 ° C., is brought into contact. All of the investigated metals are used for the multilayer metal layer on the brazing surface of the semiconductor substrate. Au or Ag used as the outermost layer is rapidly dissolved in the brazing material 3 and hardly remains in a layered form. A used as the bottom layer
l, Ti, Cr, Mo and W, and Pd, Cu and Ni used as an intermediate metal layer are easy to dissolve, though not as much as Au and Ag. In contrast, Pt used as the intermediate metal layer or the outermost layer has a low dissolution rate and a large residual thickness. As described above, the Pt layer 1B as the intermediate metal layer remains at the interface without being melted into the brazing material even after being fixed, and can be a barrier for suppressing the reaction between the lowermost metal 1A and the brazing material 3. It is based on having excellent melting resistance to the molten brazing material 3 containing a large amount of Sn.

The above configuration will be described with reference to the drawings.

[Embodiment 1] In this embodiment, a semiconductor device equipped with a power semiconductor element base and a control circuit for controlling the electric operation thereof, and an automobile ignition device using this semiconductor device will be described.

The semiconductor device 30 mounted with the power semiconductor element substrate 1 and the control circuit 10 for controlling the electric operation thereof is
It has the bird's-eye view structure and the cross-sectional structure shown in FIG. Si
IGBT chip base 1 (chip size: 5 × 5
× 0.25 mm) is a Cu with a thickness of 1 mm and an area of about 25 × 20 mm.
Composition Sn-5 wt% Sb-0.6 wt% N on base plate 2
It is fixed by i-0.05 wt% P brazing material 3 (not shown). The thickness of the Cu base plate 2 is 3 to 7
μm Ni plating (not shown) is applied. IG
On the fixed surface (collector) of the BT chip base 1, a Ti layer (0.1 μm) as the lowermost metal layer 1A, an intermediate metal layer 1
A multilayer metal layer composed of a Pt layer (0.2 μm) as B and an Au layer (0.1 μm) as outermost layer 1C is formed by vapor deposition. At this time, the brazing is 200μ thick.
This was carried out by laminating the above-mentioned brazing material 3 having a size of 5 × 5 mm between the chip base 1 and the base plate 2 and heating the laminated body to 270 ± 10 ° C. in a hydrogen-added nitrogen atmosphere.

On the other hand, a thick film Cu wiring (not shown) having a thickness of about 15 μm, a thick film resistor 11, and an overcoat glass layer (not shown) were provided. Size: 19 × 10 × 0.8m
An alumina ceramic substrate 5 of m m was prepared. Then
A paste containing a brazing material powder having a composition of Sn-3 wt% Ag-0.8 wt% Cu, which finally becomes a brazing material 3 ′, is printed on a desired region of the alumina substrate 5, and the IC chip base 12, Chip components such as the capacitor chip 13 and the glass sleeve type Zener diode chip 14 were mounted and heated to 260 ± 10 ° C. in air. As a result, each of the chip components 12, 13, 14 and the thick film resistor 11 are electrically connected to the thick film Cu wiring 4 by the brazing material 3 '.
A control circuit 10 for controlling the operation of the IGBT chip base 1 was formed on the alumina substrate 5. The alumina substrate 5 is mounted on the Cu base plate 2 with a silicone resin adhesive (not shown) 9. IGBT
The emitter electrode and gate electrode of chip 1 have a diameter of 300 μm.
It is electrically connected to the control circuit 10 by m Al wires 6. The collector electrode of the IGBT chip 1 is electrically connected to the terminal 7 via the Cu base plate 2 and the Al wire 6 '. The control circuit 10 is also electrically connected to the terminal 7 by the Al wire 6 '. The terminal 7 is made of the same material as the Cu base plate 2, and its surface is plated with Ni (not shown, thickness: 3 to 7 μm).

The assembly having the above general structure is as follows.
As shown by the broken line in the cross-sectional view shown in (b), the mounting portion of the IGBT chip 1, the mounting portion of the alumina substrate 5 to which the chip components are attached, and the Al wires 6 and 6 'are completely sealed. The transfer molding using the epoxy resin 8 including the Cu base plate 2 and a part of the terminal 7 is performed. The epoxy resin 8 has a thermal expansion coefficient of 16 ppm / ° C., a glass transition point of 155 ° C., and a volume resistivity of 9 × 10 ¹⁵ Ω · m (R
T), flexural strength: 3 × 10 ¹⁵ kgf / mm ² , flexural modulus: 1
It has a characteristic of 600 kgf / mm ² . The transfer mold was performed at 180 ° C., and then subjected to a heat treatment at 150 ° C. for 2 hours to accelerate the curing of the resin.

FIG. 2 is a schematic sectional view of the IGBT chip mounting portion, and FIG. 3 is a metal depth profile in the IGBT chip mounting portion. IGBT chip 1 before fixing
Include Ti (0.1 μm) -Pt (0.2 μm) -Au (0.1
μm). After the fixation, Au1C of the outermost layer melts into the brazing material 3 and disappears from the bonding interface, but the Pt intermediate metal layer 1B remains at the interface without being dissolved in the brazing material and directly adheres to the brazing material 3. In state. This is a characteristic point of the present invention. Further, the Ti lowermost layer metal 1A is maintained in a state before fixing without reacting with the brazing material 3 due to the reaction suppressing action of the Pt intermediate metal layer 1B. This can be confirmed from the depth profile of FIG. This is an effect of selecting Pt having low solubility in Sn as the intermediate metal layer 1B.

FIG. 6 shows a change in thermal resistance of a semiconductor device in a temperature cycle test. A curve A in the figure is a semiconductor device 30 of the present embodiment, and a curve B is a semiconductor device for comparison (IGB
Ti (0.1 μm) -Ni (0.6 μm)
m) -Ag (0.2 μm), and a multilayer metal layer was formed using the same members, materials and processes as in the present embodiment. Therefore, IGBT
The depth profile of the metal in the chip mounting portion is such that Ti as the lowermost layer metal is broadly distributed in the IGBT chip region, the intermediate metal layer region and the brazing material region, as in FIG. Broadly distributed in the metal and brazing regions. In addition, Sn as a brazing material has not only penetrated into the intermediate metal layer region and the lowermost metal region but also reached the Si region. The thermal resistance of the semiconductor device 30 of the present embodiment is represented by the number of temperature cycles: 500
The initial value is maintained in the tests up to 0 times. As described above, it is confirmed that the semiconductor device 30 of this example has excellent reliability. On the other hand, in the case of the comparative semiconductor device, the thermal resistance increases when the number of temperature cycles exceeds 100. This means that the IGBT chip brazed portion has been broken, which impairs the thermal conductivity, and suggests that the Ni layer is difficult to play the original role of the intermediate metal layer. As a result of disassembling the comparative semiconductor device after the test and examining the fracture surface of the brazing portion of the IGBT chip,
Destruction due to temperature cycling is caused by the Si-Ti layer interface and Ti
It was confirmed that it occurred near the interface between the layer and the brazing material.

The shear strength of the IGBT chip brazing portion in the semiconductor device 30 of the present embodiment and the comparative semiconductor device was compared. The shear strength was 3.5 kg / mm ² in the case of the semiconductor device 30 of the present example, whereas the shear strength was 1.3 kg / mm ^{2 in} the case of the semiconductor device for comparison. Destruction by this test occurred in the region of the brazing material 3 in the case of the semiconductor device 30 of the present example, whereas in the case of the semiconductor device for comparison, in the vicinity of the interface between the Si—Ti layer and the interface between the Ti layer and the brazing material. It had occurred in.

FIG. 7 is a diagram for explaining the circuit of the semiconductor device 30 of the present embodiment. The emitter and gate of the IGBT element 1 are electrically connected to a control circuit 10, and the operation of the element 1 is controlled by the control circuit 10. A resistance 11, an IC 12, and a capacitor 13 are mounted on the control circuit 10, and these elements are connected by a thick-film Cu wiring 4. Terminals 7 are drawn from the IGBT element 1 and the control circuit 10, respectively. The semiconductor device 30 includes an IGBT element 1 and a control circuit 10 for controlling the IGBT element 1, and is used to supply power to a coil of an automobile engine ignition device. FIG.
7 is an example of another semiconductor device used to supply power to the coil of the vehicle engine ignition device as in the circuit of FIG. The control circuit in this case includes a surge protection element 13A.
And a diode 14 are also mounted. The semiconductor device 30 composed of these circuits was used to ignite an automobile engine under an environment having a maximum ambient temperature of 120 ° C. It has been confirmed that the semiconductor device 30 of the present embodiment maintains its circuit function even when the vehicle travels for 100,000 kilometers.

[Embodiment 2] In this embodiment, a metal-bonded circuit board in which a Cu plate is integrated with an AlN ceramics plate is used.
A semiconductor device in which a power semiconductor element substrate is mounted on a mounting member in which a supporting member made of a plate is joined and an electronic device using the semiconductor device will be described.

The semiconductor device 30 of this embodiment has a form as shown in a bird's-eye view shown in FIG.

I as a power semiconductor substrate made of Si
A GBT (Insulated Gate Bipolar Transistor) chip (13 × 13 × 0.3 mm) 101 and a diode chip (10 × 10 × 0.3 mm) 101 ′ have a composition Sn-5 wt% Sb-0.6 wt% on the mounting member 2. Ni-0.05w
Brazing material 3 with t% P and thickness of 200 μm (not shown)
(270 ± 10 ° C., in a hydrogen atmosphere). The mounting member 2 has a dimension of 40 × 95 × 3 mm.
A metal bonded circuit board 155 is formed on a support plate 125 made of a Cu plate plated with i-plate (not shown, 3 to 7 μm in thickness) by brazing material 3 ″ having a composition of Sn−3.5 wt% Ag (not shown).
Composite material (250 ± 10 ° C., in a hydrogen atmosphere). FIG. 10 is a schematic cross-sectional view showing the form of the metal-bonded circuit board 155. A 300 μm thick Cu plate 15a (also serving as a collector electrode), 15b (also serving as an emitter electrode), and 15c (also serving as a gate electrode) are provided on both sides of an AlN sintered body 15 having a size of 31 × 60 × 0.63 mm. ,
A Cu plate 15d having a thickness of 150 μm is placed on a T
Ag-28 wt% Cu braze 150 added with 2 wt% i
a, 150b, 150c and 150d. Cu plates 15a, 15b, 15c and 15d
On the surface of Ni by electroless plating to a thickness of 3 to 7 μm.
A layer (not shown) is formed. Each semiconductor substrate 10
1, 101 'is wire-bonded with an Al wire (diameter: 550 .mu.m) 117 to form an emitter electrode 15b,
It is connected to the gate electrode 15c.

Collector electrode 15a, emitter electrode 15
b and the gate electrode 15c respectively have external terminals 116,
116 'are provided, and each of the semiconductor substrates 101, 10
1 ', an epoxy resin case (not shown) is provided so that the metal-bonded circuit board 155 and the like are completely shielded from the outside air, and the case is filled with silicone gel or epoxy resin and cured to cure the semiconductor device. 30 was obtained.

FIG. 11 is a schematic sectional view of the mounting portion of the semiconductor substrates 101 and 101 '. (A) is a semiconductor substrate 101,1
01 'before fixation. Semiconductor substrate 10
1,101 'is fixed on the fixing surface so as to obtain ohmic contact.
After forming a layer 1a in which i and Ni are mixed, a Cr layer 1A (0.15 μm) as a lower metal layer and a P layer as an intermediate metal layer are formed.
t layer 1B (0.45 μm), Ag layer 1C as outermost layer
(1.3 μm) are sequentially formed by electron beam evaporation. (B) shows a state after the semiconductor substrates 101 and 101 'are fixed. The Ag layer 1C dissolves in the brazing material 3 and disappears from the interface, but the Pt layer 1B remains without being eroded by the brazing material 3. The Pt layer 1B and the brazing material 3 are metallurgically bonded in direct contact with each other. Further, since the Pt layer 1B effectively functions as a reaction barrier between the brazing material 3 and the layers 1A, 1a and the base 1, the layers 1A, 1a and the base 1 at the brazing interface have the same laminated state as the initial state. Has been maintained.

IGBT in the semiconductor device 30 of the present embodiment
The shear strength of the brazed part was measured.
A large difference of 9 kg / mm ² was observed. Destruction by this test has occurred in the region of the brazing material 3 and not in the layers 1A, 1a and the base 1. Also, the base 1 of the semiconductor device 30
01 and the support member 125 have a thermal resistance of 0.23 ° C./W 2. The reason why such a small value was obtained is that the Pt layer 1B
This contributes to the fact that a defect-free bond is formed due to the presence of.

The semiconductor device 30 of this embodiment constitutes the circuit shown in FIG. A test was performed in which the device 30 was intermittently energized to repeatedly change the temperature of the support member 125 between 30 and 100 ° C. FIG. 13 shows the transition of the thermal resistance by the intermittent conduction test. The thermal resistance (A) of the semiconductor device 30 of the present embodiment shows almost no change up to 35,000 times.
Even after 0000 times, the temperature slightly increased to 0.28 ° C./W. However, this increase in thermal resistance does not affect the function of the semiconductor device 30. On the other hand, curve B shows the transition of the comparative sample. In the comparative sample, Pt as the intermediate metal layer
Although the layer 1B is replaced by a Pd layer (1.5 μm), the other configuration is the same as that of the semiconductor device 30 of the present embodiment. In this case, the thermal resistance increases from the early stage with the number of tests, and at 15,000 times, is twice or more the initial value. Thus, the semiconductor device 30 is much more stable than the comparative sample and maintains excellent heat dissipation. The reason why the heat release property of the comparative sample decreased early was that the bonding strength near the interface of the brazed part was reduced due to the reaction and erosion by the brazing material,
This is because a strong adhesive force against thermal stress based on a temperature change accompanying the test could not be maintained. On the other hand, the reason why the semiconductor device 30 of the present embodiment was able to maintain good heat dissipation for a long period of time was that a strong interface bonding force could be maintained based on the reaction barrier effect of the Pt layer 1B.

Next, the semiconductor device 30 was incorporated into an inverter 900 for controlling the number of revolutions of a motor 950 shown in FIG. FIG. 15 shows the relationship between the switching frequency and the heat generation temperature of the IGBT element base 101 when the rotation speed of the electric motor 950 is controlled using the inverter device 900. The switching loss increases as the frequency increases, but does not exceed 125 ° C., which is a temperature at which the element substrate 101 can operate stably, between 50 Hz and 30 kHz of the commercial power supply. During this time, the motor 950 operates without any special measures.

The inverter device 900 and the motor 9
50 was incorporated into an electric vehicle as its power source.
In this vehicle, the driving mechanism from the power source to the wheels can be simplified, so that the shock at the time of shifting is reduced as compared with a conventional vehicle that is irregular due to a difference in the gear engagement ratio. Furthermore, this car can run smoothly in the range of 0 to 259 km / h, and in terms of vibration and noise generated by a power source, it is about half that of a car equipped with a conventional cylinder engine. We were able to reduce.

Further, an inverter 900 incorporating the semiconductor device 30 of the present embodiment and a brushless DC motor were incorporated into a cooling / heating machine (power consumption during cooling: 5 kW, power consumption during heating: 3 kW, power supply voltage: 200 V). .
FIG. 16 is a graph showing the efficiency (curve A) of the electric motor at this time. This is shown in comparison with the case where a conventional AC motor is used (curve B). In the case of the present embodiment, the efficiency is higher by 10% or more than that of the conventional case in the whole range of the rotational speed compared.
This is useful for reducing the power consumption when using the air conditioner. In addition, the time from the start of operation to the time when the indoor temperature reaches the set temperature was reduced to about 1/2 in the case of the present embodiment as compared with the case of using the conventional AC motor.

The effects of this embodiment can be enjoyed even when the semiconductor device 30 is incorporated in a device for stirring or flowing another fluid, for example, a washing machine, a fluid circulation device, or the like.

[Embodiment 3] In this embodiment, a semiconductor device in which a power semiconductor element substrate is mounted on a mounting member in which circuit wiring is formed on an Al plate and an electronic device using this semiconductor device will be described.

FIG. 17 is a schematic sectional view of the semiconductor device 30 of this embodiment. The semiconductor device 30 includes an Al plate 201 (dimensions:
20.5 × 38 × 1.5 mm) and a Cu wiring layer 203 via an epoxy insulating layer 202 (thickness: 80 μm) on one main surface.
A power MOSFET element substrate 1 (dimensions: 5 ×) is placed on a circuit board 2 as a mounting member having a thickness (70 μm) selected and formed.
5 × 0.25 mm), the passive element comprising the chip resistor 11 and the capacitor chip 13 and the terminal 7 comprising phosphor bronze
Brazing material 3 having composition Sn-5 wt% Sb (thickness: 20 to
100 μm), and are electrically and mechanically fixed. Further, a diameter of 30 is provided between the base 1 and the Cu wiring layer 203.
An Al wire 6 of 0 μm is formed by ultrasonic bonding. The mounted components 1, 11, 13, 7, the brazing material 3, the Ai wire 6, and the circuit board 2 have a thermal expansion coefficient of 16 ppm /
It is hermetically sealed by a transfer mold of the epoxy resin 8 adjusted to ° C.

FIG. 18 is a block diagram showing the inside of the semiconductor device 30 of this embodiment. The device 30 includes a gate drive circuit 60 for driving the MOSFET element base 1 and a control unit 70 for controlling the gate drive circuit 60. Further, the semiconductor device 30 employs a resonance power supply control IC and a power MOSFET with a withstand voltage of 200 V.
The transistor 1 is housed therein, and is suitable for a small-sized, high-efficiency, low-noise resonance-type power supply device, particularly for a resonance-type AC / DC converter power supply. In the case of a resonant AC / DC converter, the switching frequency is 0.5 GHz and the efficiency is 90%
The above performance has been obtained. This includes (1) overcurrent overvoltage protection function, (2) overheat protection function, (3) gate drive circuit, (4) soft start function, and (5) uniform characteristics.
It is based on the fact that each of the power MOSFET transistors is built-in.

The W-layer 1A (0.5 μm) as the lower metal, the Pt layer 1B (0.45 μm) as the intermediate metal layer, and the Ag as the outermost layer are formed on the brazing surface of the MOSFET element substrate 1. Layer 1C (1.3 μm) was sequentially formed by electron beam evaporation. After brazing, the Ag layer 1C dissolves in the brazing material 3 and disappears from the interface.
B remains without being eroded by the brazing material 3. The Pt layer 1B and the brazing material 3 are metallurgically bonded in direct contact with each other. Further, the Pt layer 1B and the brazing material 3
Effectively acts as a reaction barrier between the layer 1A and the substrate 1 and the layer 1A and the substrate 1 at the brazing interface are maintained in the same laminated state as the initial state.

[Embodiment 4] In this embodiment, a semiconductor device in which a SiC base 1 as a power semiconductor element is fixed to a mounting member 2 will be described.

FIG. 19 shows a cross-sectional structure of a Zener diode as a small semiconductor device 30.

Diode substrate 1 (0.5) made of SiC
× 0.5 × 0.25 mm) was placed on a mounting member 2 obtained by plating a Cu alloy (not shown) of about 3 μm on a 42 alloy (Fe-42 wt% Ni) having a thickness of 0.5 mm. 12w
It is fixed by the brazing material 3 of t% Ge (thickness: 50 μm). The mounting member 2 is processed as a lead frame together with the terminals 7, 7 '. Terminal 7 carries the cathode electrode and 7 'carries the anode electrode. A wire between the diode base 1 and the terminal 7 is bonded with an Au wire having a diameter of 70 μm. The transfer molding of the epoxy resin 8 is applied to these integrated products by the same material and process as in the first embodiment, and all members except for some of the terminals 7, 7 'are sealed. The semiconductor device 30 thus obtained has an outer dimension of about 2.5 × 1 × 2 m.
m.

Initially, the brazing surface of the diode base 1 is
Cr layer 1A (0.15 μm) as lower metal, Pt layer 1B (0.45 μm) as intermediate metal layer, A as outermost layer
The u layer 1C (1 μm) was sequentially formed by an electron beam evaporation method. The brazing portion of the completed semiconductor device 30 is P
It has a structure in which the t layer 1B and the brazing material 3 are in direct contact,
No evidence of the reaction or erosion of the Cr layer 1A as the lower metal by the brazing material 3 is observed. Example 3 Semiconductor Device 3
0, High temperature test at 175 ° C (5000h) and 8
A high temperature and high humidity test of 5 ° C. and 85% RH was performed. These tests did not impair the adhesive strength of the braze at all.

The substrate 1 of this embodiment is made of SiC and other compound semiconductors, for example, Ga-As, Ga-P, Ga-Al-P.
It may be replaced by an -As-based substance.

The embodiments of the present invention have been described above. In the present invention, the mounting member 2 on which the semiconductor substrate is mounted is not limited to the materials described in the embodiments. For example, as an alternative to the Cu base plate 2 in the first embodiment, metals having Cu, Al, Fe, Mo, W, Ni, Zn as main components, these metals and other inorganic substances such as M
It may be a composite with o, W, SiC, C powder or fiber, or a laminated integrated composite of these metals and other alloys such as Invar. At this time, in order to improve the wettability of the mounting member 2 with respect to the brazing material,
u, Ni, Ag, Au, Pt, Pd, Sn, Sb, A
It is preferable to coat l, Zn, or an alloy thereof. At this time, not only the plating method but also a vapor deposition method or a sputtering method may be used.

Further, as shown in the second embodiment, the mounting member 2 may be a composite in which different kinds of members are combined. For example, the AlN base material of the metal bonded circuit board 155 may be replaced with alumina, and the support plate may be made of Cu, Al, Fe, Mo,
Metals containing W, Ni, and Zn as main components, composites of these metals with other inorganic substances such as Mo, W, SiC, C powder or fibers, and lamination and integration of these metals with other alloys such as Invar It may be a complex.

In the semiconductor device according to the present invention, the brazing material 3 can be selected from various components and compositions according to the process in which the semiconductor device is manufactured, the characteristics required for the semiconductor device, especially the reliability against thermal fatigue. In other words, Sb, Ag, Cu, Ni, P, and Sb can have an adhesive structure in which the thin Pt layer provided on the surface to be fixed of the semiconductor substrate and the solder material can be directly fixed.
The brazing material may be made of Sn and at least one material selected from the group consisting of Bi, Zn, Au and In.

In the semiconductor device according to the present invention, the semiconductor device is specified by being incorporated in an electric circuit for supplying power to a load. At this time, (1) the semiconductor device is incorporated in an electric circuit for supplying power to the rotating device to control the rotating speed of the rotating device, or a system that moves itself (for example, a train, an elevator, an escalator, (2) When the electric circuit that feeds the rotating device is an inverter circuit, (3) the semiconductor device agitates or flows the fluid. In the case of controlling the moving speed of the object to be stirred or the object to be fluidized,
(4) A case where the semiconductor device is incorporated in a device for processing an object to control a grinding speed of a workpiece, and (5) A case where the semiconductor device is incorporated in a light emitter and the amount of emitted light of the light emitter is controlled. (6) Even when the semiconductor device operates at an output frequency of 50 Hz to 30 kHz, the same effects and advantages as those of the above embodiment can be obtained.

In the semiconductor device according to the present invention, the material which can be the semiconductor bases 1, 101, 101 'is Si:
4.2 ppm / ° C, Ge: 5.8 ppm / ° C, CaAs: 6.5 p
pm / ° C, GaP: 5.3 ppm / ° C, SiC: 3.5 ppm / ° C
And so on. There are no restrictions on mounting semiconductor elements made of these materials. At this time, the semiconductor substrate may have an electrical function, such as a thyristor or a transistor, which is not described in the embodiments.

In the semiconductor device according to the present invention, the electric circuit of the semiconductor device is not limited to those described in the embodiments.
For example, as shown in FIG. 20, providing various electric circuits inside a semiconductor device does not hinder the use of the circuits in an electronic device. At this time, it is also preferable that a passive element is incorporated in an electric circuit inside the semiconductor device.

[0055]

According to the present invention, excessive interfacial reaction when the semiconductor substrate is fixed to the mounting member is suppressed, and mechanical damage of the semiconductor device due to thermal and mechanical changes during manufacturing or operation is prevented. Thus, it is possible to provide a semiconductor device with high manufacturing yield and high reliability, and an electronic device using the semiconductor device with high reliability.

[Brief description of the drawings]

FIG. 1 is a bird's-eye view and a cross-sectional view illustrating a semiconductor device according to the present invention.

FIG. 2 is a schematic sectional view of an IGBT chip and a mounting portion.

FIG. 3 is a depth profile of a metal in an IGBT chip and a mounting portion.

FIG. 4 is a depth profile of a metal in a IGBT chip for comparison and a mounting portion.

FIG. 5 is a graph showing a residual thickness when a metal layer comes into contact with a molten brazing material.

FIG. 6 is a graph showing transition of thermal resistance in a temperature cycle test of a semiconductor device.

FIG. 7 is a diagram illustrating a circuit of the semiconductor device according to one embodiment;

FIG. 8 is a diagram illustrating another example of the circuit of the semiconductor device.

FIG. 9 is a bird's-eye view of a semiconductor device according to another embodiment.

FIG. 10 is a cross-sectional view illustrating a form of a metal-bonded circuit board.

FIG. 11 is a schematic sectional view of a semiconductor substrate mounting portion.

FIG. 12 is a diagram illustrating a circuit configuration of a semiconductor device according to another embodiment.

FIG. 13 is a graph showing transition of thermal resistance by an intermittent current test.

FIG. 14 is a diagram illustrating a circuit of an inverter device incorporating a semiconductor device according to another embodiment.

FIG. 15 is a graph showing the relationship between the switching frequency and the heat generation temperature of the IGBT element base when the rotation speed of the electric motor is controlled using the inverter device.

FIG. 16 is a graph showing the efficiency of the electric motor.

FIG. 17 is a schematic sectional view of a semiconductor device according to another embodiment.

FIG. 18 is a block diagram showing the inside of a semiconductor device according to another embodiment.

FIG. 19 is a diagram showing a cross-sectional structure of a Zener diode as a semiconductor device according to another embodiment.

FIG. 20 is an example of another electric circuit built in a semiconductor device.

[Explanation of symbols]

1, 101, 101 ': semiconductor substrate, 1A: lowermost metal, 1B: Pt intermediate metal layer, 1C: outermost layer, 2: mounting member, circuit board, 3, 3,', 3 ": brazing material, 4 ... Thick film C
u wiring, 5 ... alumina ceramic substrate, 6, 6 ', 1
17: Al wire, 7, 7 ', 116, 116': terminal, 8: epoxy resin, 9: silicone resin adhesive, 1
0: control circuit, 11: thick film resistor, 12: IC chip base, 13: capacitor chip, 14: diode chip, 15: AlN sintered body, 15a, 15b, 15c, 1
5d: Cu plate, 30: semiconductor device, 60: gate drive circuit, 70: control unit, 125: support plate, 150
a, 150b, 150c, 150d: wax, 155: metal bonded circuit board, 201: Al plate, 202: epoxy insulating layer, 203: Cu wiring layer, 900: inverter device,
950: Electric motor.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshiaki Kaminaga 2477 Takaba, Hitachinaka-shi, Ibaraki Prefecture Inside Hitachi Car Engineering Co., Ltd. (72) Katsuaki Fukatsu 2477 Takaba, Hitachinaka-shi, Ibaraki Hitachi Car Engineering Co., Ltd. (72) Inventor Ryoichi Kobayashi 2520 Takahiro, Hitachinaka, Ibaraki Pref.Hitachi, Ltd.Automotive Equipment Division, Hitachi, Ltd. (72) Inventor Norihiro Kanai 2520 Odaikoba, Hitachinaka-City, Ibaraki Automobile, Hitachi, Ltd. Within the business division (72) Inventor Tsuneo Endo 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Co., Ltd.Semiconductor Division, Hitachi, Ltd. (72) Toshio Ogawa 7-1-1, Omikacho, Hitachi, Ibaraki, Japan F-term 5F047 AA in Hitachi, Ltd. Hitachi Laboratory 02 AA11 BA05 BA06 BA14 BA15 BA17 BA19 BB03 BC01 BC12 BC13

Claims (4)

[Claims] A semiconductor substrate and a member on which the semiconductor substrate is mounted are made of Sn, Sb, Ag, Cu, Ni, P, Bi, Zn, A
An adhesive structure in which at least one material selected from the group consisting of u and In is fixed by a brazing material made of Sn and the Pt layer provided on the surface to be fixed of the semiconductor substrate and the brazing material are directly fixed. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein said semiconductor substrate is fixed to a mounting member made of metal or a mounting member having an electrically insulating structure. 3. The semiconductor device according to claim 1, wherein the semiconductor substrate and a member on which the semiconductor substrate is mounted are sealed with a resin. 4. A semiconductor substrate and a member on which the semiconductor substrate is mounted are made of Sn, Sb, Ag, Cu, Ni, P, Bi, Zn, A
An adhesive structure in which at least one material selected from the group consisting of u and In is fixed by a brazing material made of Sn and the Pt layer provided on the surface to be fixed of the semiconductor substrate and the brazing material are directly fixed. An electronic device, wherein the semiconductor device has a built-in semiconductor device for supplying power to a load.