JP2001110959A - Semiconductor device and electronic device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device where a semiconductor substrate is stuck to a mounting member via a middle metal plate. SOLUTION: A semiconductor substrate, a middle metal plate, and a mounting member are stuck by a brazing material that is made of Sn and at least one type of substance selected from a group of Sn, Ag, Cu, Ni, P, Bi, Zn, Au, and In, and a thermal coefficient of expansion in a direction in parallel with the sticking surface of the middle metal plate and thermal conductivity are adjusted to 7-13.5 ppm/ deg.C and 150 W/m.K or higher, respectively, thus improving reliability for joining the semiconductor substrate to the placement member without losing a cooling property.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure in which a semiconductor element substrate is brazed on a mounting member via an intermediate metal plate, and an electronic device using the same.

[0002]

2. Description of the Related Art Heretofore, a member for supporting a semiconductor element substrate often also serves as one electrode of a non-insulated semiconductor device.
For example, a power transistor chip is mounted on a copper base with Pb
In a power transistor device mounted with -Sn solder material, a copper base (metal supporting member) also serves as a collector electrode and a supporting member of the transistor. In such a semiconductor device, a collector current of several amperes or more flows, and the transistor chip generates heat. In order to avoid instability of characteristics and deterioration of life due to the heat generation, the copper base also serves as a member for heat dissipation. Further, when a semiconductor element substrate having a high withstand voltage and a high frequency and capable of flowing a large current is directly soldered and mounted on the copper base, the role of the copper base as a heat dissipation relay member becomes more important.

In addition, a structure has emerged in which all electrodes of a semiconductor device are electrically insulated from a metal support member, thereby increasing the degree of freedom in circuit application of the semiconductor device. In such an insulated semiconductor device, all the electrodes are insulated from all the package members including the metal supporting member by the insulating member and are drawn out to the outside. Therefore, even in a usage example in which the pair of main electrodes is floating from the ground potential on the circuit, the package can be fixed to the ground potential portion regardless of the electrode potential, so that the semiconductor device can be easily mounted.

[0004] In an insulated semiconductor device, in order to operate a semiconductor element safely and stably, it is necessary to efficiently dissipate heat generated during operation of the semiconductor device to the outside of a package. This heat dissipation is usually achieved by transferring heat from the semiconductor substrate, which is a heat source, to the air through the members bonded thereto. In the insulation type semiconductor device, the heat transfer path includes an adhesive layer (brazing material or solder material) used for a portion for bonding the insulator, the semiconductor substrate, and the like.

Further, as the power handled by a circuit including a semiconductor device increases, or as the required reliability (eg, stability over time, moisture resistance, heat resistance, etc.) increases, complete insulation is required. The heat resistance referred to here includes not only the case where the ambient temperature of the semiconductor device rises due to an external factor, but also the heat resistance when the power handled by the semiconductor device is large and the heat generated in the semiconductor base is large.

On the other hand, in a hybrid integrated circuit device or a semiconductor module device, since a certain electric circuit including a semiconductor element is generally incorporated, at least a part of the circuit and a metal portion such as a support member or a heat radiation member of these devices are included. Must be electrically insulated. For example, the first
"MIST Substrate" by Kazami Akira as a prior art example: Industrial Materials (Vol. 30, No. 3), pp. 22-26 (198)
3 years), on one side of an aluminum plate (1-2 mm) with an alumite layer (14-30 μm) formed on both sides,
Copper foil (35μ) via epoxy-based insulating layer (28μm)
A substrate for a hybrid integrated circuit device formed with m) is disclosed. Also disclosed is a hybrid integrated circuit device in which a power semiconductor element and a passive element are mounted by soldering on the hybrid integrated circuit device substrate on which the copper foil is selectively etched and circuit wiring is provided.

As a second prior art example, “An Improvement on Solder Joint Reliability fo” by N. Sakamoto et al.
r Aluminum Based IMST Substrate ”: IMC 1992 Proceed
ings, pp. 525-532 (1992), a power transistor element, a ceramic capacitor, and a chip resistor are mounted on the above-mentioned substrate for a hybrid integrated circuit device using a Pb-60 wt% Sn-based solder material. Hybrid IC with structure sealed with epoxy resin having the same thermal expansion coefficient (25 ppm / ° C) as aluminum
An apparatus is disclosed.

The hybrid integrated circuit device and the hybrid IC device based on the first and second prior art examples are mechanically attached to a heat sink such as an aluminum fin or the like in order to promote heat radiation, or are provided with an external circuit. A printed circuit board or the like is used by being fixed by soldering.

In general, a semiconductor element substrate is bonded onto a mounting member with a brazing material having a relatively low melting point. For example, the third
JP-A-4-49630 as a prior art example discloses Sn-
There is disclosed an Sb-based brazing alloy, which contains both Ni, Cu and P, for assembling semiconductor devices. In this case, the mechanical strength of the brazing material itself is increased by adding Sb to Sn, and the formation of an intermetallic compound of Ni-Sn or Cu-Sn at the interface between the solder layer and the surface of the member to be bonded is prevented. It says that it is possible to improve the reliability of the semiconductor device because of the suppression.

Japanese Patent Publication No. Hei 3-3937 as a fourth prior art example discloses a semiconductor device in which a semiconductor element and a mounting member for supporting the semiconductor element are brazed with a brazing material. 87 to 92.4% tin and 7.0 to 1 by weight
A semiconductor device comprising 0.0% of antimony and 0.6 to 3.0% by weight of nickel is disclosed. According to this technique, it is said that the mechanical strength of the brazing material is high, the formation of an alloy of copper and tin is suppressed, and the reliability of the semiconductor device is improved.

A hybrid integrated circuit device or a hybrid IC device in which circuit elements are mounted using a brazing material based on the third and fourth prior art examples is an approach to environmental protection in recent years, that is, in accordance with the purpose of Pd-free soldering. Device.

[0012]

In the case of a hybrid integrated circuit device or a hybrid IC device (hereinafter referred to as a semiconductor device) based on the first and second prior art examples, a mounting component having a small coefficient of thermal expansion, for example, a semiconductor device Substrate: 3.5 ppm / ° C (S
i) is a circuit board having a large coefficient of thermal expansion (Al: 23 ppm /
C), and is fixed by brazing of a Pb-Sn alloy material. The brazing portion fixes the mounted component at a predetermined position on the substrate and plays a role of a wiring and a heat radiation path of the semiconductor device. However, the semiconductor device is repeatedly subjected to thermal stress during operation or at rest, which eventually leads to thermal fatigue failure of the brazed portion. In particular, when resin molding is required, if the coefficient of thermal expansion of the resin is not properly adjusted with respect to the substrate for a hybrid integrated circuit, an excessive residual stress will be present at the joint interface between them. When thermal stress during operation of the semiconductor device is superimposed on this, thermal fatigue fracture of the brazed portion is further accelerated. When the above-mentioned thermal fatigue fracture proceeds, adverse effects such as disconnection and interruption of the heat dissipation path occur. As a result, the semiconductor device loses its circuit function. Therefore the first
The problem of (1) is that a means for relaxing excessive stress based on a difference in thermal expansion coefficient between the semiconductor element substrate and the circuit board is required.

In the case where the amount of heat generated in the semiconductor device is small and the required reliability is not so high, there is no problem if the semiconductor substrate is mounted on any circuit board. However, when the heat generation is large and high reliability is required,
The structure of the part on which the semiconductor substrate is mounted must be appropriately selected. Circuit boards based on the first and second prior art examples have a cross-sectional structure in which copper foil wiring is formed on an aluminum plate via an epoxy insulating layer. When the semiconductor substrate as the heat source is directly mounted on the circuit board by brazing, the heat released from the semiconductor substrate is transferred to the outside via the brazing material layer, the copper foil wiring layer, the epoxy insulating layer, and the aluminum plate in order. Released. The heat dissipation when such a mounting structure is adopted is generally not so high. This is because an epoxy insulating layer having a low thermal conductivity is interposed in the heat radiation path. If the heat dissipation is not sufficient, the temperature of the semiconductor substrate during operation becomes higher and thermal runaway occurs, resulting in loss of circuit function as a semiconductor device due to overheating, destruction of the semiconductor substrate itself, disconnection or short circuit of the circuit, and epoxy insulating layer. Undesirable phenomena such as insulation deterioration occur. Therefore, a second problem is that a means for assisting heat transfer is required in a heat dissipation path between the semiconductor element substrate and the circuit board.

The present invention has been made in consideration of the above-described problems, and provides a semiconductor device capable of maintaining excellent reliability without impairing heat dissipation and an electronic device using the same.

[0015]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention comprises a semiconductor substrate, a mounting member having a wiring layer provided on a main surface of a metal plate via an insulating layer or a mounting member formed of a metal plate, and a semiconductor substrate. And an intermediate metal plate disposed between the mounting member and
at least one substance selected from the group consisting of n, Sb, Ag, Cu, Ni, P, Bi, Zn, Au and In;
n is fixed by a brazing material made of n, the coefficient of thermal expansion in the direction parallel to the fixing surface of the intermediate metal plate is adjusted to 7 to 13.5 ppm / ° C., and the thermal conductivity is adjusted to 150 W / m · K or more. And

An electronic device using a semiconductor device according to the present invention is a semiconductor substrate, a mounting member having a wiring layer provided on a main surface of a metal plate via an insulating layer, or a mounting member formed of a metal plate; The intermediate metal plate disposed between the mounting members is S
at least one substance selected from the group consisting of n, Sb, Ag, Cu, Ni, P, Bi, Zn, Au and In;
The semiconductor device is fixed by a brazing material made of n, and has a coefficient of thermal expansion of 7 to 13.5 ppm / ° C. and a thermal conductivity of 150 W / m · K or more in a direction parallel to the fixing surface of the intermediate metal plate. , And is incorporated in a device that supplies power to the load.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor device according to one embodiment of the present invention. The semiconductor device 30 according to the present invention includes an insulating layer 2 on one main surface of a metal plate (thickness: 0.8 to 5 mm) 201.
On the circuit board 2 on which the Cu wiring layer 203 is selectively formed through the semiconductor device substrate 02, the passive element including the resistor 11 as a chip resistor and the capacitor 13 as a chip capacitor, and the terminal 7, Sn, Sb, Ag, C
At least one material selected from the group consisting of u, Ni, P, Bi, Zn, Au, and In and a brazing material (thickness: 30 to 200 μm) made of Sn and electrically and mechanically fixed by a brazing material 3,31. The semiconductor element base 1 is mounted between the circuit board 2 and the circuit board 2 via an intermediate metal plate (thickness: 0.3 to 2 mm) 4 and is electrically connected to the Cu wiring layer 203 by bonding of Al wires 6. These mounted parts (reference numerals 1, 4,
11, 13, 7, 6, 3, 31) and the circuit board 2 are hermetically sealed with an epoxy resin 8 for molding.

FIG. 2 is a cross-sectional view for explaining an example of the intermediate metal plate 4 which is arranged and fixed between the semiconductor element base 1 and the circuit board 2. The intermediate metal plate 4 is formed by joining a second metal 42 on a plate in a sandwich shape to both surfaces of a first metal 41 in a plate shape. Here, the first metal 41 on the plate is for keeping the coefficient of thermal expansion in a direction parallel to the fixing surface of the intermediate metal plate 4 at a small value, and is made of invar (Fe-36 wt% Ni,
1.5 ppm / ° C.), 42 alloy (Fe-42 wt% Ni,
7ppm / ° C), Fernico (Fe-31wt% Ni-15)
wt% Co, 5 ppm / ° C), Mo (5 ppm / ° C), W (4p
pm / ° C.) and the like. On the other hand, the second metal 42 is for keeping the thermal conductivity in the direction parallel to the fixing surface of the intermediate metal plate 4 at a large value,
3W / m · K), Al (236W / m · K), bronze (1
A material having high thermal conductivity such as 80 W / m · K) and brass (106 W / m · K) is desirable. The thermal conductivity and the thermal expansion coefficient of the intermediate metal plate 4 are controlled by adjusting the thickness ratio between the first metal 41 and the second metal 42. For example, when the first metal 41 is an invar having a thickness of 0.2 mm and the second metal 42 on both sides is Cu having a thickness of 0.2 mm, the thermal conductivity is 262.
W / m · K and the coefficient of thermal expansion are 10.6 ppm / ° C. An integrated product of the first metal 41 and the second metal 42 is plated with Ni (thickness: 3 to 7 μm) 43. Ni plating 4
3 is provided to maintain the quality of the surface of the integrated product and to achieve defect-free brazing. Ni plating is Au, Ag
May be substituted. However, when the quality of the integrated product is managed in a good state, it is not essential to provide the plating 43.

FIG. 3 is a sectional view for explaining details of the mounting portion of the semiconductor element substrate 1. The semiconductor element substrate 1 has an epoxy resin insulating layer 2 on one main surface of a metal plate 201 made of Al.
02 on the circuit board 2 on which the Cu wiring layer 203 is selectively formed via Sn, Sb, Ag, Cu, Ni, P, Bi,
At least one selected from the group consisting of Zn, Au and In
It is conductively and mechanically fixed by a brazing material 3 and a brazing material 31 made of a seed material and Sn. At this time, the semiconductor element base 1 is mounted between the semiconductor element base 1 and the circuit board 2 via the intermediate metal plate 4 described with reference to FIG.

Here, the most important point of the semiconductor device of the present invention is that the intermediate metal plate 4 arranged and fixed between the semiconductor element substrate 1 and the circuit board 2 has an apparent parallel direction to the surface to be fixed. The thermal expansion coefficient is adjusted to 7 to 13.5 ppm / ° C. and the thermal conductivity is adjusted to 150 W / m · K or more.
FIG. 4 is a graph showing the thermal strain in the brazing material layers 31 and 3 at the portion where the semiconductor element substrate 1 is fixed on the circuit board 2 via the intermediate metal plate 4. Here, the graph is the result of a simulation, and represents the equivalent strain generated at the end of the brazing material layer when the strain at 150 ° C. was cooled from 0% to −55 ° C. The brazing material layer 31 has a composition of Sn-5.
wt% Sb material (thickness: 70 μm), and the brazing material layer 3 was composed of the composition Sn-3 wt% Ag-0.8 wt% Cu material (thickness: 7).
0 μm). A curve A in the drawing represents a distortion generated in a portion A in FIG. 3, and a curve B represents distortion generated in a B portion in FIG. The distortion of the portion A increases as the coefficient of thermal expansion of the intermediate metal plate 4 increases. In order to reduce the distortion of the portion A, it is advantageous that the intermediate metal plate 4 has a small coefficient of thermal expansion. On the other hand, the distortion of the portion B decreases as the coefficient of thermal expansion of the intermediate metal plate 4 increases. In order to reduce this distortion, it is advantageous that the thermal expansion coefficient of the intermediate metal plate 4 is large. Thus, part A and B
The strains of the portions are in a trade-off relationship with each other, and the two are balanced when the thermal expansion material is about 10 ppm / ° C.

FIG. 5 is a graph showing the Weibull distribution of the destruction life of the brazed portion of the semiconductor element substrate by the temperature cycle test. When Cu having a coefficient of thermal expansion of 16.5 ppm / ° C. is used as the intermediate metal plate, a life distribution of Mo (5 ppm / ° C.) with a shape parameter m = 3.0 and an average life μ = 1120 times is shown. In this case, the life is governed by the fracture of the brazing 31 by the brazing material due to cracks. The life at the -3σ level (cumulative failure rate = approximately 0.1%) in consideration of mass-produced products is as short as 120 times. In addition, M having a coefficient of thermal expansion of 5 ppm / ° C.
When o is used as the intermediate metal plate, the shape parameter m
= 5.5, average life μ = 800 times. In this case, the factor governing the life is crack fracture of the brazing material 3, and the -3σ level life is 240 times, which is better than that of Cu. However, in the case of Cu and Mo, the reliability cannot be said to have sufficient margin. The crack progress of the brazing material 31 when the coefficient of thermal expansion of the intermediate metal plate is too small, and the cracking of the brazing material 3 when the coefficient of thermal expansion is too large, are shown in FIG. Match. This implies that in order to ensure a long service life, the destruction of one of the brazing materials 31 or 3 should not proceed in advance. On the other hand, the coefficient of thermal expansion is 10.6 ppm / ° C.
In the semiconductor device 30 of the present invention using the intermediate metal plate 4 made of Cu (0.2 mm) -invar (0.2 mm) -Cu (0.2 mm) clad material, the shape parameter m = 5.3 and the average life μ = 4
The life distribution is dramatically improved to 300 times, and to the -3σ level life of 1300 times.

FIG. 6 is a graph showing a -3σ level life of a brazed portion of a semiconductor element substrate by a temperature cycle test.
On the side where the coefficient of thermal expansion is small, the breakage of the brazing material 3 due to cracks proceeds first, so that the life of the semiconductor device is shortened. In the range of 5 to about 10 ppm / ° C., the life increases as the coefficient of thermal expansion increases, and in the range of about 10 to 16.5 ppm / ° C., the life decreases as the coefficient of thermal expansion increases. In particular,
On the side where the coefficient of thermal expansion is large, the breakage of the brazing material 31 due to cracks proceeds first, so that the life of the semiconductor device is shortened. Under general operating conditions of a semiconductor device, the temperature cycle life is 1000 times or more (condition: −55 to 150).
C). The thermal expansion coefficient of the metal intermediate plate 4 selected from such a viewpoint is in the range of 7 to 13.5 ppm / ° C.

In the present invention, a wiring layer 203 made of Cu is selectively formed on one main surface of a metal plate 201 such as Al via an insulating layer 202 made of an epoxy resin. It is mounted on the circuit board 2 by soldering. In the heat radiation path from the semiconductor element base 1 to the metal plate 201, the epoxy insulating layer 202 most hinders heat radiation. In this case, the quality of the heat dissipation property of the semiconductor device depends on how to spread the heat flow in the path from the semiconductor base to the epoxy insulating layer. FIG. 7 is a graph showing the temperature rise of the semiconductor element base when power is applied to the semiconductor device. This graph is the result of a simulation. The power consumption of the semiconductor element substrate 1 is 10 W, the surface of the semiconductor element substrate 1 is insulated, and the surface of the metal plate 201 made of Al as a heat radiation surface is kept at 0 ° C. I assume. The rising temperature of the semiconductor element base 1 tends to decrease as the thermal conductivity in the direction parallel to the fixing surface of the metal intermediate plate 4 increases. The temperature for maintaining the stable operation of the semiconductor element substrate 1 is considered to be about 125 ° C. Further, it is desirable that the semiconductor device can maintain a stable operation under as high an ambient temperature as possible (the temperature of the metal plate 201 made of Al). In order to operate stably at an ambient temperature of 90 ° C., referring to the graph, it is necessary that the thermal conductivity of the metal intermediate plate is adjusted to 150 W / m · K or more. Metal intermediate plate 4 selected from such a viewpoint
Has a thermal conductivity of 150 W / m · K or more.

The circuit board 2 described above is
A Cu wiring layer 203 is selectively formed on one main surface of an Al metal plate 201 via an epoxy resin insulating layer 202. However, the circuit board 2 in the present invention
The present invention is not limited to the configuration in which the wiring layer 203 is provided on the metal plate 201 made of Al with the insulating layer 202 interposed therebetween.
The first reason is that even when the semiconductor element substrate 1 is directly brazed and mounted on the metal plate 201 made of Al without the epoxy resin insulating layer 202 and the Cu wiring layer 203, the same as in the first and second prior art examples. However, it is the same in that a component having a low coefficient of thermal expansion is brazed to a circuit board having a high coefficient of thermal expansion, and therefore has a similar problem. The second reason is that even when the semiconductor element substrate 1 is brazed and mounted on the metal plate 201 made of Al via the metal intermediate plate 4, the case of the circuit board 2 provided with the insulating layer 202 and the wiring layer 203 is different from that of the circuit board 2. This is because a similar improvement in reliability can be achieved. Therefore, in the present invention, the base plate 2 on which no circuit is formed as in a third embodiment described later is also included in the range of the circuit board 2.

As described above, an important point in the present invention is that the coefficient of thermal expansion of the intermediate metal plate 4 fixed between the semiconductor element substrate 1 and the circuit board 2 in the direction parallel to the surface to be fixed is 7 to 7 or more.
13.5 ppm / ° C and the thermal conductivity is adjusted to 150 W / m · K or more. The material that can satisfy such a condition is not limited to a material in which the second metal 42 is joined in a sandwich shape to both surfaces of the first metal 41 as shown in FIG.

FIG. 8 is a sectional view for explaining an alternative material for the intermediate metal plate. (A) shows a structure in which two assemblies in which invar as the first metal 41 and Cu as the second metal 42 are alternately joined in a stripe shape are arranged and joined so that the stripe directions are perpendicular to each other. is there. In this case, the thermal expansion coefficient and the thermal conductivity are determined by the first metal 41 and the second metal 42.
Is adjusted by the ratio of the arrangement amount, the number of overlapping assemblies, and the thickness. From this viewpoint, the number of assemblies may be one, or two or more. (B) shows a state in which invar grains as the first metal 41 are dispersed in a Cu matrix as the second metal 42. In this case, the coefficient of thermal expansion and the coefficient of thermal conductivity are adjusted by the compounding ratio of the first metal 41 and the second metal 42, the thickness, and the like. (C) shows a state in which a mixture of Mo particles as the first metal 41 and Cu particles as the second metal 42 is sintered. In this case, the coefficient of thermal expansion and the coefficient of thermal conductivity are also adjusted by the mixing ratio of the first metal 41 and the second metal 42, the thickness, and the like. The first metal 41 in (a) to (c) above is for keeping the coefficient of thermal expansion of the intermediate metal plate 4 at a small value, and is made of invar (Fe-36 wt% Ni,
1.5 ppm / ° C.), 42 alloy (Fe-42 wt% Ni,
7ppm / ° C), Fernico (Fe-31wt% Ni-15)
wt% Co, 5 ppm / ° C), Mo (5 ppm / ° C), W (4p
pm / ° C) or the like. The second metal 42 is for keeping the thermal conductivity of the intermediate metal plate 4 at a large value,
(403 W / m · K), Al (236 W / m · K), bronze (180 W / m · K), brass (106 W / m · K), and the like. (D) is a state where SiC powder 41 ′ having the same role as the first metal 41 is dispersed in an Al matrix as the second metal 42. In this case, the coefficient of thermal expansion and the coefficient of thermal conductivity are adjusted by the compounding ratio of the SiC powder 41 ′ and the second metal 42. (E) shows a SiC fiber cloth 41 ″ having the same role as the first metal 41,
2 in a state embedded in a Cu matrix. In this case, the coefficient of thermal expansion and the coefficient of thermal conductivity are adjusted by the compounding ratio of the SiC fiber cloth 41 ″ and the second metal 42. In the above (d) and (e), the second metal 42 is used.
Cu (403 W / mK) and Al (236 W /
m · K) can be used. SiC powder 41 'or SiC fiber cloth 41 "having the same role as the first metal 41.
Can be replaced with a material composed of carbon, aluminum nitride, alumina, and silicon nitride. In the above (a) to (e), the Ni plating 43 is applied to all. This may be replaced by Au or Ag. However, when the quality is managed in a good state, it is not essential to provide the plating 43.

Table 1 shows examples of physical property values of various alternative materials as the intermediate metal plate. The thermal expansion coefficient and the thermal conductivity listed here are values in a direction parallel to the surface to which the intermediate metal plate 4 is fixed.
Each material has a thermal expansion coefficient (7-1 to 1) which is essential in the present invention.
3.5ppm / ° C) and thermal conductivity (150W / mK or more)
Has been adjusted.

[0029]

[Table 1]

The semiconductor device 30 according to the present invention includes the metal plate 2
On a circuit board 2 on which a wiring layer 203 is selectively formed on one main surface of the semiconductor device 1 via an epoxy resin insulating layer 202, the semiconductor element substrate 1 is provided with Sn, Sb, A via an intermediate metal plate 4.
At least one material selected from the group consisting of g, Cu, Ni, P, Bi, Zn, Au and In is electrically and mechanically fixed by a brazing material 3 and 31 made of Sn. Specific brazing materials 3 and 31 include Sn simple metal,
Sn-5 wt% Sb-0.6 wt% Ni-0.05 wt%
Sn or Sn-S represented by Sn-5wt% Sb
b type, Sn-3.5 wt% Ag, Sn-3 wt% Ag-
Sn-Ag based such as represented by 0.8 wt% Cu, S
Sn-Bi system represented by n-58 wt% Bi, Sn-C represented by Sn-0.7 wt% Cu
u-based, Sn- as represented by Sn-52wt% In
In-based, Sn- as represented by Sn-9 wt% Zn
Zn-based, In-10 represented by In-10 wt% Ag
It is possible to apply an Ag-based material and an Au-Sn-based material typified by Au-20wt% Sn.

The semiconductor element substrate 1 includes IGBTs, transistors, thyristors, diodes, MOSFET transistors, etc.
They may have different electrical functions. The semiconductor element substrate 1 is made of Si (4.2 ppm / ° C.) or a material other than Si (Ge: 5.8 ppm / ° C., GaAs: 6.5 ppm / ° C.,
The same effect can be obtained even in the case of GaP: 5.3 ppm / ° C., SiC: 3.5 ppm / ° C.).

Semiconductor element base 1 as mounting element, resistor 1
1, a molding resin 8 for sealing the capacitor 13 and the circuit board 2, which is a component, an intermediate metal plate 4, a terminal 7, etc., is made of SiO ₂ (fused silica, crystalline silica) or ZnO as a filler.
A phenol-curable epoxy resin to which a powder is added is often used. In this case, it is possible to select an arbitrary composition of the filler in the range of 50 to 90% depending on the desired coefficient of thermal expansion and the mold processing temperature. Further, a rubber-modified epoxy resin may be used. The encapsulation with resin is preferably performed by a transfer molding method from the viewpoint of productivity and economy. However, as long as desired water resistance, electrical performance, reliability, and the like are satisfied, sealing can be performed by a potting method.

The above configuration will be described with reference to the drawings.

[Embodiment 1] In this embodiment, a semiconductor device in which a MOSFET power semiconductor element substrate is incorporated and an electronic device using this semiconductor device will be described.

FIG. 9 is a plan view, a sectional view, and a circuit diagram illustrating a semiconductor device 30 according to an embodiment of the present invention. A MOSFET chip (four pieces, chip size: 7 × 7 × 0.28 mm) made of Si as the semiconductor element substrate 1 has a size of 8 × 8 × 0.2 mm.
It is mounted on a circuit board 2 which is an Al insulated circuit board by a brazing material 31 via a 6 mm intermediate metal plate 4. The intermediate metal plate 4 is a clad material in which Cu (each thickness: 0.2 mm) as a second metal 42 is sandwiched on both sides of an invar (thickness: 0.2 mm) as a first metal 41 in a sandwich manner. Ni plating (thickness: 3-7 μm) 43
Is given. The circuit board 2 is an Al plate as a metal plate
(Size: 40.7 × 29.4 × 1.5 mm) Epoxy resin insulating layer (thickness: 150 μm) 202 on one main surface of 201
, A Cu wiring layer (thickness: 70 μm) 203 is selectively formed. The MOSFET chip 101 and the intermediate metal plate 4 are made of a brazing material (thickness: 70 μm, temperature:
270 ± 10 ° C.) 3 and the intermediate metal plate 4 and the circuit board 2 are brazed with a brazing material (thickness 70 μm, temperature: 240 ± 10 ° C.) 3 of composition Sn-3 wt% Ag-0.8 wt% Cu. Have been. The Cu wiring layer 20
A resistor 11, which is a chip resistor, is fixed between the three by a brazing material 3. The brazing is performed in a process in which a paste-like brazing material is applied to a predetermined portion, necessary members are mounted on the application portion, and then heated in the air. Then
The case 20 in which the frame 21 made of epoxy resin and the terminal 7 made of Cu were integrated was attached to the circuit board 2 with a silicone resin adhesive (not shown) 25. The gate, source, and drain of the MOSFET chip 101 were each subjected to wire bonding of an Al wire (diameter: 300 μm) 6. The gate terminal 7a is shared by each MOSFET chip 101, and the source terminal 7c and the drain terminal 7b are wired so as to be dedicated to each MOSFET chip 101. Although not shown, an epoxy resin 8b is potted on the mounting portion of the resistor 11, which is a chip resistor, and a silicone gel resin 8a is potted on the mounting portion of the MOSFET chip 101, and heat treatment is performed at 150 ° C. for 2 hours. Applied and cured. Finally, a case lid (not shown) made of epoxy resin 22
To complete the semiconductor device 30. As a result, the MOSFET chip 101, the resistor 11, the circuit board 2, and the like, which are mounted elements, are hermetically sealed with the mold resins 8a and 8b.

The semiconductor device 30 of the present embodiment manufactured as described above constitutes the circuit shown in FIG.

FIG. 10 is a graph showing the transient thermal resistance characteristics of the semiconductor device 30 of this embodiment. The thermal resistance takes a higher value as the energizing time increases, but shows a steady value (about 2.7 ° C./W) after the energizing time of about 3 s. This value means that the chip 101 can operate stably even when the MOSFET chip 101 consumes 10 W of power under the condition of an ambient temperature: 98 ° C.

FIG. 11 shows a typical semiconductor device 30 of this embodiment.
3 shows the transition of the thermal resistance by the temperature cycle test. The number of temperature cycles: Up to 2000 times, the same thermal resistance (about 2.7 ° C./W) as the initial value is maintained. The increase in thermal resistance occurs after the number of temperature cycles: 2000 times. If the number of temperature cycles when 1.5 times the initial value is reached is defined as the life, the life of the semiconductor device 30 of this embodiment is about 5000 times. The life of the semiconductor device 30 of the present embodiment obtained as described above has a distribution statistically represented by a straight line C in FIG. The −3σ level life obtained from the straight line C is 1300 times (−55 to 150 ° C.), indicating that the semiconductor device 30 of the present example has sufficient reliability as a mass-produced product. In the semiconductor device 30 of the present embodiment, the coefficient of thermal expansion of the metal intermediate plate 4 is adjusted to a preferable range of 10.6 ppm / ° C. (7-13.5 ppm / ° C.). This suppresses premature breakage of either the brazing material 31 or the brazing material 3 made of the brazing material layer, and contributes to prolonging the life of the semiconductor device as a whole.

FIG. 12 is a block diagram for explaining a power supply circuit device 90 as an electronic device in which the semiconductor device 30 of this embodiment is incorporated. The power supply circuit device 90 rectifies AC power and supplies voltage-controlled power to a load circuit. Here, the load circuit in this embodiment is an arithmetic circuit of a computer.

[Embodiment 2] In this embodiment, a semiconductor device in which a power semiconductor element substrate is mounted on a mounting member in which circuit wiring is formed on an Al plate and an electronic device using this semiconductor device will be described.

FIG. 1 is a schematic sectional view of a semiconductor device 30 according to this embodiment. The semiconductor device 30 includes a metal plate 2 made of Al.
01 (dimensions: 20.5 × 38 × 1.5 mm) on one main surface via an epoxy resin insulating layer 202 (thickness: 80 μm).
On the circuit board 2 as a mounting member on which the u wiring layer 203 (thickness: 70 μm) is selectively formed, a passive element including a resistor 11 as a chip resistor and a capacitor 13 as a chip capacitor and a terminal 7 made of phosphor bronze. Has the composition Sn-5
It is electrically and mechanically fixed by a brazing material 3 (thickness: 50 to 100 μm) of wt% Sb. On the circuit board 2, a semiconductor element substrate 1 (size: 5 × 5 × 0.25 mm), which is a power MOSFET, is brazed by a brazing material having a composition of Sn-5 wt% Sb via an intermediate metal plate 4.
(Thickness: 50-100 μm) and brazing material 3 (thickness: 50
１００100 μm) so as to be electrically and mechanically fixed. The intermediate metal plate 4 is sandwiched on both sides of an invar (thickness: 0.2 mm) serving as a first metal 41 in the form of a second metal 42.
Is a clad material joined with Cu (each thickness: 0.2 mm), and the surface thereof is plated with Ni (thickness: 3 to 7 μm) 43. Between the semiconductor element substrate 1 and the Cu wiring layer 203 Are formed with an Al wire 6 having a diameter of 300 μm by ultrasonic bonding.
1, 13, 7), brazing material 3, Al wire 6, and circuit board 2
Is an epoxy resin 8 adjusted to a thermal expansion coefficient of 16 ppm / ° C.
Is hermetically sealed by the transfer mold.

FIG. 13 is a block diagram showing the inside of the semiconductor device 30 of this embodiment. The semiconductor device 30 includes a gate drive circuit 60 for driving the semiconductor element substrate 1 which is a MOSFET, and a control unit 70 for controlling the gate drive circuit 60. Further, the semiconductor device 30 employs a resonance power control IC,
It houses a semiconductor element substrate 1 which is a 0V power MOSFET transistor, and is suitable for a compact, high-efficiency, low-noise resonance type power supply device, particularly for a resonance type AC / DC converter power supply. In the case of the resonance type AC / DC converter, a performance with an efficiency of 90% or more is obtained at a switching frequency of 0.5 GHz. These are (1) overcurrent overvoltage protection function, (2) overheat protection function, (3) gate drive circuit,
This is based on the fact that (4) a soft start function and (5) two power MOSFET transistors with uniform characteristics are built in.

In the semiconductor device 30 of the present embodiment, the coefficient of thermal expansion of the intermediate metal plate 4 is adjusted to a preferable range of 10.6 ppm / ° C. (7-13.5 ppm / ° C.). This suppresses premature breakage of either the brazing material 31 or the brazing material 3, and contributes to extending the life of the semiconductor device as a whole.

[Embodiment 3] In this embodiment, a semiconductor device equipped with a power semiconductor element base and a control circuit for controlling its electric operation and an electronic device as an automobile ignition device using this semiconductor device will be described. .

A semiconductor device 30 mounted with a semiconductor element substrate 1 and a control circuit 10 for controlling its electric operation is shown in FIG.
Has a bird's-eye view structure and a cross-sectional structure shown in FIG. IGBT chip base 1 made of Si (chip size: 5 × 5 × 0.
25 mm) is an intermediate metal plate (size: 6 × 6) on a circuit board 2 which is an Al base plate having a thickness of 1 mm and an area of about 25 × 20 mm.
× 0.6 mm) 4 through the composition Sn-5 wt% Sb-0.
Brazing (thickness: 200 μm, temperature: 270 ± 10 ° C.) 31 with brazing material of 6 wt% Ni-0.05 wt% P and brazing material of composition Sn-3 wt% Ag-0.8 wt% Cu (thickness: 200 μm) , Temperature: 240 ± 10 ° C.) 3. The intermediate metal plate 4 is a clad material in which Cu (each thickness: 0.2 mm) as a second metal 42 is sandwiched on both sides of an invar (thickness: 0.2 mm) as a first metal 41 on both surfaces. Ni plating (thickness: 3-7 μm)
43 is given. Also, Ni plating (thickness: 3 to 7 μm) 43 is provided on the surface of the circuit board 2 which is an Al base plate.
Is given.

On the other hand, a Cu wiring layer (not shown) 203 having a thickness of about 15 μm, a resistor 11 which is a thick film resistor, and an overcoat glass layer (not shown) are provided.
A 0.8 mm alumina ceramic substrate 5 was prepared.
Next, in a desired region of the alumina ceramic substrate 5, a composition Sn-3wt% Ag-
A paste containing 0.8 wt% Cu brazing filler metal powder is printed, and the printed portion has an IC chip substrate 12 and a capacitor 1.
3. Then, chip components such as a diode 14 which is a glass sleeve type Zener diode chip were mounted and heated to 250 ± 10 ° C. in air. Thus, each chip component (symbols 12, 13, and 14) and the resistor 11 are electrically connected to the Cu wiring layer 203 by the brazing material layer 3 ', and the semiconductor element substrate 1 as an IGBT chip is formed on the alumina ceramic substrate 5. A control circuit 10 for controlling the operation of (1) is formed.
The alumina ceramic substrate 5 is coated with a circuit board 2 which is an Al base plate by a silicone resin adhesive (not shown) 9.
Mounted on top. The emitter electrode and the gate electrode of the semiconductor element substrate 1 which is an IGBT chip have a diameter of 300.
It is electrically connected to the control circuit 10 by a μm Al wire 6. The collector electrode of the semiconductor element substrate 1 that is an IGBT chip is composed of a circuit board 2 that is an Al base plate and an Al wire 6.
And is electrically connected to the terminal 7 via. The control circuit 10 is also electrically connected to the terminal 7 by the Al wire 6 '. The terminals 7 are made of the same material as the circuit board 2 which is an Al base plate, and the surface thereof is plated with Ni (not shown, thickness: 3 to 7 μm).

The assembly having the above schematic structure is as follows:
As shown by the broken line in the cross-sectional view shown in (b), the mounting portion of the semiconductor element substrate 1 which is an IGBT chip, the mounting portion of the alumina ceramic substrate 5 to which the chip components are attached,
In order to completely seal the wires 6 and 6 ′, transfer molding is performed with an epoxy resin 8 including a part of the terminal 7 and the circuit board 2 which is an Al base plate. Epoxy resin 8 has a thermal expansion coefficient of 16 ppm / ° C. and a glass transition point of:
155 ° C., volume resistivity: 9 × 10 ¹⁵ Ω · m (RT), flexural strength: volume resistivity: 3 × 10 ¹⁵ kgf / mm ² , flexural modulus:
It has a characteristic of 1600 kgf / mm ² . The transfer mold was performed at 180 ° C., and then subjected to a heat treatment at 150 ° C. for 2 hours to accelerate the curing of the resin.

FIG. 15 shows a change in thermal resistance of a semiconductor device in a temperature cycle test. A curve A in the figure is a semiconductor device 30 of this embodiment, and a curve B is a semiconductor device for comparison (M
o applied intermediate metal plate). The thermal resistance of the semiconductor device 30 of the present embodiment is determined by the number of temperature cycles:
The initial value (approximately 1.1 ° C./W) is maintained in the test up to 5000 times. As described above, it is confirmed that the semiconductor device 30 of this example has excellent reliability. 50
After the test up to 00 times, the brazing portion of the IGBT chip was examined, and it was confirmed that no breakage occurred in any of the brazing material 31 and the brazing material 3 by the brazing material layer. This is because the thermal expansion coefficient of the intermediate metal plate 4 is adjusted to a preferable thermal expansion coefficient range of 10.6 ppm / ° C. (7-13.5 ppm / ° C.). This is based on the fact that the destruction of either one of the above is suppressed and the life of the semiconductor device as a whole is prolonged. On the other hand, in the case of the comparative semiconductor device, the number of temperature cycles: 10
Exceeding zero causes an increase in thermal resistance. This means that the brazing portion of the IGBT chip has been broken to inhibit thermal conductivity. As a result of disassembling the comparative semiconductor device after the test and examining the brazed portion of the IGBT chip, it was confirmed that destruction occurred in the brazing material 3.

The initial value of the thermal resistance of the semiconductor device 30 of this embodiment is about 1.1 ° C./W. This value depends on the ambient temperature:
This means that the IGBT chip can operate stably even when the IGBT chip consumes 10 W of power under the condition of 114 ° C. Such excellent heat dissipation means that stable performance can be maintained even when the semiconductor device 30 is mounted in a severe temperature condition such as an engine room, and is particularly preferable as a semiconductor device for automobiles.

FIG. 16 is a diagram for explaining the circuit of the semiconductor device 30 of this embodiment. The emitter and the gate of the semiconductor element substrate 1 which is an IGBT element are electrically connected to a control circuit 10, and the operation of the semiconductor element substrate 1 is controlled by the control circuit 10. The control circuit 10 includes a resistor 11, an IC chip base 12, and a capacitor 13, and these elements are connected by a Cu wiring layer 203. Terminals 7 are respectively drawn from the semiconductor element substrate 1 which is an IGBT and the control circuit 10. The semiconductor device 30 comprises a semiconductor element base 1 which is an IGBT element and a control circuit 10 for controlling the same.
It comprises an element 1 and a control circuit 10 for controlling the element 1,
It is used to supply power to the coil of the engine ignition device for automobiles. FIG. 17 is used to supply power to the coil of the vehicle engine ignition device in the same manner as the circuit of FIG.
13 is an example of another semiconductor device. The control circuit in this case includes
A surge protection element 13A and a diode 14 are also mounted. The semiconductor device 30 composed of these circuits was used to ignite an automobile engine under an environment having a maximum ambient temperature of 110 ° C. It has been confirmed that the semiconductor device 30 of the present embodiment maintains its circuit function even when the vehicle travels for 100,000 kilometers.

Embodiment 4 In this embodiment, a semiconductor device for a DC / DC converter incorporating a MOSFET power semiconductor element substrate and an electronic device as a DC / DC converter using this semiconductor device will be described.

In this embodiment, a semiconductor device 30 for a DC / DC converter is a semiconductor device
SFET chip 101 (8 pieces, chip size: 9 x 9 x 0.
28mm) is an intermediate metal plate 4 of size 10 × 10 × 0.6mm.
3 on the circuit board 2 which is a circuit board through
1, the brazing material 3. The intermediate metal plate 4
Cu (as each thickness: 0.2 mm) as a second metal 42 is sandwiched on both sides of an invar (thickness: 0.2 mm) as a first metal 41.
0.2 mm), and the surface thereof is plated with Ni (thickness: 3 to 7 μm) 43. The circuit board 2, which is a circuit board, has a Cu wiring layer (thickness: 150 μm) 202 on one main surface of an Al plate (size: 68 × 46 × 1.5 mm) as a metal plate 201 via an epoxy resin insulating layer (thickness: 150 μm). (Thickness: 70 μm) 203 is selectively formed. MO
The semiconductor element substrate 1 as an SFET chip and the intermediate metal plate 4 are brazed by a brazing material (thickness: 70 μm, temperature: 270 ± 10 ° C.) having a composition of Sn-5 wt% Sb, and are insulated from the intermediate metal plate 4 by Al. The circuit board 2, which is a circuit board, is brazed by a brazing material (thickness: 70 μm, temperature: 240 ± 10 ° C.) 3 having a composition of Sn-3 wt% Ag-0.8 wt% Cu. Next, the epoxy resin frame 2
1 and a terminal 7 made of Cu are integrated with a circuit board 2 which is a circuit board.
Mounted by The gate, source, and drain of the semiconductor element substrate 1, which is a MOSFET chip, were each subjected to Al wire (diameter: 300 μm) 6 wire bonding. Further, a silicone gel resin 8a is applied by potting to a mounting portion of the semiconductor element substrate 1 which is a MOSFET chip,
It was cured by applying a heat treatment at 150 ° C. × 2 h. Finally, the semiconductor device 30 was completed by attaching the case lid 22 made of epoxy resin.

The semiconductor device 30 of the present embodiment manufactured as described above constitutes a circuit shown in FIG. The gate terminal 7a is provided exclusively for each semiconductor element substrate 1 as each MOSFET chip, and the source terminal 7c, the input terminal 7A, and the output terminal 7B are wired so as to be shared between the semiconductor element substrates 1 as each MOSFET chip. Have been.

One MOSFET of the semiconductor device 30 of this embodiment
The steady thermal resistance per semiconductor element substrate as a chip is
It was about 1.5 ° C / W. This value is the ambient temperature: 110
The semiconductor element substrate 1 which is a MOSFET chip under the condition of
This means that the MOSFET chip 1 can operate stably even when the power of 0 W is consumed.

The transition of the thermal resistance of the semiconductor device 30 of the present embodiment by the temperature cycle test (−55 to 150 ° C.) was traced. Temperature cycle number: Up to 5000 times, the same thermal resistance (about 1.5 C / W) as the initial value was maintained. In the semiconductor device 30 of this embodiment, the thermal expansion coefficient of the intermediate metal plate 4 is 10.6 p.
Since the thermal expansion coefficient is adjusted to a preferable range of pm / ° C. (7-13.5 ppm / ° C.), any of the brazing material 31 and the brazing material 3 by the brazing material layer is prevented from being prematurely destroyed. The overall life is extended.

FIG. 19 is a block diagram for explaining an electronic device 90 as a DC / DC converter in which the semiconductor device 30 of the present embodiment is incorporated. The electronic device 90, which is a DC / DC converter, includes a semiconductor device 30, a control circuit 10A for driving the semiconductor device 30, and a transformer 8 according to the present embodiment.
1, a rectifier circuit 82, and a smoothing and control circuit 83 are incorporated.
5 and this power is ultimately sent to the load circuit 86. Here, the load circuit is, for example, a lighting device, a wiper,
Motors as power sources for windows, air conditioners, etc., engine ignition devices, sensors, etc. The electronic device 90, which is a DC / DC converter device described above, was mounted on an automobile, and its performance was confirmed under operating conditions corresponding to a running distance of 100,000 kilometers. As a result, it was confirmed that the semiconductor device 30 of the present example and the electronic device 90 as the converter device maintained their intended circuit functions even after traveling 100,000 km.

[Embodiment 5] In this embodiment, a semiconductor device equipped with a power semiconductor element base and a control circuit for controlling the electrical operation thereof, and an electronic device as an automobile ignition device using this semiconductor device will be described. .

The semiconductor device 30 of this embodiment has basically the same configuration as the semiconductor device described in the third embodiment (see FIGS. 14, 16 and 17). Therefore, only the changed points are described below.

Intermediate metal plate (size: 6 × 6 × 0.6 mm) 4
Is made of the material shown in Table 1, and its surface is subjected to Ni plating (thickness: 3 to 7 μm) 43. IGBT
Semiconductor element substrate 1 which is a chip substrate (chip size: 5
× 5 × 0.25mm) is 1mm thick and about 25 × 20mm in area
Of a composition Sn-5wt on a circuit board 2 which is an Al base plate of the above through an intermediate metal plate (size: 6 × 6 × 0.6 mm) 4
% Sb-0.6 wt% Ni-0.05 wt% P brazing material (thickness: 200 μm, temperature: 270 ± 10 ° C.) 31 and a brazing material of composition Sn-3 wt% Ag-0.8 wt% Cu : 200 μm, temperature: 240 ± 10 ° C.) 3. The surface of the circuit board 2 which is an Al base plate is plated with Ni (thickness: 3 to 7 μm) 43. Further, an alumina ceramics substrate 5 on which a control circuit 10 similar to that of the third embodiment is formed is mounted on a circuit board 2 which is an Al base plate with a silicone resin adhesive 9, and predetermined wiring and resin molding are performed. The semiconductor device 30 was obtained.

Table 2 shows the performance of the semiconductor device 30 of this embodiment. Thermal resistance is 0.8-1.7 ° C / W. They are,
Ambient temperature: This means that the IGBT chip can operate stably even when the semiconductor element substrate 1 as the IGBT chip consumes 10 W of power at a temperature higher than 108 ° C. Such excellent heat dissipation means that stable performance can be maintained even when the semiconductor device 30 is mounted in a severe temperature condition such as an engine room, and is particularly preferable as a semiconductor device for automobiles. Further, in the test up to the number of temperature cycles: 5000, no increase in the thermal resistance occurred in each sample. This is because the intermediate metal plate 4 has a preferable coefficient of thermal expansion as shown in Table 2 (7-13.5p).
(pm / ° C.), so that the pre-breakage of either the brazing material 31 or the brazing material 3 by the brazing material layer is suppressed, and the life of the semiconductor device as a whole is extended.

[0061]

[Table 2]

The semiconductor device 30 of this embodiment comprises a semiconductor element base 1 which is an IGBT element and a control circuit 10 for controlling the same. The circuit has the circuit shown in FIG. Used to supply power.
This semiconductor device 30 was used to ignite an automobile engine in an environment having a maximum ambient temperature of 110 ° C. It has been confirmed that the semiconductor device 30 of the present embodiment maintains its circuit function even when the vehicle travels for 100,000 kilometers.

The embodiments of the present invention have been described above. The semiconductor device 30 in the present invention is not limited to the range described in the embodiment.

For example, the semiconductor device 30 according to the present invention may be expanded to a device constituting a circuit shown in FIG.
In this case, the semiconductor device 30 is a motor 950 shown in FIG.
Is incorporated in an electronic device 90 which is an inverter device for controlling the number of revolutions. The electronic device 90, which is an inverter device, is an electronic device according to the present invention, and is incorporated into an electric vehicle together with the electric motor 950 as a power source thereof. In this vehicle, the driving mechanism from the power source to the wheels can be simplified, so that the shock at the time of shifting is reduced as compared with a conventional vehicle that is irregular due to a difference in the gear engagement ratio.
Furthermore, this car can run smoothly in the range of 0 to 259 km / h, and in terms of vibration and noise generated by a power source, it is about half that of a car equipped with a conventional cylinder engine. Can be reduced. The electronic device 90, which is an inverter device incorporating the semiconductor device 30 of the present invention, is incorporated in a cooling / heating machine (power consumption during cooling: 5 kW, power consumption during heating: 3 kW, power supply voltage: 200 V) together with a brushless DC motor. You may. In this case, it is possible to obtain high energy efficiency, which is useful for reducing power consumption when using the air conditioner / heater. Also, the time from when the indoor temperature reaches the set temperature until the operation starts,
It can be reduced to about １ ／ compared to the case where an AC motor is used.

The same effect can be obtained even when the semiconductor device 30 is incorporated in a device for stirring or flowing another fluid, for example, a washing machine, a fluid circulation device, or the like.

In the present invention, the semiconductor device is used by being incorporated in an electric circuit for supplying power to a load. On this occasion,
(1) A semiconductor device is incorporated in an electric circuit for supplying power to a rotating device to control the rotation speed of the rotating device, or to move the system itself (for example, a train,
(Elevator, escalator, belt conveyor) together with the rotating device to control the moving speed of the moving system; (2) when the electric circuit for feeding the rotating device is an inverter circuit; (4) When the semiconductor device is incorporated in a device for processing an object and the grinding speed of the workpiece is controlled, the semiconductor device is incorporated in a device for agitating or flowing the object to control the moving speed of the object to be stirred or the fluid. (5) When the semiconductor device is incorporated in a light emitting body to control the amount of light emitted from the light emitting body; and (6) When the semiconductor device has an output frequency of 50 Hz to 3 Hz.
Even when operating at 0 kHz, the same effects and advantages as those of the above embodiment can be obtained.

In the present invention, the electric circuit of the semiconductor device is not limited to those described in the embodiments. For example, as shown in FIG. 22, the provision of various electric circuits inside the semiconductor device does not hinder the use of these circuits in an electronic device. At this time, it is also preferable that a passive element is incorporated in an electric circuit inside the semiconductor device.

[0068]

According to the present invention, the stress at the portion where the semiconductor substrate is fixed to the mounting member is relieved and the heat dissipation is improved, so that damage to the semiconductor device due to thermal and mechanical changes during operation is prevented. It is possible to provide a semiconductor device capable of preventing the occurrence and maintaining excellent reliability without deteriorating heat dissipation, and an electronic device using the same.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating an example of an intermediate metal plate arranged and fixed between a semiconductor element substrate and a circuit board.

FIG. 3 is a cross-sectional view illustrating details of a mounting portion of the semiconductor element substrate 1.

FIG. 4 is a graph showing a thermal strain in a brazing material layer at a portion where a semiconductor element substrate is fixed on a circuit board via an intermediate metal plate.

FIG. 5 is a graph showing a Weibull distribution of a destructive life of a brazed portion of a semiconductor element substrate by a temperature cycle test.

FIG. 6 is a graph showing a -3σ level life of a brazed portion of a semiconductor element substrate by a temperature cycle test.

FIG. 7 is a graph showing a temperature rise of a semiconductor element base when power is applied to a semiconductor device.

FIG. 8 is a cross-sectional view illustrating an alternative material for the intermediate metal plate.

FIG. 9 is a plan view, a cross-sectional view, and a circuit diagram illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a graph showing transient thermal resistance characteristics of the semiconductor device according to one embodiment.

FIG. 11 is a graph showing a change in thermal resistance of a semiconductor device according to an example in a temperature cycle test.

FIG. 12 is a block diagram illustrating an electronic device in which a semiconductor device according to one embodiment is incorporated.

FIG. 13 is a block diagram showing the inside of a semiconductor device according to another embodiment.

14A and 14B are a bird's-eye view and a cross-sectional view illustrating a semiconductor device on which a power semiconductor element substrate and a control circuit thereof are mounted.

FIG. 15 is a graph showing changes in thermal resistance of a semiconductor device in a temperature cycle test.

FIG. 16 is a diagram illustrating a circuit of a semiconductor device according to another embodiment.

FIG. 17 is a circuit diagram of another semiconductor device used to supply power to a coil of an automobile engine ignition device.

FIG. 18 is a diagram illustrating a circuit of a semiconductor device according to another embodiment.

FIG. 19 is a DC / D in which a semiconductor device according to another embodiment is incorporated.
It is a block diagram explaining the electronic device as a C converter.

FIG. 20 is a diagram illustrating another circuit of the semiconductor device of the present invention.

FIG. 21 is a diagram illustrating an inverter device incorporating the semiconductor device of the present invention.

FIG. 22 is a diagram illustrating another electric circuit of the semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor element base, 2 ... Circuit board, 3 ... Brazing material, 3 '
... brazing material layer, 4 ... intermediate metal plate, 5 ... alumina ceramics substrate, 6, 6 '... Al wire, 7 ... terminal, 7a ... gate terminal, 7b ... drain terminal, 7c ... source terminal, 7A ... input terminal, 7B ... output terminal, 8 ... epoxy resin, 8a ... silicone gel resin, 8b ... epoxy resin, mold resin, 9,25 ... silicone resin adhesive, 10,10A ...
Control circuit, 11: resistor, 12: IC chip base, 13 ...
Capacitor, 13A: surge protection element, 14: diode, 20: case, 21: epoxy resin frame, 22: case lid, 30: semiconductor device, 31: brazing, 41: first
Metal, 41 ': SiC powder, 41 ": SiC fiber cloth, 42: Second metal, 43: Ni plating, 60: Gate drive circuit, 70: Control unit, 81: Transformer, 82
... Rectifier circuit, 83 ... Smoothing and control circuit, 84 ... Input power supply, 85 ... Battery, 86 ... Load circuit, 90 ... Electronic device, 2
01 ... metal plate, 202 ... epoxy resin insulating layer, 203 ...
Cu wiring layer, 950 ... motor.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mamoru Iizuka 111 Nishiyokote-cho, Takasaki City, Gunma Prefecture Semiconductor Engineering Division, Hitachi, Ltd. (72) Inventor Tsuneo Endo 4-6-1 Kanda Surugadai, Chiyoda-ku, Tokyo Shares (72) Inventor Yoshio Sudo, 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Hitachi, Ltd. Inside Semiconductor Co., Ltd. (72) Inventor Toshiharu Niitsu 4-6-6 Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi, Ltd. F term in the Semiconductor Division (reference) 5F036 AA00 BB08 BC06 BD01 BE01

Claims (3)

[Claims] 1. A mounting member comprising a semiconductor substrate, a metal plate and a mounting member provided with a wiring layer on a main surface of the metal plate via an insulating layer, and a mounting member formed of a metal plate and disposed between the semiconductor substrate and the mounting member. The intermediate metal plate is Sn, Sb, Ag, Cu, Ni, P, B
At least one material selected from the group consisting of i, Zn, Au and In is fixed by a brazing material made of Sn, and the thermal expansion coefficient in a direction parallel to the fixing surface of the intermediate metal plate is 7-1.
A semiconductor device wherein the thermal conductivity is adjusted to 3.5 ppm / ° C. and the thermal conductivity is adjusted to 150 W / m · K or more. 2. The semiconductor device according to claim 1, wherein a portion to which the semiconductor substrate is fixed is sealed with a resin. 3. A mounting member having a wiring layer provided on a main surface of a semiconductor substrate and a metal plate via an insulating layer or a mounting member formed of a metal plate, and a mounting member disposed between the semiconductor substrate and the mounting member. The intermediate metal plate is Sn, Sb, Ag, Cu, Ni, P, B
At least one material selected from the group consisting of i, Zn, Au and In is fixed by a brazing material made of Sn, and the thermal expansion coefficient in a direction parallel to the fixing surface of the intermediate metal plate is 7-1.
An electronic device, wherein a semiconductor device adjusted to 3.5 ppm / ° C. and a thermal conductivity of 150 W / m · K or more is incorporated in a device for supplying power to a load.