JP2009099655A - Lead-free soldering method of wide-gap semiconductor chip - Google Patents
Lead-free soldering method of wide-gap semiconductor chip Download PDFInfo
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Abstract
Description
本発明は、ＳｉＣ等のワイドギャップ半導体チップの電極を鉛フリー半田で半田付けする方法に関するものである。 The present invention relates to a method of soldering electrodes of a wide gap semiconductor chip such as SiC with lead-free solder.
従来、たとえば図１（ａ）および図２（ａ）に例示したように、ワイドギャップ半導体チップにおいて、Ａｇの酸化膜（図中「Ａｇ層」）がチップ電極最表面に形成されていても、鉛系の半田を使用した場合では、その濡れ性が鉛フリー半田よりも良いため、電極間の接合状態に大きな問題は生じていなかった。
しかし、錫−銀−銅（Sn-Ag-Cu）や金−錫（Au-Sn）などの鉛フリー半田は、鉛系半田に比べ濡れ性が悪いため、電極表面の状態による影響が大きい。このため、鉛系半田と同様な条件で半田付けを行ったとしても、図２（ｂ）に例示したような未接合部が生じてしましい、鉛系半田と同等の接合状態を作り出すことは、極めて困難である。
この鉛フリー半田を使用した場合の問題点を克服する手法としては、たとえば以下のものが考えられる。
１．電極最表面の酸化物層を化学薬品により除去する（いわゆるウェットエッチング）。
２．ドライエッチングなど物理的な手法で除去する。
Conventionally, for example, as illustrated in FIG. 1A and FIG. 2A, in a wide gap semiconductor chip, an Ag oxide film (“Ag layer” in the figure) is formed on the outermost surface of the chip electrode. When lead-based solder is used, the wettability thereof is better than that of lead-free solder, so that no major problem has occurred in the bonding state between the electrodes.
However, lead-free solders such as tin-silver-copper (Sn-Ag-Cu) and gold-tin (Au-Sn) have poor wettability compared to lead-based solder, and are therefore greatly affected by the state of the electrode surface. For this reason, even if soldering is performed under the same conditions as lead-based solder, an unjoined portion as illustrated in FIG. 2B may be produced, and a joint state equivalent to lead-based solder is created. It is extremely difficult.
As a technique for overcoming the problems in the case of using this lead-free solder, for example, the following can be considered.
1. The oxide layer on the outermost surface of the electrode is removed with chemicals (so-called wet etching).
2. It is removed by a physical method such as dry etching.
しかしながら、１の手法では、例えば、亜鉛と塩酸の溶液を使用することで除去することは可能であるものの、これはチップの表面電極を犯してしまうという問題あり、また亜鉛が残留すると更に半田濡れ性が低下する。
２の手法としては、例えば、プラズマエッチング方法などがあるが、チップ自体の温度が上昇してしまうため、電極に使用している金属へのダメージが懸念される。
また、１，２ともに、除去後即時に半田付けしなければ、最表面に酸化物層が再び構成されてしまい、半田付けとのタイミング設定に難がある。
However, in one method, for example, it can be removed by using a solution of zinc and hydrochloric acid. However, this has a problem that the surface electrode of the chip is violated. Sex is reduced.
As the second method, for example, there is a plasma etching method or the like. However, since the temperature of the chip itself increases, there is a concern about damage to the metal used for the electrode.
If both 1 and 2 are not soldered immediately after removal, an oxide layer is formed again on the outermost surface, which makes it difficult to set the timing for soldering.
本発明は、以上の事情に鑑みてなされたものであり、ワイドギャップ半導体チップの電極構造において、鉛フリー半田を用いた半田付けを行った場合の接合状態を良好なものとし、上記各種手法と同様な問題点も生じることのない、ワイドギャップ半導体チップの鉛フリー半田付け方法、および鉛フリー半田付けによるワイドギャップ半導体チップを提供することを課題としている。 The present invention has been made in view of the above circumstances, and in the electrode structure of a wide gap semiconductor chip, the bonding state when soldering using lead-free solder is made favorable, It is an object of the present invention to provide a lead-free soldering method for a wide gap semiconductor chip and a wide gap semiconductor chip by lead-free soldering without causing the same problems.
本発明は、上記の課題を解決するものとして、ワイドギャップ半導体チップの電極上に、鉛フリー半田付け時の電極最表面の酸化を防ぐ保護層を形成し、該保護層上に鉛フリー半田で半田付けを行う、ことを特徴とするワイドギャップ半導体チップの鉛フリー半田付け方法を提供する。
また、本発明は、上記の課題を解決するものとして、ワイドギャップ半導体チップの電極上に、鉛フリー半田付け時の電極最表面の酸化を防ぐ保護層が設けられ、該保護層上に鉛フリー半田で半田付けが行われている、ことを特徴とする鉛フリー半田付けによるワイドギャップ半導体チップを提供する。
上記のとおりの特徴を有する本発明によれば、ワイドギャップ半導体チップの電極構造において、上記保護層を１層以上設けることにより、鉛フリー半田付け時に酸化物層自体が電極最表面に構成されず、よって、図２（ｂ）に例示したような電極最表面と鉛フリー半田との間の未接合部が生じない、良好な接合状態を持つ鉛フリー半田付けを実現することができる。
保護層としては、半田付け前に除去する必要のない材料であって、なおかつ鉛フリー半田となじみが良い、もしくは半田付けの際に鉛フリー半田に吸収される材質のものを選択する。候補として考えられる材料は、例えば、金、プリフラックスなどが挙げられる。金の製膜は真空蒸着もしくはめっきで行うことができる。
In order to solve the above problems, the present invention forms a protective layer on the electrode of a wide gap semiconductor chip to prevent oxidation of the outermost surface of the electrode during lead-free soldering, and the lead-free solder is formed on the protective layer. Provided is a lead-free soldering method for a wide gap semiconductor chip, characterized by performing soldering.
In order to solve the above problems, the present invention provides a protective layer for preventing oxidation of the outermost surface of the electrode during lead-free soldering on the electrode of the wide gap semiconductor chip, and the lead-free coating is provided on the protective layer. Provided is a wide gap semiconductor chip by lead-free soldering, which is characterized by being soldered with solder.
According to the present invention having the features as described above, in the electrode structure of the wide gap semiconductor chip, by providing one or more protective layers, the oxide layer itself is not formed on the outermost electrode surface during lead-free soldering. Therefore, it is possible to realize lead-free soldering having a good joined state in which an unjoined portion between the electrode outermost surface and lead-free solder as illustrated in FIG. 2B does not occur.
As the protective layer, a material that does not need to be removed before soldering and that is compatible with lead-free solder or that is absorbed by lead-free solder during soldering is selected. Examples of materials considered as candidates include gold and preflux. Gold film formation can be performed by vacuum evaporation or plating.
［第一実施形態］
図２（ｂ）は、本発明の一実施形態であり、上記のとおりの保護層として１層の金層が電極最表面をカバーして設けられている。
ここで、図２（ａ）の金薄膜層（厚さ１００ｎｍ以上）で電極最表面をカバーしていないワイドギャップ半導体チップと図２（ｂ）の金薄膜層でカバーしたものそれぞれに対してSn-Ag-Cuの鉛フリー半田を用いた半田付け付けを行ったところ、図３（ａ）（ｂ）に示すようなＸ線透視装置による画像が得られた。この画像データから算出した結果、同じ鉛フリー半田を使用して同じ条件で半田付けした場合、未接合部分であるいわゆるボイドが３５％から１５％に減少していることが分かった。
ボイドが多いとShear強度が低くなる、熱伝導が悪くなるといった、特にパワーデバイスでは致命的な問題が生じるが、本発明によれば、極めて良好な接合状態が得られ、Shear強度ならびに熱伝導の向上を図ることができる。
なお、半田付けの条件としては、窒素などの不活性ガス中での加熱、真空中での加熱など極力酸素を排した環境での半田付けが望ましい。
[First embodiment]
FIG. 2B shows an embodiment of the present invention, and a single gold layer is provided to cover the outermost surface of the electrode as the protective layer as described above.
Here, Sn is applied to each of the wide gap semiconductor chip that does not cover the outermost surface of the electrode with the gold thin film layer (thickness of 100 nm or more) in FIG. 2A and the gold thin film layer that is covered with the gold thin film layer in FIG. When soldering using a lead-free solder of -Ag-Cu was performed, an image obtained by an X-ray fluoroscopic apparatus as shown in FIGS. 3A and 3B was obtained. As a result of calculation from this image data, it was found that when the same lead-free solder was used and soldered under the same conditions, so-called voids, which are unjoined portions, decreased from 35% to 15%.
When there are many voids, the shear strength becomes low and the heat conduction becomes bad, especially in power devices, but a fatal problem arises.However, according to the present invention, a very good bonding state can be obtained, and the shear strength and heat conduction are reduced. Improvements can be made.
The soldering conditions are preferably soldering in an environment where oxygen is eliminated as much as possible, such as heating in an inert gas such as nitrogen or heating in a vacuum.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| RU2460168C2 (en) * | 2009-12-31 | 2012-08-27 | Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" | Method of soldering silicon carbide-based chips |
| RU2753171C1 (en) * | 2020-11-25 | 2021-08-12 | федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский политехнический университет Петра Великого" (ФГАОУ ВО "СПбПУ") | Method for non-damaging surface mounting of silicon crystals and a3b5 type crystals by using shs foil deposited in form of metallizing multilayer nanostructured coating on surface of these crystals |
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| RU2460168C2 (en) * | 2009-12-31 | 2012-08-27 | Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" | Method of soldering silicon carbide-based chips |
| RU2753171C1 (en) * | 2020-11-25 | 2021-08-12 | федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский политехнический университет Петра Великого" (ФГАОУ ВО "СПбПУ") | Method for non-damaging surface mounting of silicon crystals and a3b5 type crystals by using shs foil deposited in form of metallizing multilayer nanostructured coating on surface of these crystals |
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