JP2003297873A - Semiconductor device, structure and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for which the flow-out of a primary mounting solder material and short-circuit, the disconnection and the position deviation of a chip component due to the flow-out are prevented when loading the semiconductor device composed by loading the chip component on a substrate and resin-sealing the loaded chip component on an external wiring board. <P>SOLUTION: For the semiconductor device, a solder layer fixing the chip component and a wiring member is sealed with a resin layer, and the solder layer is constituted of a composite material for which non-metal powder is dispersed in a matrix metal. Thus, for the semiconductor device, the flow-out of the solder material and the short-circuit, the disconnection and the position deviation of the chip component due to the flow-out at secondarily mounting the semiconductor device composed by loading the chip component on the wiring member by the solder material and resin-sealing the soldered part on an external wiring member can be prevented. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a circuit element (chip component) mounted on a wiring member is resin-sealed.

[0002]

2. Description of the Related Art JP-A-6-614 as a prior art example 1
No. 17 discloses a semiconductor device in which one or more semiconductor elements are fixed to a predetermined conductive pattern formed on the first main surface of an electrically insulating substrate made of alumina, and this is resin-sealed. ing.

Japanese Patent Laid-Open No. 7-2355 as Prior Art Example 2
No. 65 has a wiring board and circuit components electrically connected to the wiring board via bumps made of solder, and solid fine particles for controlling bump height are dispersed in the bumps. The disclosed electronic circuit device is disclosed. Here, the bump is a Pb—Sn alloy having a melting point of 183 ° C., and the solid fine particles are Cu, Fe, Ni, Pt, Ag and alloys thereof, stainless steel balls, Mo powder, resin-coated metal powder. . When a chip component is soldered using such a solder material, an intermetallic compound with Sn grows and bonds on the surface of each solid fine particle. Therefore, the bump height can be easily adjusted, and even if the surface tension of the bump is unbalanced when the chip component is mounted, it is possible to prevent the chip component from being obliquely mounted.

[0004]

In recent years, from the viewpoint of environmental protection, Pb-Sn which has been conventionally applied to mounting electronic parts.
It is desired to substitute the Pb-free alloy for the system alloy material. Currently available Pb-free solder materials are alloys containing an overwhelming amount of Sn, and their melting points are 240 ° C. or lower. Chip parts are mounted on the board using solder material,
When a Pb-free solder material is applied to a resin-sealed semiconductor device in which chip components are resin-sealed, the solder material of the semiconductor device is re-melted at the time of secondary mounting on an external wiring board or the like, resulting in a short circuit or disconnection of wiring. There is a problem of misalignment of chip parts.

In the prior art example 1, consideration is given to remelting of the solder layer and the accompanying short circuit of the internal circuit or deterioration of the circuit function, which is peculiar to the case where the solder material for primary mounting is sealed with a sealing material. Not done.

In the electronic circuit device disclosed in the prior art example 2, although the solid fine particles and the intermetallic compound grown on the surface thereof can prevent the bump height from being adjusted and the chip components to be mounted obliquely, the soldering material for the primary mounting. Does not provide a solution to the above problems peculiar to a system sealed with the above-mentioned sealing material. Further, the solder base material of this prior art example is Pb-S.
Since it is an n-based alloy, it cannot support the above-mentioned Pb-free state.

An object of the present invention is to flow out a solder material for primary mounting when a chip component as a circuit element is mounted on a substrate and a semiconductor device obtained by sealing the mounted chip component with a resin is mounted on an external wiring substrate. Another object of the present invention is to provide a semiconductor device capable of preventing a short circuit, a wire breakage, and a positional deviation of chip parts due to the semiconductor device, a structure using the semiconductor device, or an electronic device using these.

[0008]

The semiconductor device of the present invention comprises:
The solder layer in which the chip component and the wiring member are fixed to each other is sealed with a resin layer, and the solder layer is composed of a composite material in which a nonmetal powder is dispersed in a matrix metal.

Further, in the structure of the present invention, the solder layer in which the chip component and the wiring member are fixed is sealed with the resin layer, and the solder layer is composed of the composite material in which the nonmetal powder is dispersed in the matrix metal. The semiconductor device is fixed to the external wiring member via the connection layer.

Further, in the electronic device of the present invention, the solder layer in which the chip component and the wiring member are fixed is sealed with a resin layer, and the solder layer is composed of a composite material in which a non-metal powder is dispersed in a matrix metal. A semiconductor device or a structure in which the semiconductor device is fixed to an external wiring member via a connection layer is incorporated.

Here, examples of the electronic device include a secondary battery device, a high frequency power amplifier device, a power measuring device, a liquid crystal display device or a converter device.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) In this embodiment, a semiconductor device 11 will be described.

FIG. 1 is a schematic sectional view for explaining the semiconductor device of this embodiment. The semiconductor device 11 is configured as follows. The substrate 1 serving as a wiring member is a multi-layer glass ceramics substrate [glass ceramics (also referred to as a low temperature firing substrate), and the inner wiring layer (Ag-1
wt% Pt) 2 and through-hole wiring (Ag-1 wt%
Pt) 2A is provided. A wiring pattern (Ag-1 wt% Pt) 4 is provided on the first main surface 1A of the substrate 1,
On this wiring pattern 4, a semiconductor element substrate (Si, 3.5 ppm / ° C.) including an integrated circuit element substrate 6A (not shown) and an FET element substrate 6B 6, a chip resistor (about 7 ppm /
(C) 8 and capacitors (about 11.5 ppm / C) 9 are electrically conductively fixed by the solder layer 5 (primary mounting soldering). As shown in FIG. 2, the solder layer 5 is composed of a composite in which an alumina powder (particle size: 1 μm) 5B is dispersed in a matrix metal 5A made of Sn-5 wt% Sb alloy, and the addition amount of the alumina powder 5B is set. Is 50
It is adjusted to vol%. In addition, a thin metal wire 7 made of Au is provided between the semiconductor element base 6 and a predetermined portion of the wiring pattern 4.
Bonding (integrated circuit element substrate 6A: diameter 27μ
m, FET element base 6B: diameter 50 μm).
These chip parts, the thin metal wires 7, and the first main surface 1A are resin layers whose main component is an epoxy material (the physical properties after curing are: thermal expansion coefficient: 9.0 ppm / ° C, Young's modulus: 24.5 GPa, glass. It is sealed so as to be completely shielded from the outside air by a transition point: 150 ° C., a filler addition amount: 85 wt%) 10.
The second surface of the multilayer ceramic substrate 1 opposite to the first main surface 1A
An external electrode layer (Ag-1 wt% Pt) 3 is provided on the main surface 1B. The external electrode layer 3 is electrically connected to the wiring pattern 4 via the inner wiring layer 2 and the through-hole wiring 2A provided inside the multilayer ceramic substrate 1. Since the chip component including the semiconductor element substrate 6 including the integrated circuit element substrate 6A and the FET element substrate 6B, the chip resistor 8 and the capacitor 9 is conductively fixed on the wiring pattern 4 by the solder layer 5, the external electrode layer 3 is formed. Are also electrically connected to these chip components. Here, the inner wiring layer 2 and the through-hole wiring 2A are arranged so as to be embedded in the inner region of the multilayer ceramic substrate 1. Although not shown, a Ni plating layer and an Au plating layer are sequentially provided on the surfaces of the wiring pattern 4 and the external electrode layer 3. Also, chip resistor 8 and capacitor 9
A Ni plating layer and a Sn plating layer are sequentially provided on the electrode of. As described above, all the chip components are completely sealed by the substrate 1, the wiring pattern 4, and the resin layer 10, and the solder layer 5 fixing these chip components is also the chip components 6, 8, 9, Wiring pattern 4, resin layer 1
It is completely sealed by 0.

Next, the solder layer 5 will be described. Figure 2
FIG. 3 shows a schematic sectional view of a solder layer applied to the semiconductor device of this example. (A) is a schematic diagram of the solder layer 5, S
In a matrix metal 5A made of an n-5 wt% Sb alloy (melting point: 230 to 240 ° C.), alumina (average particle size:
The non-metal powder 5B of about 1 μm) is dispersed. The addition amount of the non-metallic alumina powder 5B is 50 vo
l% and the remaining 50 vol% is matrix metal 5A
Are occupied by. (B) shows the semiconductor element substrate 6 (6A, 6
It is an expanded sectional schematic diagram of the part in which B) is mounted. The semiconductor element substrate 6 is electrically conductively fixed to the wiring pattern 4 on the substrate 1 by the solder layer 5 having the structure (a). Substrate 1, wiring pattern 4, semiconductor element substrate 6 (6
A, 6B) and the solder layer 5 are sealed by the resin layer 10. On the surface of the wiring pattern 4, a Ni plating layer (5 μm
m, not shown) and an Au plating layer (1 μm, not shown) are sequentially provided. Here, the semiconductor element substrate 6
Ti (0.15 μm) -on the adhered surface of (6A, 6B)
Ni (0.6 μm) -Au (0.2 μm) laminated metal layer 60
5 is formed by vapor deposition. (C) is an enlarged schematic sectional view of a portion where the chip resistor 8 and the capacitor 9 are mounted. The chip resistor 8 and the capacitor 9 also have the wiring pattern 4 on the substrate 1 by the solder layer 5 having the structure (a).
Is electrically conductively fixed to. Here, the chip resistor 8 and the capacitor 9 are provided with an electrode 105 made of an Ag thick film. Although not shown, the surface of the Ag thick film has a Ni plating layer (5 μm) and a Sn plating layer (1 μm).
Are provided in sequence. However, chip parts 6, 8, 9
After being fixed (first mounting soldering), the Au plating layer on the wiring pattern 4, the Au layer on the laminated metal layer 605,
The Sn plating layer on the electrode 105 merges with the solder layer 5.
The substrate 1, the wiring pattern 4, the chip resistor 8, the capacitor 9, and the solder layer 5 are sealed with a resin layer 10.
A particularly characteristic feature of the present invention is that the non-metallic powder 5B is dispersed in the matrix metal 5A while the periphery of the solder layer 5 is completely sealed by another solid substance. With the solder layer 5 having such a configuration, the solder material 5 is substantially fluidized even when the semiconductor device 11 is heated to a temperature at which the matrix 5A is in a molten state (secondary mounting soldering) in a subsequent step. No
Short circuits, displacement of chip parts and deterioration of heat dissipation of chip parts are avoided. These are important points in the present invention.

Next, the problem when the solder layer 5 is composed only of a matrix metal will be described. FIG. 3 is a schematic cross-sectional view illustrating a problem when the solder layer is composed of only matrix metal. Where (a), (b)
Is mainly a resin with a high Young's modulus (eg epoxy resin)
Problems that often occur when sealed by 10,
(C) and (d) show problems that are likely to occur mainly when the resin is sealed with a resin (for example, gel resin) 10 having a low Young's modulus and a high thermal expansion coefficient. (A) is a schematic cross-sectional view illustrating a state in which a short circuit occurs between electrodes of a chip component due to a flow of molten solder. By increasing the internal pressure P (825 MPa) due to the remelting of the solder layer 5, the chip component 8,
Resin 10 in the vicinity of 9 peels off (between chip component and sealing resin)
The molten solder material 5a along the voids created thereby.
Is leaked. When this outflow proceeds, the electrodes 105 are short-circuited. (B) is a schematic cross-sectional view illustrating a state in which the peripheral wiring patterns are short-circuited by the flow of the molten solder. The resin 10 in the vicinity of the chip components 8 and 9 is peeled off (between the substrate and the sealing resin) due to the increase in the internal pressure P due to the remelting of the solder layer 5, and the molten solder material 5a flows out along the void created thereby. When this outflow progresses, the wiring patterns 4 are short-circuited. (C) is a schematic cross-sectional view illustrating a state in which the chip component is lifted up by the flow of molten solder and the thermal deformation of the sealing resin. This is a phenomenon that tends to occur when the chip component is the semiconductor element substrate 6 (6A, 6B).
The semiconductor element substrate 6 is lifted in the Y direction by an external force based on the thermal deformation of the solder layer 5, and the peripheral portion of the solder layer 5 is narrowed accordingly. As a result, the solder layer 5 is in a state where the heat conduction is obstructed over most of the area. In particular, the FET element substrate 6B has a large amount of heat generation, and the phenomenon of (c) becomes an obstacle to normal electrical operation. (d) is a phenomenon that tends to occur when the chip components are passive components 8 and 9, and the components 8 and 9 float up in the Y direction or move in the X direction (positional shift) due to external force based on thermal deformation of the resin 10. To do. In particular, when the positional deviation progresses, the molten solder material 5 short-circuits the wiring patterns 4. Although not shown in the figure, the solder layer 5 is cut due to the progress of displacement, and the electrode 105 and the wiring pattern 4 are electrically disconnected.

Next, returning to FIG. 2, the description will be continued. When the matrix 5A is remelted in the secondary mounting soldering process, its volume expands by about 16% in the process of changing from the solid phase state to the liquid phase state. On the other hand, since the non-metal powder 5B has a higher melting point than the matrix metal 5A, the solid state is maintained even when the matrix metal 5A is in a molten state.
The volume expansion amount shared by the non-metal powder 5B is so small that it can be ignored. Since the volume ratio of the non-metal powder 5B to the solder layer 5 is 50 vol%, the substantial expansion of the solder layer 5 can be suppressed to about 8%. This value is 1/2 that in the case where the solder layer is composed only of the matrix metal. Internal pressure generated in the solder layer 5 by ½ volume expansion is 413MP
a (42 kgf / mm ² ), and the solder layer is composed only of matrix metal, 825 MPa (84.1 kgf /
mm ² ). As a result, peeling of the bonding interface of the sealing resin is suppressed, so that the molten solder material flows out along the peeling void, or a short circuit occurs between the electrodes 105 or between the wiring patterns 4 (see FIGS. 2A and 2B). ) Is prevented. Also,
Even if the bonding interface of the sealing resin peels off and the flow of the solder layer 5 starts, the non-metal powder 5B has a role of suppressing the flow of the molten matrix 5a (clogging phenomenon) by depositing in the minute peeling voids. .

As described above, in the present embodiment, the presence of the non-metal powder 5B that maintains the solid phase state reduces the substantial volume expansion of the solder layer 5 even if it is re-melted, resulting in an excessive internal pressure. It is possible to suppress the rise, peeling of the sealing resin, the outflow of the molten solder material and the short circuit, and the outflow and the short circuit of the molten solder material due to the clogging phenomenon of the non-metal powder 5B.

In the present invention, the sealing resin 10 for sealing the chip components mounted on the substrate 1 is not limited to the epoxy material having a high Young's modulus. For example, gel resin (Young's modulus: 0.98MP
a, coefficient of thermal expansion: 950 ppm / ° C, penetration: 55 to 90
(1 / 10mm)), silicone resin (Young's modulus: 11G
Pa, thermal expansion coefficient: 30 ppm / ° C.) When sealed with resin 10 having a low Young's modulus and a high thermal expansion coefficient, if the primary mounting solder material is composed only of matrix metal, it will be re-melted. It causes "floating" and "misalignment" of mounted chip parts. The floating means that the chip component is lifted from a predetermined mounting position (floating vertically with respect to the board,
3 (c)) mode. The displacement is
It appears as a mode in which the plate is deviated from the predetermined mounting position and horizontally displaced with respect to the substrate (see FIG. 3D). Such floating or displacement is not preferable because it leads to loss of the circuit function of the semiconductor device. According to the study by the present inventors, this is because the chip component released from the fixed state by remelting of the primary mounting solder material is applied in the horizontal direction with respect to the substrate by the application of external force due to thermal expansion or thermal deformation of the resin. And that can be moved in the vertical direction.

As described above, since the solder material composed only of the matrix has a high internal pressure due to its remelting, the surrounding environment collapses (peeling of the sealing resin or deformation of the resin) to accelerate fluid deformation. On the other hand, in this embodiment, the non-metal powder 5B is the matrix metal 5A.
Has a function of lowering the substantial fluidity of the solder layer 5 (in other words, increasing the viscosity) when remelted. Here, the non-metal powder 5B increases (1) the role of a resistance substance that blocks the flow of the molten matrix 5B itself, and (2) increases the contact area between the liquid phase (molten matrix metal 5B) and the solid phase (non-metal powder 5B). And has a role of increasing the bonding force between the two (suppressing breaking of the molten matrix 5B). Due to the effects of (1) and (2) above, the substantial fluidity of the solder layer 5 is lowered, and floating and displacement are suppressed. As described above, by applying the solder layer of the present embodiment, the viscosity of the remelted solder layer 5 is substantially increased by the non-metal powder 5B, the movement of the chip component due to the application of the external force is suppressed, and the disconnection and the floating are caused. And positional deviation can be suppressed.

Further, the use of non-metallic powder as the powder to be added to the solder material 5 has the following advantages. (1) Generally, the density of the non-metal powder is lower than that of the metal powder, so that the dispersibility in the solder material can be improved. (2) Even if a crack occurs in the solder material due to the temperature cycle, the crack does not propagate in the non-metal powder and the crack propagates by bypassing the non-metal powder, so that the temperature cycle life can be extended. (3) The non-metallic powder can be easily manufactured at low cost because the particle size can be easily adjusted (sorted) by crushing. (4) The non-metal powder does not elute harmful metal ions that are harmful to the environment.

In the semiconductor device of the present invention, the solder layer 5
It is particularly desirable that the matrix metal 5A constituting the above is a metal or alloy mainly composed of Sn from the viewpoint of environmental protection. As the matrix metal 5A suitable for such purpose, a metal composed of Sn or Sn, Sb, Zn, Cu,
Ni, Au, Ag, P, Bi, In, Mn, Mg, S
An alloy composed of two or more kinds selected from the group of i, Ge, Ti, Zr, V, Hf and Pd can be selected. For example, Sn
-3.5 wt% Ag, Sn-3 wt% Ag-0.8 wt% C
Sn-Ag alloy represented by u, Sn-5wt
% Sb, Sn-10 wt% Sb, Sn-5 wt% Sb-
Represented by Sn-Sb-based alloys represented by 0.6 wt% Ni-0.05 wt% P, Sn-Bi-based alloys represented by Sn-58 wt% Bi, and Sn-0.7 wt% Cu. Sn-Cu based alloy, Sn-52 wt% I
Sn-In based alloy represented by n, Sn-9wt
% Zn, Sn-Zn alloy, In-1
In-Ag based alloys represented by 0 wt% Ag, and Au-S represented by Au-20 wt% Sn.
It may be replaced with an n-based alloy. Also, Sn-8.5wt
% Zn-1.5 wt% In, Sn-4 wt% Ag-2w
t% Zn-2wt% Bi, such as the above-mentioned Sn system, Sn
-Ag system, Sn-Sb system, Sn-Bi system, Sn-Cu
It is also possible to apply an alloy material which is an arbitrary combination of a system, Sn-In system, Sn-Zn system, In-Ag system, and Au-Sn system solder material. Among the above alloys, Sn-3 wt% Ag-0.8 wt% Cu, S is more preferable material.
n-10 wt% Sb, Sn-0.7 wt% Cu, Sn-
9 wt% Zn can be mentioned.

However, since these metals or alloys contain an overwhelmingly large amount of Sn, their melting points are not so high as around 200.degree. In addition, the solder layer 5 after the primary mounting is fused with the metal forming the fixing portion of the chip components 6, 8, 9 and the metal provided on the surface of the wiring pattern 4. By this fusion, the solder layer 5 after the primary mounting
Will have an even lower melting temperature (this will be discussed below). Therefore, the solder layer 5 containing a large amount of Sn
In such a case, problems such as remelting due to secondary mounting soldering, outflow of molten solder material, short circuit, disconnection, floating and displacement are likely to occur, and the role of the present invention for providing these preventive measures becomes more important.

On the other hand, although it is a step back in terms of making Pb free, in the present invention, even the solder material 5 containing Pb can be applied for the primary mounting of the chip components 6, 8 and 9. For example, Pb-12 wt% Sn-8 wt% Sb-1
wt% Ag alloy, Pb-5wt% Sn, Pb-3.5wt
% Sn-1.5 wt% Ag, Sn-60 wt% Sn, Sn
A Pb-Sn alloy represented by -50 wt% Sn can be used. Many of these alloys have a higher melting point than the Pb-free solder material containing a large amount of Sn as described above.

However, the solder layer 5 after the primary mounting is fused with the metal on the surface of the fixed portion of the chip parts 6, 8 and 9 or the surface metal of the wiring pattern 4, so that the solder layer 5 after the primary mounting has a low melting temperature. The circumstances that result in having the same are as described above (this will be described later). Therefore, even in the case of the solder layer 5 containing Pb, the role of the present invention is important to prevent re-melting due to secondary mounting soldering, outflow of molten solder material, short circuit, disconnection, floating and displacement.

Next, a solder material mainly containing Sn and Pb
With respect to the melting point lowering when the Sn-based solder material is fused with the peripheral material, the mechanism will be described.

FIG. 4 shows the case of Sn-10 wt% Sb solder material
It is a graph explaining melting point fall when u fuses.
(A) is a schematic diagram of endothermic characteristics when the solder material is not fused with Au, (b) is a schematic diagram of endothermic characteristics when fused with Au, and (c) is the Au concentration dependence of the endothermic peak height Indicates. Here, Au is the introduction source of the wiring pattern 4 or Au provided on the surface of the laminated metal layer 605 in the semiconductor element substrate 6. When the solder material does not fuse Au (a), an endothermic reaction having a peak at about 245 ° C. occurs in the temperature rising process. By this reaction, the solder material changes from the solid phase to the liquid phase and becomes a molten state. The endothermic peak (ΔP1) corresponding to this peak shows a large value. When Au is fused (b), the peak at 245 ° C. in (a) shifts to the low temperature side to 235 ° C., and a deep peak (ΔP2) of about 221 ° C. is generated in the lower temperature region. At this time, the endothermic peak (ΔP1) on the high temperature side becomes shallower than the peak ΔP1 in the case of (a). The above tendency is summarized as (c). The peak on the high temperature side (ΔP1) decreases as the Au concentration in the solder increases, whereas the peak on the low temperature side (ΔP2) increases as the Au concentration increases. From this tendency, although the solder material with a small amount of Au fusion changes from the solid phase to the liquid phase by the reaction corresponding to the high temperature side peak (ΔP1), the reaction of the low temperature side peak (ΔP2) increases as the amount of Au fusion increases. It becomes dominant and the lowering of the melting point is promoted.

FIG. 5 shows Pb-12 wt% Sn-8 wt% S.
It is a graph explaining melting point fall when Sn fuses to b-1wt% Ag solder material. Here, Sn uses Sn plating provided on the surfaces of the electrodes 105 of the chip components 8 and 9 as an introduction source. (A) is a schematic diagram of endothermic characteristics when the solder material is not fused with plating Sn, (b) is a schematic diagram of endothermic characteristics when fused with plating Sn, and (c) is Sn concentration at endothermic peak height Show dependencies. Solder material is Sn
(A) is not fused, the temperature rise process is about 245 ° C.
An endothermic reaction with a peak at occurs. By this reaction, the solder material changes from the solid phase to the liquid phase and becomes a molten state. The endothermic peak (ΔP1) corresponding to this peak shows a large value. When the plating Sn is fused (b), the peak at 245 ° C in (a) shifts to the low temperature side to 230 ° C, and a deep peak at about 183 ° C in the lower temperature region.
Yields (ΔP2). At this time, the endothermic peak (ΔP
1) is shallower than the peak ΔP1 in the case of (a). The above tendency is summarized as (c). The peak on the high temperature side (ΔP1) decreases as the Sn concentration in the solder increases, while the peak on the low temperature side (ΔP2) decreases with the plating S.
It increases as the n concentration increases. From this tendency, plating S
The peak of the high temperature side (ΔP1) for solder materials with a small fusion amount of n
Although it changes from the solid phase to the liquid phase by the reaction corresponding to, the peak on the low temperature side (Δ
The reaction of P2) becomes dominant and the lowering of the melting point is promoted.

As described above, the problem that the peripheral material is taken in by the primary mounting solder to have a low melting point and is easily re-melted in the secondary mounting soldering is that the solder material 5 contains a large amount of Sn, It is common to all cases where a large amount of Pb is contained.

The solder layer 5 of this embodiment is also effective in suppressing fusion of peripheral materials. The amount of the peripheral material dissolved in the molten solder material 5 in the primary mounting soldering is (a) the substantial contact area between the matrix metal 5A and the peripheral material in the solder material 5, (b) the molten solder material at the contact interface. It is determined by the liquidity factor. In other words, the amount of the peripheral material melted in is larger as the contact area is larger and the fluidity is higher, and conversely is smaller as the contact area is smaller and the fluidity is lower. As described with reference to FIG. 2, in the semiconductor device 11 of the present embodiment, the solder layer 5 has the alumina powder 5B dispersed in the Sn-5 wt% Sb alloy matrix metal 5A, and the volume occupied by the alumina powder 5B and the matrix metal 5A. Is 50 vol% respectively. Since the molten matrix metal 5A near the contact interface is blocked by the alumina powder 5B,
The substantial contact area with the surrounding material is reduced. Moreover, as described above, the fluidity of the molten matrix metal 5A is lowered (the viscosity is increased). Due to the decrease in fluidity, the fresh molten matrix metal 5A containing no peripheral material substance is less likely to be supplied to the contact interface, and further dissolution of the peripheral material is suppressed. As a result, Au and S
The amount of fusion of n can be reduced, and the low temperature side peak (ΔP
The lowering of the melting point due to the reaction of 2) can be suppressed. This is also one of the important actions in the present invention. Therefore, by applying the solder material of this embodiment, the molten solder material 5
By substantially reducing the contact area with the peripheral material and reducing the fluidity, it is possible to suppress the melting of the peripheral material and the accompanying lowering of the melting point.

Next, a method of manufacturing the semiconductor device 11 of this embodiment will be described. FIG. 12 is a diagram illustrating a multi-layer glass ceramic substrate applied to the semiconductor device of this example. As shown in the sectional view of (a), the first green sheet made of a mixture of the glass ceramic material 1C and an organic material (the area after firing is 78.8 mm × 75 mm and the thickness after firing is 0.25 mm). Through hole is formed in a predetermined portion of the paste 18 and the paste 18 is adjusted such that the composition after firing is Ag-1 wt% Pt in the through hole.
While filling B, a paste layer 18A for forming the wiring pattern 4 is formed by a screen printing method. Further, as shown in (b), a through hole is formed in a predetermined portion in the same second green sheet 64 as described above, the same paste 18B is filled in this through hole, and the inner wiring layer 2 is formed. The paste layer 18C for forming is formed by the screen printing method. A break line (groove) 16 is provided in advance on the back surface of the second green sheet 64. The break line 16 divides the multilayer glass ceramic substrate 1 in a subsequent process and determines the size (or section) of the semiconductor device 11. In this section, 102 effective areas can be obtained. Next, the first and second green sheets 63 and 64 are laminated and fired at 1000 ° C. to simultaneously sinter the material of the glass ceramic material 1C and the pastes 18A, 18B and 18C. Green sheets 63, 64 after this process
Are bonded to each other and become a highly rigid sintered body. As shown in the plan view of (c), the surface of the green sheet 63 side after sintering (first of the multilayer glass ceramic substrate 1
A wiring pattern 4 is formed on the main surface 1A). The wiring pattern 4 is patterned so as to fit within a section formed by break lines 16 provided on the opposite surface (corresponding to the second main surface 1B of the multilayer glass ceramic substrate 1). Then, as shown in the plan view of (d),
The composition after firing on the opposite surface (second main surface 1B) is Ag-1.
A paste 18D, which is adjusted to have wt% Pt and is to become the external electrode layer 3 after firing, is formed by a screen printing method and fired in air at 850 ° C. Through this step, the multilayer glass ceramic substrate 1 is obtained. In addition,
Wiring pattern 4 on this multilayer glass ceramic substrate 1
On the external electrode layer 3, a Ni plating layer (not shown, thickness: 0.5 to 4 μm) and an Au plating layer (not shown, thickness: 0.1 to 2 μm) are sequentially laminated. It Ni
The plating layer is used for the primary and secondary mounting soldering.
And acts as a barrier that prevents the wiring pattern 4 and the external electrode layer 3 from being eroded by the external wiring connection layer solder material 12. The Au plating layer has a role of imparting wettability to the solder material 5 and the solder material 12 for the external wiring connection layer, and at the same time imparting wire bonding property of the thin metal wire 7. As shown in the sectional view of (e), the multilayer glass-ceramic substrate 1 includes a wiring pattern 4, an inner wiring layer 2, a through-hole wiring 2A, and an external electrode layer provided on the first main surface 1A in a plurality of compartments. 3 is provided, and these predetermined parts are electrically connected. The area of the multilayer glass ceramics substrate 1 after firing is 78.8 mm × 75 mm.
And the thickness is adjusted to 0.5 mm. The multilayer glass ceramic substrate 1 obtained through the above steps is
Thermal expansion coefficient: 6.2 ppm / ° C, thermal conductivity: 2.5 W / m
K, bending strength: 2.5 GPa, Young's modulus: 110 GP
a, dielectric constant: 5.6 (1 MHz).

The multilayer glass-ceramic substrate 1 has another performance [coefficient of thermal expansion: 12.2 ppm / ° C., thermal conductivity: 2.0 W /
m · K, bending strength: 2.0 GPa, Young's modulus: 110 G
Pa, dielectric constant: 5.4 (1 MHz)] multi-layer glass-ceramic substrate or multi-layer ceramic substrate using alumina material as a base material [coefficient of thermal expansion: 12.2 ppm / ° C, thermal conductivity: 2.0 W / m] K, flexural strength: 2.0 GPa, Young's modulus: 110 GPa, dielectric constant: 5.4 (1 MHz)]. In any case of the multilayer glass ceramics substrate or the multilayer alumina ceramics substrate, the inner wiring layer 2, the through-hole wiring 2A, the external electrode layer 3, and the wiring pattern 4 are made of Ag conductive material, Cu conductive material, W, It is also possible to substitute a conductive material made of Cu in which a metal powder such as Mo is dispersed.

FIG. 13 is a sectional view showing the subsequent manufacturing process of the semiconductor device. On the wiring pattern 4 of the multilayer glass ceramics substrate 1, a chip component composed of a semiconductor element substrate 6 including an integrated circuit element substrate 6A and an FET element substrate 6B, a chip resistor 8 and a capacitor 9 (not shown) has a composition Sn.
It is electrically conductively fixed by a solder layer 5 in which an alumina powder (particle size: 1 μm, addition amount: 50 vol%) 5B is dispersed in a matrix metal 5A made of −5 wt% Sb. In this step, a paste (paste in which the powder of the matrix metal 5A and the non-metal powder 5B are kneaded with a flux agent in advance) whose composition after soldering is adjusted to the above-described configuration is applied to a predetermined portion of the wiring pattern 4. Print,
The chip parts 6, 8 and 9 are set on the paste, and the procedure of heating to 265 ° C. in air is followed. Through this process,
As shown in (a), the chip parts 6, 8 and 9 are conductively fixed on the multilayer glass ceramic substrate 1.

Here, the solder layer 5 has the structure shown in FIG. Since this point has already been described in detail, only the role of the alumina powder 5B will be described, and the other description will be omitted. The role of the alumina powder 5B is exhibited in the process of mounting the semiconductor device 11 on the wiring board 14 by the secondary mounting soldering described later (see FIG. 6). Its role is 2
During the next mounting soldering, (1) due to the presence of the alumina powder 5B that maintains the solid state, even if the solder layer 5 is remelted, its substantial volume expansion is reduced, and the internal pressure is excessively increased and peeled. , Suppress the outflow and short circuit of the molten solder material, and suppress the outflow and short circuit of the molten solder material due to the clogging phenomenon of the alumina powder 5B. (2) The contact area of the molten solder material 5 with the peripheral materials is substantially small. At the same time, by lowering the fluidity, it is possible to suppress the dissolution of the peripheral material and the lowering of the melting point.

A metal composed of Sn as the matrix metal 5A, or Sn, Sb, Zn, Cu, Ni, Au, A
g, P, Bi, In, Mn, Mg, Si, Ge, Ti,
An alloy consisting of two or more kinds selected from the group of Zr, V, Hf and Pd is selected, and the non-metal powder 5B is an oxide,
One kind of powder selected from the group consisting of nitride, boride, carbide, sulfide, phosphide, silicide, fluoride, silicon simple substance, germanium simple substance, carbon simple substance, and boron simple substance, or a mixed powder composed of two or more kinds is selected. Even when selected, the non-metal powder 5B exerts the preferable actions of (1) and (2) under the condition where the solder layer 5 is hermetically sealed.

Next, as shown in (b), a thin metal wire made of Au (integrated circuit element base 6A: diameter 27 μm, FE, is provided between the semiconductor element base 6 and a predetermined portion of the wiring pattern 4.
The T element substrate 6B (diameter 50 μm) 7 is thermocompression bonded at 200 ° C. On the chip component mounting side of the multilayer glass ceramics substrate 1 which has undergone the steps up to this point, the main component is an epoxy material so that the chip components 6, 8 and 9 and the thin metal wires 7 and the first main surface 1A are completely covered. Is a resin layer
(The physical properties after curing are: thermal expansion coefficient: 9.0 ppm / ° C, Young's modulus:
24.5 GPa, glass transition point: 150 ° C., filler addition amount: 85 wt%) 10 is printed, and 110 ° C. in air ×
The epoxy material is cured by sequentially performing heat treatment for 1.5 hours and 150 ° C. × 1.5 hours. By the above processing, as shown in the sectional structure of (c), the resin layer 10 seals the chip components 6, 8, 9 and the thin metal wires 7 and the first main surface 1A so that they are completely shielded from the outside air. To be done. Next, the resin-molded multilayer glass-ceramic substrate 1 is divided along the break lines 16 by applying an external force due to a bending moment. At this time, the multilayer glass-ceramic substrate 1 and the resin layer 10 are fractured in such a manner that their fracture surfaces substantially belong to the same plane. Further, the external electrode layer 3 also has a form that substantially belongs to the same plane as the fracture surface of the multilayer glass ceramics substrate 1 and the resin layer 10 due to this fracture.

Through the above steps, the semiconductor device 11 disclosed in FIG. 1 is obtained. According to the above process, in the process leading to individual division, chip component mounting, wire bonding, and resin molding can be performed on a multi-layered multi-layer glass ceramics substrate 1 unit. Therefore, the mass productivity of the semiconductor device 11 is increased, and the economic merit is increased.

In the above-described individualizing and dividing step, an external force due to a bending moment is applied to the multilayer glass ceramics substrate 1, the resin layer 10 and the external electrode layer 3. The semiconductor device 11 can also be individualized by cutting with a rotary blade, for example.

According to the semiconductor device 11 described above,
Even if re-melting of the solder layer 5 occurs in the secondary mounting soldering process described later, the matrix metal 5A can be prevented from flowing out and a short circuit caused thereby.

In addition to the materials used in this embodiment, the following materials can be used for the semiconductor device 11 of the present invention.

As the thick film material, materials other than Ag-Pt based materials such as Ag (162 Ω · cm, 962 ° C.), Pt (10
60Ω ・ cm, 1772 ° C), Cu (172Ω ・ cm, 10
84 ℃), Pd (1080Ω ・ cm, 1554 ℃), Au
It may be replaced with a material composed of at least one metal selected from the group of (240 Ω · cm, 1064 ° C.). For example, composition: Cu (about 100 wt%) material, Ag-15w
Thick film materials such as t% Pd materials can also be suitable wiring materials.
In such a case, for example, Ag, Pt, Cu, formed as a wiring layer such as the external electrode layer 3 or the wiring pattern 4,
Forming a Ni layer or an Au layer on the surface of a thick film material made of at least one kind of metal selected from the group of Pd and Au by plating or the like is to maintain the quality of the surface of the thick film material and wire bonding. This is preferable for securing the solderability, ensuring the solder wettability, preventing the corrosion by the solder material, and preventing the formation of intermetallic compounds at the soldering interface.

[0041] The glass ceramic material 1C, for example, _{(1) Al 2 O 3 -2MgO} · SiO 2 - (B 2 O 3 -S
iO ₂ ) system [composition: Al ₂ O ₃ (35 wt%), 2MgO
_{· SiO 2 (25wt%),} B 2 O 3 -SiO 2 glass (4
0 _{wt%)], (2) Al 2 O 3} - (CaO-Al 2 O 3 -
SiO ₂ —B ₂ O ₃ ) system [composition: Al ₂ O ₃ (40 wt
_{%), CaO-Al 2 O} 3 -SiO 2 -B 2 O 3 glass (6
0 wt%)], (3) Al ₂ O _3- (PbO-SiO ₂ -B ₂
O ₃₎ based _{[Composition: Al 2 O 3 (55wt%} ), PbO-S
iO ₂ -B ₂ O ₃ glass (45 wt%)], (4) BaO
_{-Al 2 O 3 -SiO 2 -CaO-} B 2 O 3 system [composition: a glass phase BaAl ₂ SiO ₆ is _{deposited], (5) Al 2 O 3} -
(B ₂ O ₃ —SiO ₂ ) system [composition: Al ₂ O ₃ (50 wt
%), B ₂ O ₃ —SiO ₂ glass (50 wt%)] can be used. The multilayer ceramic substrate 1 obtained by using these glass ceramic materials 1C has, for example, (a) Cu wiring applied, thermal expansion coefficient: 5.9 ppm / ° C., thermal conductivity: 2.2 W / m · K, bending Strength: 0.2 GPa, Young's modulus: 110 GPa, wiring resistance (sheet resistance): 3 mΩ
/ □, (b) Thermal expansion coefficient with Cu wiring: 6.2 ppm / ° C, thermal conductivity: 1.3 W / m · K, bending strength: 0.2 GPa, Young's modulus: 100 GPa, wiring resistance (sheet resistance ): 3 mΩ
/ □, (c) Thermal expansion coefficient of Cu wiring: 12.2 ppm / ° C, thermal conductivity: 2.0 W / mK, bending strength: 0.2 GPa, Young's modulus: 75 GPa, wiring resistance (sheet resistance) ): 3 mΩ
/ □, (d) Coefficient of thermal expansion with Ag or Ag-Pt wiring: 6.
3ppm / ℃, thermal conductivity: 2.5W / mK, bending strength:
0.25 GPa, Young's modulus: 75 GPa, wiring resistance (sheet resistance): 3 mΩ / □, (e) Thermal expansion coefficient with Ag or Ag-Pt wiring: 1
It has characteristics such as 0.4 ppm / ° C., thermal conductivity: 4.7 W / m · K, bending strength: 0.21 GPa, Young's modulus: 75 GPa, wiring resistance (sheet resistance): 3 mΩ / □.

The base material of the substrate 1 is not limited to the glass-ceramic material. As an example, it has wiring in which W is dispersed in Cu, coefficient of thermal expansion: 7.0 ppm / ° C., thermal conductivity: 1.
5.2 W / mK, bending strength: 0.4 GPa, Young's modulus: 3
An alumina substrate having 00 GPa and wiring resistance (sheet resistance): 4 mΩ / □ may be used. Further, the glass-ceramic material that is the base material of the substrate 1 can be replaced with aluminum nitride, silicon nitride, glass, and beryllia. In this case, it is not essential that any substrate 1 of glass ceramics, alumina, aluminum nitride, silicon nitride, glass, and beryllia has the inner wiring layer 2 and the through hole wiring 2A.

The base material of the inner wiring layer 2, the through-hole wiring 2A, the external electrode layer 3 and the wiring pattern 4 has a low wiring resistance, is easy to fire or manufacture, and is resistant to erosion by a solder material. Is selected in consideration of. From this viewpoint, the base materials of the inner wiring layer 2, the through-hole wiring 2A, the outer electrode layer 3 and the wiring pattern 4 are Cu, Ag, Pt,
It may be composed of at least one metal selected from the group of Pd and Au. At this time, it may be formed by a thick film firing method or a physical vapor deposition method. Especially Ag-0.2-1.5wt% P
The t material has a low wiring resistance (sheet resistance) of about 3 mΩ / □,
Simultaneous firing with the glass ceramic material at about 1000 ° C. is easy. Also, Ag-0.2 to 1.5 wt% P
In the case of the t material, even if the chip component is fixed with a molten solder material containing an overwhelming amount of Sn such as Sn-3.5 wt% Ag material (melting point: 221 ° C), erosion by the molten solder material is almost impossible. I do not receive it. When a solder material containing less Sn is used, problems due to erosion can be almost avoided. Therefore, in the present invention, when the external electrode layer 3 and the wiring pattern 4 are made of Ag-0.2 to 1.5 wt% Pt material, it is not essential to form the Ni layer or the Au layer on the surface by plating. Further, the inner wiring layer 2 and the through-hole wiring 2A are not required to be provided in the semiconductor device 11 if there is no need depending on the required performance.

The resin layer 10 has the following physical properties after curing: thermal expansion coefficient: 5 to 220 ppm / ° C., Young's modulus: 1 to 50 GP
a, various epoxy resins having a glass transition point: 75 to 160 ° C. can be substituted. Moreover, for example, the physical properties after curing are as follows: thermal expansion coefficient: 90 to 900 ppm / ° C., Young's modulus: 0.8 to 6.
Various RTV (Room Temperature Vulcani) with 4 MPa
zing) Rubber resin can be used instead. Further, a resin obtained by mixing the above various epoxy resins and various RTV rubber resins may be substituted.

The epoxy material as the resin layer 10 has physical properties after curing, for example, thermal expansion coefficient: 9.0 ppm / ° C., Young's modulus:
24.5 GPa, glass transition point: 150 ° C., filler addition amount: 85 wt%, as well as physical properties after curing such as thermal expansion coefficient: 14 ppm / ° C., Young's modulus: 8.8 GPa,
It is possible to replace with an epoxy resin having a Young's modulus after curing of 1 to 50 GPa and a coefficient of thermal expansion of 5 to 220 ppm / ° C. such as a glass transition point: 136 ° C. and an amount of filler added: 74 wt%. Further, as the resin layer 10, a resin composition containing a thermosetting or thermoplastic resin other than the epoxy resin composition, a filler, and the like can be used as long as it can mechanically protect mounted components or hermetically seal the components. The thermosetting resin is preferably an epoxy resin, and in this case, either liquid or solid form can be used. The liquid epoxy resin can be formed by a known method such as transfer molding. Polyphenylene sulfide (PP) as a thermoplastic resin
S), polybutene terephthalate (PBT) and the like can be formed by an injection molding method. As the epoxy resin, bisphenol A type epoxy resin, tetrabromobisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol A / F type epoxy resin, bisphenol AD type epoxy resin, phenol novolac type epoxy resin, cresol novolac type epoxy resin , Biphenyl type epoxy resin, etc. can be used.
Further, the alicyclic epoxy resin may be used alone or in combination for improving heat resistance. Examples of the alicyclic epoxy resin include 3,4-epoxycyclohexylmethyl- (3,4-epoxy) cyclohexanecarboxylate, 4- (1,2-epoxypropyl) -1,2-epoxycyclohexane, and 2- (3 , 4-epoxy) cyclohexyl-5,5-spiro (3,4-epoxy) cyclohexane-m-dioxane and the like can be mentioned. Further, as a curing agent for epoxy resin, an amine curing agent,
An acid anhydride type curing agent, a phenol resin, etc. can be used. Examples of the amine curing agent include diethylenetriamine, bis (aminomethyl) cyclohexane, diaminodiphenylmethane, diaminodiphenylsulfone and the like. Examples of the acid anhydride-based curing agent include methyltetrahydrophthalic anhydride, methylhymic acid anhydride, and nadic acid anhydride. Examples of the phenol resin include phenol novolac resin and phenol alkyl resin. The epoxy material as the resin layer 10 can be replaced with a resin having a small Young's modulus and a high coefficient of thermal expansion. For example, the physical properties after curing are as follows: thermal expansion coefficient: 14 ppm / ° C., Young's modulus: 8.8 GPa, glass transition point: 136 ° C., filler addition amount: 74 wt%, the thermal expansion coefficient after curing is 5 to 22 ppm. It is possible to replace it with an epoxy resin in the range of / ° C.

As the filler, fused silica, crystalline silica, alumina, magnesium oxide, magnesium carbonate,
Calcium carbide, dolomite, aluminum hydroxide, magnesium hydroxide, calcium fluoride, magnesium fluoride, aluminum fluoride, talc, clay, mica, etc. can be used, and the shape can be crushed, spherical or fibrous. Good. The average particle size of these fillers is 0.1 to 30.
The range of μm is preferred. The reason for this is that the particle size is 0.1 μm
If it is smaller, the viscosity becomes higher and the workability is impaired.
When the particle size is large by 30 μm, it becomes difficult to fill the narrow part. Moreover, the expansion coefficient after curing of the resin layer 10 can be adjusted to a desired range by adjusting the addition amount of the filler. That is, the thermal expansion coefficient can be decreased by increasing the filler addition amount, and can be increased by decreasing the addition amount. In addition to these, a softening agent, a flame retardant, a coloring agent, a surface treatment agent and the like can be added as required.

In the present invention, the base material of the substrate 1 can be replaced with a material other than the ceramic material. For example, it is possible to replace it with a composite resin material (glass epoxy, physical expansion coefficient: 14 ppm / ° C., Young's modulus: 170 GPa) in which glass cloth is used as a base material and epoxy is impregnated therein. Also, paper phenolic material using paper as the base material and phenolic resin as the impregnating resin, glass cloth, glass non-woven fabric as the base material, composite material using epoxy resin, polyimide, bismaleide triazine as the impregnating resin, base material It is also possible to use a glass polyimide material using glass cloth as the material and polyimide as the impregnating resin. Furthermore, a flexible printed board in which a wiring pattern is formed on a film of polyester, polyimide, polyimideamide or the like can also be used. The wirings provided on these substrates 1 are Cu and Ni, and may be a single layer or multiple layers.

The Si material for the semiconductor element substrate 6 is Ga
Ga, As, Al, typified by compound semiconductor materials such as As material (6.0 ppm / ° C.) and SiC (3.7 ppm / ° C.),
It may be replaced with a compound semiconductor containing at least one selected from the group of P, In, Sb, C and N as a main component, or a Ge material (6.0 ppm / ° C.). Also, obtained by combining these materials including Si material, for example, SiG
It may be e.

The thin metal wire 7 made of Au is Al or Si,
It is possible to replace with an Al material added with Ni.
These alternative materials, including Au materials, can be
A diameter of 100 μm can be selected.

The electrical connection of the external circuit is generally achieved by soldering on a circuit board (for example, a glass epoxy board) whose base material is a material having a different thermal expansion coefficient from that of the semiconductor device. In recent years, from the viewpoint of environmental protection, it has been desired to replace the Pb-Sn alloy material that has been conventionally applied to mounting electronic components with a Pb-free alloy. Currently, a practical Pb-free solder material is an alloy containing an overwhelmingly large amount of Sn, and its melting point is 240 ° C. or lower.
For example, Sn-5 wt% Sb solder material (melting point: 230-
The above-mentioned semiconductor device in which the semiconductor element is fixed (primary mounting soldering) by using 240 ° C is Sn-3wt% Ag-
When using 0.5 wt% Cu solder material (melting point: 221 ° C) to solder to the circuit board (secondary mounting soldering), it is necessary to heat at a temperature about 40 deg higher than the melting point to ensure the secondary mounting. is there. In such heat treatment, not only the secondary mounting solder material but also the primary mounting solder material is melted. According to the results of studies by the present inventors, the Pb-free solder material causes a volume expansion of about 16% in the process of changing from the solid phase state to the liquid phase state. The periphery of the solder material for primary mounting is sealed with resin, and this volume expansion causes a large internal pressure of 825 MPa (84.1 kgf / mm ² ). As a result, the bonding interface (resin-
(Between the ceramic plates) is peeled off, and the molten primary mounting solder material flows out through the voids created thereby, causing a short circuit between the wiring patterns. For example, when a chip component such as a capacitor and a resistor is primarily mounted, the electrodes of the chip component are short-circuited due to the same cause. Such a short circuit causes not only the semiconductor device but also the circuit function of an electronic device using the semiconductor device to disappear.

Further, when the substrate on which the chip component is mounted is a substrate whose base material is resin, a soldering material having a high melting point cannot be used as the soldering material for primary mounting. The reason for this is that the heat resistance of the resin substrate is not as high as that of the ceramic material. For example, 250 ° C for a glass epoxy substrate
When the primary mounting soldering is performed at the above temperature, quality deterioration such as deterioration (discoloration), modification (insulation deterioration), and deformation of the board itself occurs. In order to avoid this, it is necessary to use a material that can be processed at a temperature not exceeding 250 ° C. as a solder material for primary mounting. In the case of a semiconductor device that is primarily mounted with such a low melting point solder material, the outflow of the primary mounting solder material in the subsequent secondary mounting soldering, and the resulting short circuit, disconnection,
The displacement of the chip parts is further accelerated.

According to this embodiment, the above-mentioned problems are solved and a chip component as a circuit element is mounted on the substrate,
Highly reliable semiconductor device capable of preventing outflow of primary mounting solder material, short circuit, disconnection, and displacement of chip parts when mounting a semiconductor device in which mounted chip parts are resin-sealed on an external wiring board Can be provided.

(Embodiment 2) The semiconductor device 11 obtained in Embodiment 1 is mounted on the wiring board 14 and applied to the structure 15 of this embodiment shown in FIG. In the structure 15, the external wiring 13 made of a Cu material having a thickness of 25 μm provided on one surface of the wiring board 14 and the external electrode layer 3 of the semiconductor device 11 are conductively fixed to each other via the external wiring connection layer 12. It is obtained by In this case, as the external wiring connection layer 12, Sn-
3 wt% Ag-0.5 wtCu solder material (melting point: 221
C.) to fix (working temperature: 260.degree. C.).
The wiring board 14 is made of glass epoxy material (composite material in which glass fiber cloth is impregnated with epoxy resin, coefficient of thermal expansion:
The base material is a material having a different coefficient of thermal expansion from the multilayer ceramic substrate 1 in the semiconductor device 11, such as 9.0 ppm / ° C., Young's modulus: 35 GPa). The size of the wiring board 14 is 30 mm × 7 mm × 0.6 mm. Also in such a structure 15, the inner wiring layer 2 and the through-hole wiring 2A are arranged so as to be embedded in the internal region of the multilayer ceramic substrate 1.

Here, the chip parts 6 (6A, 6B), 8 and 9 housed in the semiconductor device 11 are electrically conductively fixed (first order) to the wiring pattern 4 provided on the substrate 1 by the solder layer 5. It has been soldered). The solder layer 5 is
As described in Example 1, the matrix metal 5A made of the Sn-5 wt% Sb alloy was mixed with the alumina powder (particle size: 1
μm) 5B dispersed in the composite, and the amount of alumina powder 5B added is adjusted to 50 vol%. Any of the chip parts 6, 8 and 9 is completely sealed by the substrate 1, the wiring pattern 4 and the resin layer 10, and the solder layer 5 fixing these chip parts is also the chip parts 6, 8 and 9 and the wiring pattern. 4, completely sealed by the resin layer 10.

Also in such a structure 15, the solder layer 5 is in a portion where the periphery is completely sealed by another solid substance, and the non-metal powder 5 is added to the matrix metal 5A.
The important point is that B is in a dispersed state. Since the solder layer 5 has such a structure, the semiconductor device 11 can be connected to the external wiring connection layer (Sn-3wt% Ag-0.5w).
Secondary mounting using t% Cu solder material 12 (heating temperature:
At 260 ° C.), even if the matrix metal (Sn-5 wt% Sb) 5A of the solder layer 5 is in a molten state, the alumina powder 5B is not molten and the solid state can be maintained.

The advantages or effects described in the first embodiment can be directly enjoyed in the secondary mounting process for obtaining the structure 15. Since the details have already been described, only the main points are shown to avoid duplication. (1) Due to the presence of the non-metal powder 5B that maintains the solid state, even if the solder layer 5 is remelted, its substantial volume expansion is reduced, and the internal pressure is excessively increased, peeling, molten solder material flows out, and a short circuit occurs. And the non-metallic powder 5B is clogged to prevent the molten solder material from flowing out and short-circuiting. (2) The presence of the non-metal powder 5B that maintains the solid state increases the substantial viscosity of the remelted solder layer 5, suppresses the movement of the chip component due to the application of external force, and suppresses the floating and displacement. (3) The substantial contact area of the molten solder material 5 with the peripheral material is reduced, and at the same time, the fluidity is lowered to suppress the melting of the peripheral material and the lowering of the melting point thereof.

In the structure 15, since the re-melting of the solder layer 5 is permitted by the secondary mounting heat treatment, the external wiring connection layer 1
The Sn-3 wt% Ag-0.5 wt% Cu solder material as 2 can be replaced with another metal or alloy material. For example, Pb
-12wt% Sn-8wt% Sb-1wt% Ag, Pb
-5wt% Sn, Pb-3.5wt% Sn-1.5wt%
Ag, Pb-40 wt% Sn, Pb-60 wt% Sn,
Pb-Sn alloys represented by Pb-85wt% Sn, Pb-Sn alloys containing Bi, Ag, Sb, In, Au,
An alloy material containing at least one selected from the group consisting of Zn, Cu, Pd, Mn, Mg, and P can be used. Also, from the viewpoint of environmental protection, a metal composed of Sn, or Sn, Sb, Zn, Cu, Ni, Au, Ag, P, B
i, In, Mn, Mg, Si, Ge, Ti, Zr, V,
An alloy composed of two or more kinds selected from the group of Hf and Pd can be selected. For example, Sn-3.5 wt% Ag, Sn-
S represented by 3 wt% Ag-0.8 wt% Cu
n-Ag based alloy, Sn-5wt% Sb, Sn-10wt
% Sb, Sn-5 wt% Sb-0.6 wt% Ni-0.0
Sn-Sb based alloys represented by 5 wt% P, S
Sn-Bi-based alloy represented by n-58 wt% Bi, Sn- represented by Sn-0.7 wt% Cu
Cu-based alloys, Sn-In-based alloys represented by Sn-52wt% In, Sn-Zn-based alloys represented by Sn-9wt% Zn, In represented by In-10wt% Ag -Ag alloy, and Au-20wt%
It may be replaced with an Au-Sn alloy such as represented by Sn. Also, Sn-8.5 wt% Zn-1.5 wt%
In, Sn-4wt% Ag-2wt% Zn-2wt%
Like Bi, the above-mentioned Sn system, Sn-Ag system, Sn-S
b type, Sn-Bi type, Sn-Cu type, Sn-In type, S
It is also possible to apply an alloy material in which an n-Zn-based solder material, an In-Ag-based solder material, and an Au-Sn-based solder material are arbitrarily combined. As a more preferable material among the above alloys, Sn-3
wt% Ag-0.8 wt% Cu, Sn-10 wt% S
b, Sn-0.7 wt% Cu, Sn-9 wt% Zn can be mentioned.

The wiring board 14 has physical properties such as a coefficient of thermal expansion:
It can be replaced with a glass epoxy material having 14 ppm / ° C. and Young's modulus: 170 GPa. In addition to the glass epoxy material, paper phenolic material using paper as a base material and phenolic resin as an impregnating resin, glass cloth, glass non-woven fabric as a base material, composite material using paper and epoxy resin as an impregnating resin, It is also possible to use a glass polyimide material using glass cloth as the base material and polyimide as the impregnating resin. Furthermore, a flexible printed board in which a wiring pattern is formed on a film of polyester, polyimide, polyimideamide or the like can also be used. The wiring board 14 may be a single layer or a board having a wiring pattern formed on an aluminum board provided with an organic insulating layer.

On the other hand, Pb-5 was used as the external wiring connection layer 12.
When using a high temperature solder such as wt% Sn (melting point 315 ° C.), the secondary mounting temperature must be at least the melting point 315 ° C. or higher (usually about 330 ° C.). With the above organic substrate, sufficient heat resistance cannot be expected. In this case, as the wiring board 14, glass ceramics, alumina, aluminum nitride, silicon nitride,
It is possible to use an inorganic heat-resistant wiring board using, as a base material, one kind of ceramics selected from the group consisting of glass and beryllia.

It is preferable that a wiring pattern for further connecting to an external circuit is provided on the back surface of each of the above-mentioned substrates on which the semiconductor device 11 is mounted. At this time, the wiring pattern on the back surface and the wiring pattern for mounting the semiconductor device 11 are electrically connected.

Although the external wiring 13 is provided on one surface of the wiring board 14, the external wiring 13 can be electrically connected to the opposite main surface side via the through hole wiring. . In addition, when wiring with higher density,
It is also possible to provide one or more inner wiring layers in the wiring board 14.

[0062]

[Table 1]

Table 1 is a table for explaining the defect occurrence rate of the structure of the present invention. The solder layer 5 in the semiconductor device 11 is Sn
-5 wt% Sb alloy Matrix metal 5A in which 50 vol% of alumina powder 5B is dispersed. Further, it is compared with a structure obtained by using a semiconductor device having the same structure to which an Sn-5 wt% Sb alloy to which non-metal powder is not added is applied. The defect occurrence rate of the structure 15 of the present invention is 0.00002.
%, About 1/100 of 3.45% of the structure for comparison
It has been reduced to 00. The failure mode is the loss of circuit function due to a short circuit in both structures, but in the case of the structure 15 of the present invention, the solder material 5 by addition of the alumina powder 5B is used.
The effect of preventing the outflow of water is clearly shown.

[0064]

[Table 2]

Table 2 shows the defect occurrence rate due to the disappearance of the circuit function of the structure in which the semiconductor device mounted with the chip component is connected (secondarily mounted) to the external wiring board by using the solder material to which various non-metal powders are added. The disappearance of the circuit function here is caused by the fact that the solder material 5 is remelted and flows out to cause a short circuit. When any of the non-metal powders 5B was added, the circuit function loss due to short circuit was 0.016% or less, which is far lower than 3.45% of the comparative structure (Table 1). . As the non-metal powder 5B for the solder material 5, all the substances listed in Table 2 are applicable. Further, as the non-metal powder 5B, the density of the solder material (for example, Sn: 7.3 g / cm ³ , P
b: 11.3 g / cm ³ ) It is preferable to use a non-metal powder having a density equal to or lower than that, and the relationship between the density ρ1 of the solder layer and the density ρ2 of the non-metal powder is ρ1 ≧ ρ2
It is good to By using such a non-metal powder, precipitation in the molten solder material can be prevented and the dispersibility of the non-metal powder in the solder material can be improved. Further, in the present invention, the non-metal powder 5B that can be added to the solder material 5 is not limited to the single-metal non-metal powder listed in Table 2. 2 selected from the group of oxide, nitride, boride, carbide, sulfide, phosphide, silicide, fluoride, silicon simple substance, germanium simple substance, carbon simple substance, boron simple substance
Even a mixed powder material composed of more than one kind of substance is applicable as long as it is a powder.

FIG. 7 is a graph for explaining the influence of the alumina powder particle size on the short circuit defect rate after the secondary mounting. In the case where the particle size of the alumina powder 5B is in the range of 0.05 to 10 μm, the short circuit defect rate is 0% or infinitely close to it. Therefore,
It is more preferable to select the particle size in the range of 0.05 to 10 μm. Further, the semiconductor device and the structure of the present invention are handled as mass-produced products together with the electronic device described later. In this case, it is desirable that the defective rate of each product is 0.1% (about −3σ level) from the viewpoint of stable production of the product.
Therefore, in the present invention, the short circuit defect rate up to 0.1% is within the allowable range. From this point of view, the particle size of the alumina powder 5B selected as a preferable range is from 0.05 to
It is 60 μm. The non-metal powder 5B is one kind selected from the group consisting of oxide, nitride, boride, carbide, sulfide, phosphide, silicide, fluoride, silicon simple substance, germanium simple substance, carbon simple substance and boron simple substance. Even in the case of the substance of No. 1 or a mixed powder material composed of two or more kinds of substances, the preferable particle size range is 0.05 to 60 μm, and the more preferable particle size range is 0.05 to 10 μm. is there. From the viewpoint of increasing the filling rate of the non-metal powder 5B in the solder material 5, it is desirable to add the non-metal powder 5 having various particle diameters in combination in the range of 0.05 to 60 μm.

FIG. 8 is a graph for explaining the effect of the amount of alumina powder added on the short circuit failure rate after secondary mounting. When alumina powder is not added, the short-circuit failure rate is as high as 3.5%, which exceeds the allowable failure rate (0.1%, about -3σ level). Further, even when the amount of alumina powder added is less than 3 vol%, a high short circuit failure rate is exhibited. This is because the amount of alumina powder 5B is too small to satisfy the following points. (1) Efficiently suppressing volume expansion due to remelting of the matrix metal 5A (2) Sufficiently increasing the substantial viscosity of the remelting solder material 5 (3) Substantial contact area between the molten solder material 5 and peripheral materials On the other hand, while the amount of alumina powder added is 3 vol% or more,
%, Which is below the allowable defect rate. This is because the alumina powder 5B is added in an amount sufficient to satisfy the above points (1) to (3). From this, the amount of alumina powder added is 3 to 85 from the viewpoint of preventing short-circuit defects.
A range of vol% is selected. The above tendency is common to all the matrix metals 5A and the non-metal powders 5B described above.

However, the addition amount of the alumina powder 5B must be considered from the viewpoint of the reliability of the semiconductor device 11 and the structure 15. FIG. 9 is a graph for explaining the influence of the amount of alumina powder added on the disconnection failure rate of the structure of the present invention. The disconnection failure referred to here is disconnection due to crack destruction of the solder layer 5 inside the semiconductor device 11, and the temperature cycle test is performed 1000 times at −20 to 110 ° C. When the amount of the alumina powder 5B added is in the range of 0 to 75 vol%, the disconnection failure rate is 0% or almost as close as possible, and excellent results are obtained. However, if it exceeds 75 vol%, the defect rate increases. The crack breakage occurs because as the amount of alumina powder 5B added increases, excessive strain due to temperature changes concentrates on the matrix metal 5A in the solder layer 5. When the addition amount of the alumina powder 5B is in an appropriate range, the region of the matrix metal 5A that shares the strain expands, and the concentration of excessive stress is avoided, so that cracking of the solder layer 5 is suppressed. From this, the amount of alumina powder added is 0 from the viewpoint of preventing disconnection due to crack destruction.
A range of ~ 75 vol% is selected. The above tendency is common to all the matrix metals 5A and the non-metal powders 5B described above.

As described above, from the viewpoint of preventing short circuit and disconnection, 3 to 75 vol% is selected as an appropriate addition amount of alumina powder 5B. Further, in order to obtain uniform dispersibility of the powder particles in the matrix metal, a more preferable addition amount is selected from 10 to 50 vol%.
This proper addition amount is a metal whose matrix metal 5A is made of Sn or Pb, Sn, Sb, Zn, Cu, Ni, A.
u, Ag, P, Bi, In, Mn, Mg, Si, Ge,
In the case of an alloy composed of two or more kinds selected from the group of Ti, Zr, V, Hf and Pd, the non-metal powder 5B is an oxide,
Consists of a single substance selected from the group consisting of nitride, boride, carbide, sulfide, phosphide, silicide, fluoride, silicon simple substance, germanium simple substance, carbon simple substance and boron simple substance, or two or more substances The same applies to mixed powder materials. Before mounting the chip component, the matrix metal 5A and the non-metal powder 5B are preferably in a paste state. From the viewpoint of producing a paste in which the nonmetal powder 5B is uniformly dispersed, the addition amount of the nonmetal powder 5B is preferably 5 to 30 vol%.

As described above, the structure 15 of this embodiment is one in which the semiconductor device 11 is mounted (secondary mounting soldering) on the wiring board 14 under the working temperature of 260 ° C. The defect occurrence rate of the semiconductor device 11 due to this heat treatment is 0.00032% as shown in Table 1, which is 3.45% of that of the comparative structure (Sn-5 wt% Sb alloy is applied as the solder layer, non-metal powder is not added). It is reduced to about 1/10000 compared to%. The defective mode is the loss of circuit function due to a short circuit in both structures, but in the case of the structure 15 of the present invention, the effect of preventing the outflow of the solder material 5 by adding the alumina powder 5B is clearly shown. Loss of circuit function (solder material 5
The reason is that the alumina powder 5B, which maintains the solid state even under the secondary mounting heat treatment, substantially suppresses the volume expansion of the remelted solder material 5 and causes an excessive increase in the internal pressure. This is because peeling, the outflow and short circuit of the molten solder material are suppressed, and the outflow and short circuit of the molten solder material are suppressed by the clogging phenomenon of the alumina powder 5B. Further, the alumina powder 5B that maintains the solid phase state increases the substantial viscosity of the remelted solder material 5 and contributes to suppressing outflow and short circuit. Furthermore, alumina powder 5B was used during the primary mounting.
Is molten solder material 5 (especially molten matrix metal 5A)
, The Au plating layer on the wiring pattern 4, the chip component 8,
The contact area between the Sn plating layer on the electrode 105 of No. 9 and the Au layer on the laminated metal layer 605 of the semiconductor chip 6 is narrowed,
The fact that the fusion of Sn and Sn into the solder layer 5 is suppressed also contributes.

Although the particle size of the alumina powder 5B used in this example is 1 μm, the object of the present invention can be achieved with other particle sizes. As shown in Fig. 7, the particle size is 0.
In the range of 05-60 μm, the short-circuit failure rate is 0% or as close as possible. For smaller chip parts,
The smaller particle size allows mounting without displacement. From such a viewpoint, it is more preferable to select the particle size in the range of 0.05 to 10 μm. Further, the semiconductor device 11 and the structure 15 are handled as mass-produced products together with the electronic device described later. In this case, it is desirable that the defective rate of each product is 0.1% (about −3σ level) from the viewpoint of stable production of the product. Therefore, in the present invention, the short circuit defect rate up to 0.1% is within the allowable range. From this point of view, the particle size of the alumina powder 5B selected as a preferable range is 0.05 to 60 μm. Non-metal powder 5
B is selected from the group of oxide, nitride, boride, carbide, sulfide, phosphide, silicide, fluoride, silicon simple substance, germanium simple substance, carbon simple substance, boron simple substance 1
Even in the case of a mixed powder material composed of one kind of substance or two or more kinds of substances, the preferable particle size range is 0.05 to 60.
It is the same in that the more preferable particle size range is 0.05 to 10 μm. In addition, from the viewpoint of increasing the filling rate of the non-metal powder 5B in the solder material 5, 0.05 to 60
It is desirable to combine and add the non-metal powders 5 having various particle diameters in the range of μm.

The non-metal powder 5B may have a perfect spherical shape, an indefinite spherical shape, a square shape, or a rod shape.

Although the amount of the alumina powder 5B used in this example is 50 vol%, the object of the present invention can be achieved with other amounts. As shown in FIG. 8, the short-circuit failure rate is high in the region where the amount of alumina powder added is small, and exceeds the allowable failure rate (0.1%, about -3σ level). This is because the amount of alumina powder 5B is small,
(1) Efficiently suppressing volume expansion due to remelting of the matrix metal 5A, (2) Sufficiently increasing the substantial viscosity of the remelting solder material 5, (3) Substantially the molten solder material 5 and peripheral materials This is because the contact area cannot be sufficiently exerted in terms of making it small enough.

On the other hand, the amount of alumina powder added is 3 to 85 vol%
In the range of 0, it is less than the allowable defect rate of 0%. This is based on the fact that the alumina powder 5B is added in an amount sufficient to fulfill the functions (1) to (3). Therefore, the amount of alumina powder added is selected in the range of 15 to 85 vol% from the viewpoint of preventing short circuit failure. The above tendency is common to all the matrix metals 5A and the non-metal powders 5B described above.

On the other hand, the addition amount of the alumina powder 5B must be taken into consideration from the viewpoint of the reliability of the semiconductor device 11 and the structure 15. As shown in FIG. 9, the failure rate of disconnection of the structure 15 (disconnection due to crack destruction of the solder layer 5 inside the semiconductor device 11, temperature cycle test: -20 to 110)
Amount of alumina powder 5B is 0 to 75
Excellent results have been obtained at or near 0% in the range of vol%. However, if it exceeds 75 vol%, the defect rate increases. The crack breakage occurs because as the amount of alumina powder 5B added increases, excessive strain due to temperature changes concentrates on the matrix metal 5A in the solder layer 5. When the addition amount of the alumina powder 5B is in an appropriate range, the region of the matrix metal 5A that shares the strain expands, and the concentration of excessive stress is avoided, so that cracking of the solder layer 5 is suppressed. Therefore, from the viewpoint of preventing disconnection due to crack destruction, the amount of alumina powder added is 0 to
A range of 75 vol% is selected. The above tendency is common to all the matrix metals 5A and the non-metal powders 5B described above.

As described above, from the viewpoint of preventing short circuit and disconnection, 3 to 75 vol% is selected as an appropriate addition amount of the alumina powder 5B. Further, in order to obtain uniform dispersibility of the powder particles in the matrix metal, a more preferable addition amount is selected from 10 to 50 vol%.
This proper addition amount is a metal whose matrix metal 5A is made of Sn or Pb, Sn, Sb, Zn, Cu, Ni, A.
u, Ag, P, Bi, In, Mn, Mg, Si, Ge,
In the case of an alloy composed of two or more kinds selected from the group of Ti, Zr, V, Hf and Pd, the non-metal powder 5B is an oxide,
One substance selected from the group consisting of nitride, boride, carbide, sulfide, phosphide, silicide, fluoride, silicon simple substance, germanium simple substance, carbon simple substance, and boron simple substance, or a mixture of two or more kinds of substances The same applies to powder materials.

FIG. 14 is a graph for explaining the short circuit failure rate of the structure obtained by applying the semiconductor device exposed to the high temperature and high humidity atmosphere. Here, Sample A is a structure 1 obtained by subjecting the semiconductor device 11 to a high temperature and high humidity atmosphere (85 ° C., 85% RH) for 500 hours and then performing secondary mounting soldering at 260 ° C.
5, Sample B is a structure 15 obtained by performing the above secondary mounting without exposing the semiconductor device 11 to a high temperature and high humidity atmosphere, and all are the structures 15 of the present embodiment. Sample C is a comparative example structure obtained by performing secondary mounting of the semiconductor device 11 which was primarily mounted with a solder material to which non-metal powder was not added and which was not exposed to a high temperature and high humidity atmosphere. The short-circuit failure rate of sample A is 0.0048%, which is almost the same as that of sample B (0.00032%).
The yield is overwhelmingly better than (3.45%).
When the semiconductor device 11 is exposed to a high temperature and high humidity atmosphere,
Water penetrates inside through the resin layer 10. This moisture reduces the bonding force at the contact interface between the chip components 6, 8, 9, the wiring pattern 4, the substrate 1 and the resin layer 10, and the interface is peeled due to remelting and volume expansion of the solder material 5 accompanying secondary mounting soldering. Is likely to occur. However, the result of the sample A shows that the solder material 5 is
There is no outflow or short circuit. Alumina powder 5
This is the effect of the addition of B.

The structure 15 of this example was put into a temperature cycle test of −20 to 110 ° C. together with the structure of the comparative example.
Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. In the test up to 2000 times, the structure 15 of the present embodiment did not show a defect due to the disappearance of the circuit function of the semiconductor device 11. On the other hand, the structure of the comparative example did not lose the circuit function after the test was performed up to 2000 times. These test results show that even when the non-metal powder 5B is added to the solder layer 5,
It suggests that the connection reliability of is comparable to that without the addition of non-metal powder.

Example 3 Structure 15 obtained in Example 2
Was applied to a lithium-ion secondary battery as the electronic device 100 shown in FIG. The electronic device (secondary battery, external size: 60 mm × 30 mm × 8 mm) 100 has the following configuration. A bottomed prismatic metal case (size: 55 mm × 29 mm × 7 mm) 20 made of stainless steel is used to store the positive electrode active material, negative electrode active material, positive electrode current collector, negative electrode current collector, separator, organic electrolyte, etc. The next battery element is stored. In this battery, LiCoO ₂ is used as the positive electrode active material, and carbon having a graphite structure is used as the negative electrode active material. The positive electrode active material is held by a positive electrode current collector made of Al, and the negative electrode active material is held by a negative electrode current collector made of Cu. A separator is arranged between the positive electrode active material and the negative electrode active material, and is filled with the organic electrolytic solution. A metal lid 21 having a concave cross section is fitted in the opening of the metal case 20 that serves as the negative electrode of the secondary battery. A positive electrode 23 is provided at the center of the metal lid 21 with an insulating layer 22 made of a glass material interposed therebetween. In addition, a safety valve 24 is provided in a predetermined hole of the metal lid 21.
Is attached. A flexible printed circuit board 25 made of polyimide and provided with Cu wiring (not shown) in a space formed by the metal lid 21 and the metal case 20.
Then, the structure 15 in which the semiconductor device 11 is mounted on the wiring board 14 is mounted. As will be described later, the semiconductor device 11 is provided with a protection circuit for preventing over-discharge, over-charge and over-current and for preventing overheating of the secondary battery element.

The reason for suppressing overcharge and overdischarge of the secondary battery is as follows. For example, when a lithium-ion secondary battery is over-discharged above a predetermined battery voltage, lithium metal is deposited on the negative electrode, the positive electrode active material is decomposed, the organic electrolyte is decomposed, and the positive and negative electrodes are short-circuited and the battery performance is deteriorated. It causes such as. Therefore, overcharge of the secondary battery must be avoided. On the contrary, when the lithium-ion battery is over-discharged below the specified battery voltage, the metal of the negative electrode current collector is ionized and eluted in the organic electrolyte solution, which deteriorates the current collecting function and causes the negative electrode active material to fall off, resulting in a capacity loss. Cause a decline. This is the reason why over-discharge must be suppressed.

The flexible printed board 25 is provided with a positive electrode external terminal 35, a negative electrode external terminal 36 and a ground terminal 37. The positive electrode external terminal 35 is connected to the metal case 20 via the connecting portions 30 and 31, the structure 15, and wiring (not shown) on the flexible printed board 25. Flexible printed circuit board 25 and structure 1
In the wiring board 14 of No. 5, holes 34 and 38 are formed at positions corresponding to the safety valve 24, respectively. An insulating plate 27 having holes 26 at positions corresponding to the external terminals 35, 36, 37 is arranged on the flexible printed board 25. An insulating plate 28 is also arranged on the bottom surface side of the metal case 20. The outer surfaces of the insulating plate 27, the metal case 20 and the insulating plate 28 are covered with a heat shrinkable tube 29.
A charger or an electronic device (for example, powering a mobile phone or a personal computer) is connected between the positive electrode external terminal 35 and the negative electrode external terminal 36 for practical use.

An important point in obtaining the electronic device 100 of the present embodiment is that in the secondary mounting soldering in which the semiconductor device 11 is mounted on the wiring board 14, the outflow of the remelted solder material 5 and the resulting short circuit are avoided. This is the point where the structure 15 obtained as a result is mounted.

The electronic device (lithium ion secondary battery) 100 of this embodiment having the above-described structure is the semiconductor device 1 shown in FIG.
Built-in circuit 1. An integrated circuit element 6A, an FET element 6B, chip resistors 8A and 8B, and a chip capacitor 9 are mounted on the semiconductor device 11. An FET element 6B composed of an overdischarge prevention FET element 61 and an overvoltage prevention FET element 62 is connected between a metal case (also serving as a negative electrode) 20 accommodating the secondary battery element and the negative electrode external terminal 36. ing. When an overvoltage is applied between the positive electrode 23 and the metal case 20, the integrated circuit element 6A will be turned off by the FET element 62A.
Turn off. This prevents overcharging. Also,
The integrated circuit element 6A turns off the FET element 61 when the voltage between the positive electrode 23 and the metal case 20 drops below a predetermined voltage due to overdischarge. This prevents overcurrent.

Conventionally, a discrete type element has been used as an element of a protection circuit mounted on a secondary battery such as a lithium ion secondary battery, so that there is a limit to downsizing of the protection circuit. A lithium-ion secondary battery, which is an example of the electronic device of the present invention, uses a semiconductor device in which a chip component as a circuit element is mounted on a wiring board and the mounted chip component is resin-sealed as a protection circuit. . Therefore, in the lithium ion secondary battery of the same size, the size of the conventional metal case 20 was 50 mm × 29 mm × 7 mm, whereas the size of the metal case 20 of this embodiment was 55 mm × 29 mm × 7 mm. became. Therefore, the volume occupied by the protection circuit in the secondary battery is reduced, and the occupied capacity of the battery element can be increased. As a result, the capacity of the secondary battery can be increased, and the operating time of the lithium ion secondary battery is increased by 1.1 times.

The electronic device 100 has chip parts 6, 8 and 9 as circuit elements mounted on the multilayer ceramic substrate 1, and the mounted chip parts are sealed with a resin layer 10.
A semiconductor device 11 that is small, lightweight, thin, and suitable for mass production and surface mounting, and the semiconductor device 11 on the external wiring board 14
The structure 15 in which the solder material is prevented from flowing out and short-circuited during the next mounting is housed. Accordingly, the electronic device 100
High reliability, high performance, high volumetric efficiency, and high density mounting are possible.

Examples of the electronic equipment include a mobile telephone, a portable radio telephone device, a portable personal computer,
Examples include portable video cameras. Even in the electronic device 100 in which the semiconductor device 11 or the structure 15 of the present invention is mounted on these electronic devices, effects such as miniaturization, high reliability, and high performance can be obtained.

(Embodiment 4) In the present embodiment, as the multilayer ceramic substrate 1, the inner wiring layer 2, in which W is dispersed in Cu, is used.
Through-hole wiring 2A, external electrode layer 3, wiring pattern 4
Expansion coefficient: 7.0 ppm / ° C, thermal conductivity: 15.2
W / mK, bending strength: 0.4 GPa, Young's modulus: 30
A semiconductor device 11 was manufactured using an alumina substrate having characteristics of 0 GPa and wiring resistance (sheet resistance): 4 mΩ / □.
At this time, chip parts 6, 8 and 9 are first mounted and soldered
As a solder material 5 for (240 ° C.), Pb-50w
Non-metal powder (particle size: 2.0 to 20 μm, addition amount: 35 vo) made of a mixture of silicon carbide (SiC) and silicon nitride (Si ₃ N ₄ ) on a matrix metal 5A made of a t% Sn alloy.
1%) 5B was used as the composite material. The structure of members other than the multilayer ceramic substrate 1 and the solder material 5 and the manufacturing process including secondary mounting soldering are the same as those in the first embodiment. The semiconductor device having the above-described configuration has the same performance, advantages, and effects as those of the first embodiment.

The semiconductor device 11 was secondarily mounted and soldered on the wiring board 14 and housed in the structure 15. The structure 15 was applied to the lithium ion secondary battery as the electronic device 100. Also in these cases, the structure of members other than the multilayer ceramic substrate 1 and the solder material 5 is the same as in the second and third embodiments. As a result, the same excellent performance as in Examples 2 and 3 was obtained. In particular, the short-circuit failure rate of the structure 15 was as low as 0.0004%, and the yield was excellent as an electronic component for mass-produced products. This is because the mixed powder 5B of silicon carbide (SiC) / silicon nitride (Si ₃ N ₄ ) added to the solder material 5 acted effectively in suppressing the volume expansion and outflow of the matrix metal 5A. Further, the structure 15 of the present example was subjected to the temperature cycle test of −20 to 110 ° C. As a result, the structure 15 did not show a defect due to the disappearance of the circuit function of the semiconductor device 11 in the test up to 2000 times. .

Also, the occupied volume of the protection circuit housed in the lithium ion secondary battery 100 was reduced as in the third embodiment. As a result, the size of the conventional metal case 20 is 50
The size of the metal case 20 of the present embodiment could be increased to 55 mm × 29 mm × 7 mm, while the size was mm × 29 mm × 7 mm. Therefore, by increasing the occupied capacity of the battery element, it was possible to achieve a higher capacity of the secondary battery and to increase the operable time of the lithium ion secondary battery by 1.1 times.

Example 5 The semiconductor device 1 obtained in Example 4
1 was directly mounted on the flexible printed circuit board 25 to obtain a lithium ion secondary battery as the electronic device 100. Also in this case, the member structure is the same as that of the fourth embodiment except that the external wiring board 14 is not used. As a result, the size of the conventional metal case 20 is 50 mm × 29 mm ×
It was possible to increase the size of the metal case 20 of this embodiment to 55 mm × 29 mm × 7 mm, while it was 7 mm. Therefore, by increasing the occupied capacity of the battery element, it was possible to increase the capacity of the secondary battery and to increase the operable time of the lithium ion secondary battery by 1.1 times.

(Embodiment 6) In this embodiment, a semiconductor device 11 having a power multiplication circuit is obtained. FIG. 15 shows a circuit block diagram of a power multiplication circuit device as a semiconductor device of this embodiment. The semiconductor device 11 includes a Hall effect element 70, a voltage conversion circuit 75, and a voltage-current conversion circuit 76. The chip parts constituting these circuits have wirings in which W is dispersed in Cu, thermal expansion coefficient: 7.0 ppm / ° C., thermal conductivity: 15.2 W / m · K, bending strength: 0.4 GPa,
Young's modulus: 300 GPa, wiring resistance (sheet resistance):
Primary mounting soldering was carried out in the same manner as in Example 1 on the multilayer ceramic substrate 1 made of alumina of 4 mΩ / □. In this soldering, Sn-3wt% Ag-0.5
A solder material 5 in which zirconia (ZrO ₂ ) powder (particle size: 1.0 to 40 μm, addition amount: 45 vol%) 5B was dispersed in a matrix metal 5A made of a wt% Cu alloy was used. Thereafter, the same wire bonding, resin molding, and individualized dividing steps as in Example 1 were performed. The size of the semiconductor device 11 is reduced to 15 mm × 10 mm × 1.2 mm.

The semiconductor device 11 obtained as described above is prepared by depositing Sn-- on the polyimide sheet 14 provided with the Cu wiring layer 13.
Secured by the external wiring connection layer 12 made of 3 wt% Ag-0.5 wt% Cu alloy (secondary mounting soldering: 260
℃) was. The structure 15 thus obtained is subjected to secondary mounting soldering after being exposed to a high temperature and high humidity atmosphere (85 ° C., 85% RH) for 500 hours. This structure 1
The short circuit failure rate of No. 5 was 0.0038%, which was an excellent yield. As a result, even if moisture has penetrated into the interior through the resin layer 10, the chip components, the wiring patterns 4,
Without reducing the bonding force at the contact interface between the substrate 1 and the resin layer 10, the interface does not separate even when the solder material 5 is remelted and volume-expanded due to the secondary mounting soldering, and the solder material 5 flows out or short-circuits. Suggest not. This is the effect of adding the zirconia powder 5B.

The structure 15 of the present embodiment is replaced with -40 to 125.
It was put into a temperature cycle test of ° C. Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. In the test up to 2000 times, the structure 15 of the present embodiment did not show any defect due to the disappearance of the circuit function of the semiconductor device 11. These test results suggest that excellent connection reliability can be maintained even when the zirconia powder 5B is added to the solder layer 5.

FIG. 16 shows a block diagram of the magnetic field generator. The magnetic field generation unit includes a magnetic core 84, a current coil 85 wound around the core 84, a magnetic field gap 86, a semiconductor device 11 in which the Hall effect element 70 is housed in the magnetic field gap 86, and the semiconductor device 11 on the wiring board 14. Structure 1 secondarily mounted on
It is composed of 5.

The function of the semiconductor device 11 will be described below with reference to FIG.
This will be described using 5 and 16. The power supply voltage of the measured system input to the input terminals 73 and 74 is input to the voltage-current conversion circuit 76 via the voltage conversion circuit 75 including the resistors 71 and 72. The voltage-current conversion circuit 76 outputs a current proportional to the input voltage to the control current terminal 77 of the Hall effect element 70. On the other hand, the current of the system under measurement is input to the current coil 85, and a magnetic field proportional to the input current is generated in the gap 86,
Hall electromotive force is generated at the voltage output terminals 79 and 80 of the Hall effect element 70, which are arranged so as to be orthogonal to the magnetic field of the gap 86 and the flow direction of the control current of the Hall effect element 70. The variable resistor 81 is for compensating the offset voltage generated due to the asymmetry of the characteristics of the Hall effect element 70, is connected between the voltage output terminals 79 and 80, and the movable terminal 78 is grounded. The output is output from the output terminals 82 and 83 to the outside.

The magnetic field generator having the above-described structure was used for a power multiplication circuit in a power meter or a power meter. These wattmeters and watthour meters are downsized and lightened, and their structures are simplified.

(Embodiment 7) In the present embodiment, the semiconductor device 11 and the semiconductor device 1 as the high frequency power amplifier (high frequency power module) used in the transmitting section of the cellular telephone or the like.
1 using structure 1, mobile phone 1 using structure 15
I got 00.

FIG. 17 is a schematic sectional view illustrating a high frequency power module which is a semiconductor device of this embodiment. The semiconductor device (8 mm × 12.3 mm × 2.7 mm) 11 of this embodiment has the following configuration. Multilayer glass-ceramic substrate 1
Has a thermal expansion coefficient of 6.2 ppm / ° C. and a thermal conductivity of 2.5 W / m.
・ K, Bending strength: 0.25 GPa, Young's modulus: 110 GP
a, Dielectric constant: 5.6 (1 MHz). Board 1
The inner wiring layer (Ag-1 wt%
Pt) 2, blind type via (Ag-1 wt% Pt, diameter: 0.14 mm) 40, thermal via (Ag-1 wt%)
Pt, diameter: 0.14 mm) 41, through-type via (Ag-1w)
t% Pt, diameter: 0.14 mm) 42, respectively. On the first main surface 1A of the substrate 1, the wiring pattern (A
g-1 wt% Pt, thickness: 0.015 mm) 4. This wiring pattern 4 has chip resistance (about 7ppm
/ ° C.) 8 and chip capacitor (about 11.5 ppm / ° C.) 9 are electrically conductively fixed by the solder layer 5 (primary mounting soldering). A cavity 43 is provided on the first main surface 1A, and a wiring pattern 4 provided on the bottom thereof.
A semiconductor element substrate (Si, which includes an integrated circuit element substrate 6A (not shown) and an FET element substrate 6B (not shown) on the top)
3.5 ppm / ° C) 6 conductively fixed by the solder layer 5 (1
Next mounting is soldered). As shown in FIG. 2, the solder layer 5 includes Pb-12 wt% Sn-8 wt% Sb-.
Matrix metal 5A made of 1 wt% Ag alloy (melting point: 238 ° C.) and silicon nitride powder (particle size: 0.1 to 1 μm)
5B is composed of a composite in which silicon nitride powder 5
The amount of B added is adjusted to 20 vol%. Further, a metal thin wire 7 made of Au is bonded between the semiconductor element substrate 6 and a predetermined portion of the wiring pattern 4 (integrated circuit element substrate 6
A: diameter 27 μm, FET element substrate 6B: diameter 50 μm
m) has been done. These chip parts and thin metal wires 7,
The first main surface 1A is completely shielded from the outside air by the gel resin layer (the physical properties after curing are thermal expansion coefficient: 210 ppm / ° C., Young's modulus: 0.62 MPa, glass transition point: −42 ° C.) 10. It is sealed. In addition, mounted chip parts 6,
8, 9 and the resin layer 10 are sealed around the substrate 1 and a metal cap (thickness: 0.15 mm) 44 fitted therein. The metal cap 44 is for shielding electromagnetic noise. An external electrode layer (Ag-1 wt% Pt, thickness: 0.015 mm) was formed on the second main surface 1B of the substrate 1.
3 is provided.

The gel resin layer 10 has the following physical properties after curing: thermal expansion coefficient: 200-9600 ppm / ° C., Young's modulus: 90 Pa.
It is possible to substitute with various gel resins having ˜11 GPa and penetration: 55-90 (1/10 mm).

FIG. 18 is a circuit diagram of the semiconductor device of this embodiment. The input signal is amplified and output in three stages.

In this embodiment, P is used as the solder layer 5.
A comparative semiconductor device having chip parts 6, 8 and 9 mounted thereon was also manufactured using an alloy composed of b-12 wt% Sn-8 wt% Sb-1 wt% Ag alloy. Here, except for the solder layer 5, all have the same member configuration as the semiconductor device 11 of this embodiment.

FIG. 19 is a schematic sectional view illustrating a structure for a mobile phone. The structure 15 is the same as the semiconductor device 11 described above.
External wiring board (glass epoxy material, 15mm x 20mm x
1.2 mm, coefficient of thermal expansion: 14.0 ppm / ° C, Young's modulus: 17
0 GPa) 14 and is secondarily mounted and soldered. The external wiring 13 made of a Cu layer having a thickness of 25 μm is provided on the external wiring substrate 14, and the external electrode layer 3 of the semiconductor device 11 is provided on the external wiring 13 with the external wiring connection layer 12
Is fixed by secondary mounting soldering (working temperature: 260 ° C.) using Sn-3.5 wt% Ag (melting point: 221 ° C.). Here, the above-mentioned comparative semiconductor device was obtained in the same manner.

FIG. 20 is a circuit block diagram of a mobile phone to which the structure of this embodiment is applied. Input audio signal is mixer 5
At 0, it is converted into a high frequency signal from the oscillator 51, and is emitted as a radio wave from the antenna through the structure 15 of this embodiment, which is a power amplifier, and the antenna duplexer 52. The transmission power is monitored by the combiner and is kept constant by the control signal to the structure 15 of the present embodiment, which is a power amplifier. Here, the antenna duplexer 52 and the antenna are loads referred to in the present invention.

The portable telephone having the above-mentioned structure is downsized and lightened, and the structure is simplified.

FIG. 21 is a graph explaining the disconnection defect rate and the thermal resistance increase defect rate of the structure of this example. here,
Sample A is the structure 1 of this embodiment to which the semiconductor device 11 is applied.
5 and Sample B are comparative structures obtained by secondarily mounting comparative semiconductor devices. The disconnection defect referred to here is that the chip components 8 and 9 float up in the Y direction or move (shift in position) in the X direction due to the thermal deformation of the resin layer 10, as described in FIG. 3D. The solder layer 5 is cut by
This is a state in which the electrode 105 and the wiring pattern 4 are electrically disconnected. In addition, the thermal resistance increase defect is shown in FIG.
As described in (c), the semiconductor element substrate 6 (6A, 6B) is lifted in the Y direction due to the thermal deformation of the resin 10, and the peripheral portion of the solder layer 5 is narrowed accordingly. Is a state in which the heat resistance is impaired (the thermal resistance after secondary mounting and soldering reaches twice the thermal resistance after primary mounting and soldering). The failure rate of disconnection of sample A is 0.0031% and the failure rate of increase in thermal resistance is 0.000.
25%, which is far superior to the sample B disconnection failure rate: 1.64% and the thermal resistance increase failure rate: 1.86%. Silicon nitride powder 5B is added to the solder layer 5 of Sample A, and the presence of this powder 5B substantially increases the viscosity of the remelted solder material 5 (more accurately, the matrix metal 5A). As a result, even if the resin 10 is thermally deformed, the chip components 8 and 9 are prevented from being lifted or displaced, and a disconnection state is avoided. Further, since the semiconductor element substrate 6 (6A, 6B) is also prevented from rising, the peripheral edge of the solder layer 5 is not narrowed and the heat dissipation of the semiconductor element substrate 6 is maintained. On the other hand, in the case of Sample B, since the non-metal powder is not added to the solder layer, the viscosity of the remelted solder material decreases. As a result, the chip components 8 and 9 are lifted or displaced, and the semiconductor element substrate 6 (6A, 6B) is lifted, resulting in a disconnection state or a thermal resistance increase state. As described above, the fact that the defect occurrence rate of the structure 15 of the present embodiment is significantly reduced is due to the addition of the silicon nitride powder 5B to the solder layer 5.

The structure 15 of this example was put into a temperature cycle test of −40 to 125 ° C. together with the structure for comparison. Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. In the test up to 2000 times, the structure 15 of the present embodiment did not show any defect due to the disappearance of the circuit function of the semiconductor device 11. On the other hand, the structure of the comparative example did not lose the circuit function after the test was performed up to 2000 times. These test results suggest that even when the silicon nitride powder 5B is added to the solder layer 5, the connection reliability of the solder layer 5 is comparable to that when the non-metal powder is not added.

(Embodiment 8) In the present embodiment, in Embodiment 7
The result of using "non-metal powder with metal coating" in which the surface of the non-metal powder is coated with a metal film is described as the non-metal powder 5B.

Alumina (Al ₂ O ₃ ) powder (particle size: 1.0 to 3.0 μm) was selected as the non-metal powder, and Ni was selected as the coating metal. Ni coating on the alumina powder was performed by electroless plating, and the average film thickness was 0.1.
5 μm was obtained. As shown in FIG. 2, Pb-12 wt%
Sn-8 wt% Sb-1 wt% Ag alloy (melting point: 238
This Ni-coated alumina powder was added to matrix metal 5A composed of (° C.). The particle diameter of the Ni-coated alumina powder 5B is 1.5 to 3.5 μm, and the addition amount is 20 vol%. Using this powder 5B, a semiconductor device 11 as a high-frequency power amplifier (high-frequency power module) used in a transmitter of a cellular telephone or the like, and a structure 15 using the semiconductor device 11 were obtained.

A structure in which three types of semiconductor devices, that is, the semiconductor device 11 of this embodiment, a comparative semiconductor device to which uncoated alumina powder-added solder is applied, and a comparative semiconductor device to which solder without powder addition is applied, are secondarily mounted. Samples A, B, and C were compared with each other. As shown in Table 3, the disconnection failure rate was 0.0011 for each of Samples A and B.
%, 0.0015%, and the thermal resistance increase defect rate is sample A, B
Sample C with 0.0021% and 0.026%, respectively
(Disconnection failure rate: 1.64%, thermal resistance increase failure rate: 1.86
%), Which was far superior to that of%). In addition, in the samples A and B, the sample A has a slight disconnection defect,
There are few defects with increased thermal resistance.

[0110]

[Table 3]

The sample A of the structure 15 of the present example is the same as the samples B and C of the structure for comparison (the structure to which the uncoated alumina powder is added and the structure to which the powder is not added). It was put into a temperature cycle test of 40 to 125 ° C. Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. In the test up to 2000 times, the structure 15 of the present embodiment did not show any defect due to the disappearance of the circuit function of the semiconductor device 11. On the other hand, the structure of the comparative example did not lose the circuit function after the test was performed up to 2000 times. This test result is
The connection reliability of the non-metal powder-added solder layer 5 is comparable to that when no non-metal powder is added, and the connection reliability of the non-metal powder-added solder layer 5 depends on the presence or absence of a metal coating on the non-metal powder 5B. Suggest that it will not be done.

Further, the number of test cycles was extended to 3000 and the temperature cycle limit life of these structures was confirmed. Sample A: about 2700 cycles, sample B: about 2400 cycles, sample C: about 2800 cycles. It becomes a cycle, and about 300 between the samples A and B to which the powdered solder is applied
There was a cycle difference. This test result is explained by the difference in wettability between the matrix metal 5A and the non-metal powder 5B. That is, the presence of the coating metal improves the wettability of the matrix metal 5A and the non-metal powder 5B. As a result, the bonding strength at the interface between the matrix metal 5A and the non-metal powder 5B is increased, and the possibility of crack breakage of the matrix 5A with the interface as a starting point can be reduced.

As the non-metal powder 5B, oxide, nitride, boride, carbide, sulfide, phosphide, silicide,
One substance selected from the group consisting of fluoride, silicon simple substance, germanium simple substance, carbon simple substance, and boron simple substance, or 2
It may be a mixed powder material composed of more than one kind of substance.

As a metal coating method for the non-metal powder 5B, a wet plating method (for example, an electroless plating method) is used.
Known methods such as dry plating and dry plating (as an example, physical vapor deposition method) can be appropriately used. The metal to be coated may be basically any metal as long as it can ensure wettability with the matrix metal 5A. Specific examples include Ni, Cu, Au, Ag, Pd, Zn and S.
n, Pt are mentioned. The thickness of the coating metal is not particularly limited as long as the wettability can be secured, but it is preferably 0.001 to 20 μm, more preferably 0.5 to 3
It is in the range of μm.

A cellular phone 100 was obtained using the structure 15 in this example.

(Embodiment 9) In the present embodiment, a semiconductor device 11 as a high-frequency power amplifier (high-frequency power module) of another form used for a transmitter of a cellular telephone or the like, a structure 15 using the semiconductor device 11, and a structure. A mobile phone 100 using the body 15 was obtained.

FIG. 22 is a schematic sectional view for explaining a high frequency power module as the semiconductor device of this embodiment. In the semiconductor device (8 mm × 12.3 mm × 2.5 mm) 11 of the present embodiment, as the resin layer 10, a resin layer whose main component is an epoxy material (the physical properties after curing are thermal expansion coefficient: 9.0 ppm / ° C.). , Young's modulus: 24.5 GPa, glass transition point: 150 ° C., filler addition amount: 85 wt%). The configuration of members other than the resin layer 10 is the same as that of the semiconductor device manufactured in Example 7, and has the circuit shown in FIG.

In the present embodiment, P is used as the solder layer 5.
A comparative semiconductor device having chip parts 6, 8 and 9 mounted thereon was also manufactured using an alloy composed of b-12 wt% Sn-8 wt% Sb-1 wt% Ag alloy. Here, except for the solder layer 5, all have the same member configuration as the semiconductor device 11 of the present embodiment.

FIG. 23 is a schematic sectional view illustrating a structure for a mobile phone. The structure 15 is the same as the semiconductor device 11 described above.
External wiring board (glass epoxy material, 15mm x 20mm x
1.2 mm, coefficient of thermal expansion: 14.0 ppm / ° C, Young's modulus: 17
0 GPa) 14 and is secondarily mounted and soldered. The external wiring 13 made of a Cu layer having a thickness of 25 μm is provided on the external wiring substrate 14, and the external electrode layer 3 of the semiconductor device 11 is provided on the external wiring 13 with the external wiring connection layer 12
Is fixed by secondary mounting soldering (working temperature: 260 ° C.) using Sn-3.5 wt% Ag (melting point: 221 ° C.). Here, the above-mentioned comparative semiconductor device was obtained in the same manner. The structure 15 of the present embodiment having the above configuration was applied to a mobile phone having the circuit shown in FIG.

The mobile phone 100 obtained by using the structure 15 having the above-mentioned structure is downsized and lightened, and the structure is simplified.

The defect that occurs in the structure sealed with the resin layer 10 having a high Young's modulus such as the semiconductor device 11 or the structure 15 of this embodiment is a short circuit due to the outflow of the remelted solder material 5, As described above, the defect due to the positional shift disconnection and the increase in the thermal resistance due to the lifting, which is seen in the structure sealed by the resin layer having a high thermal expansion coefficient and a high Young's modulus, does not occur. Further, the short-circuit failure rate of the structure 15 of this example is 0.0004.
It is as low as 3%, which is far superior to 2.75% of the structure for comparison. This is based on the same effect as that of the second embodiment by the silicon nitride powder 5B added to the solder layer 5.

(Embodiment 10) In this embodiment, a semiconductor device 11 using a wiring board 1 having a resin as a base material will be described.

FIG. 24 is a schematic sectional view for explaining the semiconductor device of this embodiment. The semiconductor device 11 is configured as follows. Multi-layer glass epoxy board (30mm × 7mm ×
The inner wiring layer (Cu, thickness: 15)
μm) 2 and through-hole wiring (Cu, plating formation) 2
A is provided. A wiring pattern (Cu, thickness: 25 μm, Ni plating having a thickness of 5 μm and Au plating having a thickness of 1 μm are sequentially formed) 4 is provided on the first main surface 1A of the substrate 1, and the wiring pattern 4 is integrated on the wiring pattern 4. Circuit element base 6A
(Not shown) and semiconductor element substrate (Si, 3.5 ppm / ° C.) including FET element substrate 6B 6, chip resistance (about 7 ppm)
/ ° C.) 8 and capacitors (about 11.5 ppm / ° C.) 9 are electrically conductively fixed by the solder layer 5 (primary mounting soldering, working temperature: 270 ° C.). Solder layer 5 is a matrix metal 5A made of Sn-5 wt% Sb alloy.
Silica (SiO ₂ ) powder (particle size: 2-10 μm) 5B
And the amount of silica powder 5B added is adjusted to 35 vol%. A thin metal wire 7 made of Au is bonded (integrated circuit element substrate 6A: diameter 27 μm, FET element substrate 6B: diameter 50 μm) between a predetermined portion of the semiconductor element substrate 6 and the wiring pattern 4. These chip parts and thin metal wires 7 and the first main surface 1
A is a resin layer whose main component is an epoxy material (physical properties after curing include thermal expansion coefficient: 9.0 ppm / ° C, Young's modulus: 24.5 GP
a, glass transition point: 150 ° C., filler addition amount: 85 wt
%) 10 so as to be completely shielded from the outside air. This resin layer (Dimension: 10.5 mm x 4 mm x 0.8
mm) 10 is formed by the potting method.
An external electrode layer (Cu, thickness: 25 μm, Ni plating with a thickness of 5 μm and Au plating with a thickness of 1 μm are sequentially formed) 3 is formed on the second main surface 1B opposite to the first main surface 1A of the substrate 1. It is provided. The external electrode layer 3 is electrically connected to the wiring pattern 4 by relaying the inner wiring layer 2 and the through-hole wiring 2A provided inside the substrate 1. Chip parts 6,
Since the electrodes 8 and 9 are conductively fixed on the wiring pattern 4 by the solder layer 5, the external electrode layer 3 is also electrically connected to these chip components. As described above, any chip component is completely sealed by the substrate 1, the wiring pattern 4, and the resin layer 10, and the solder layer 5 that fixes these chip components is also chip components 6, 8, 9, It is completely sealed by the wiring pattern 4 and the resin layer 10.

Before the semiconductor device 11 is manufactured, the multilayer glass epoxy substrate 1 has a frame shape (8 pieces are taken), and the chip parts 6, 8 and 9 are mounted, wire bonding and resin molding are performed. After completion, it is singulated by cutting with a rotating blade. The external electrode layer 3 does not necessarily have to be formed on the second main surface 1B side, and may be formed on the first main surface 1A side as necessary.

According to the semiconductor device 11 described above,
The solder layer 5 includes a matrix metal 5A made of Sn-5 wt% Sb alloy, silica powder (particle size: 2 to 10 μm) 5B.
Since it is composed of a composite in which
Even if remelting occurs in the next mounting soldering, it is possible to prevent the matrix metal 5A from flowing out and the resulting short circuit.

(Embodiment 11) In this embodiment, Embodiment 10 will be described.
A structure 15 in which a metal member is connected to the semiconductor device 11 obtained in the above will be described.

FIG. 25 is a schematic sectional view illustrating the structure of this example. The external electrode layer 3 of the semiconductor device 11 has Sn-3 wt% Ag-0.5 as the external wiring connection layer 12.
Ni plate using wtCu solder material (melting point: 221 ° C)
(10 mm × 3 mm × 0.4 mm) 55 is fixed (secondary mounting soldering, working temperature: 260 ° C.). This Ni plate 5
Reference numeral 5 has a role of a wiring member for electrically connecting the semiconductor device 11, the metal case (also serving as the negative electrode) 20 housing the secondary battery element, and the positive electrode 23 (see FIG. 10). . Even if the member connected to the external electrode layer 3 of the semiconductor device 11 is the metal material 55 and does not have the form of the wiring board as described above, it belongs to the scope of the structure 15 in the present invention.

As described above, the structure 15 of this embodiment is secondarily soldered at the working temperature of 260 ° C. The short-circuit failure occurrence rate of the semiconductor device 11 due to this heat treatment is as low as 0.00002%, which clearly shows the effect of preventing the solder material 5 from flowing out by adding the silica powder (particle size: 2 to 10 μm) 5B. The outflow of the solder material 5 was prevented because the powder 5B, which maintains the solid state even under the secondary mounting heat treatment, substantially suppresses the volume expansion of the remelted solder material 5 and causes an excessive increase in the internal pressure. This is because the peeling, the outflow and short circuit of the molten solder material are suppressed, and the outflow and the short circuit of the molten solder material are suppressed by the clogging phenomenon of the powder 5B. In addition, the powder 5B that maintains the solid state increases the substantial viscosity of the remelted solder material 5 and contributes to suppressing outflow and short circuit. Further, at the time of the primary mounting, the powder 5B is the molten matrix metal 5A, the Au plating layer on the wiring pattern 4, the S on the electrodes 105 of the chip parts 8 and 9.
n plating layer, A on the laminated metal layer 605 of the semiconductor chip 6
This also contributes to the fact that the contact area between the u layers is narrowed and the fusion of Au and Sn into the solder layer 5 is suppressed.

In the present invention, even if the substrate 1 uses a resin material as a base material, silica powder (particle size: 2 to 10 μm) is used.
m) Various metals listed in Table 2 can be applied to the metal having the same action as 5B. In addition, oxides, nitrides, borides, carbides, sulfides, phosphides, silicides, fluorides,
As long as it is a powder, it is applicable even if it is a powder of one kind of substance selected from the group of simple substance of silicon, simple substance of germanium, simple substance of carbon and simple substance of boron, or a mixture of two or more substances.

The particle size of the powder 5B used in this example is 2-1.
Although the particle size is 0 μm, the object of the present invention can be achieved with other particle sizes. The particle size of the powder 5B selected as a preferable range is 0.05 to 60 μm. The non-metal powder 5B is an oxide, a nitride, a boride, a carbide, a sulfide, a phosphide, a silicide, a fluoride, a silicon simple substance,
Even in the case of a single material selected from the group of germanium simple substance, carbon simple substance, and boron simple substance, or a mixed material composed of two or more kinds of substances, the preferable particle size range is 0.05 to 60 μm.
It is the same in that the more preferable particle size range is 0.05 to 10 μm. From the viewpoint of increasing the filling rate of the non-metal powder 5B in the solder material 5, 0.05-60 μm.
It is desirable to add non-metallic powders 5 having various particle diameters in combination within the range of m.

The shape of the non-metal powder 5B may be a perfect sphere, an irregular sphere, a prism, or a rod.

Although the addition amount of the silica powder 5B used in this example is 35 vol%, the object of the present invention can be achieved with other addition amounts. As described above, from the viewpoint of preventing short circuit and disconnection, 3 to 75 vol% is selected as an appropriate addition amount of the powder 5B. Further, in order to obtain uniform dispersibility of the powder particles in the matrix metal, a more preferable addition amount is selected from 10 to 50 vol%.

The above-mentioned proper particle size range and proper addition amount are set such that the matrix metal 5A is made of Sn or Pb, S.
n, Sb, Zn, Cu, Ni, Au, Ag, P, Bi,
In, Mn, Mg, Si, Ge, Ti, Zr, V, H
In the case of an alloy composed of two or more kinds selected from the group of f and Pd, the non-metal powder 5B is an oxide, a nitride, a boride,
In the case of a mixed powder material composed of one substance selected from the group consisting of carbide, sulfide, phosphide, silicide, fluoride, silicon simple substance, germanium simple substance, carbon simple substance and boron simple substance, or two or more kinds of substances. But they are common.

The structure 15 of this example is replaced with −20 to 110.
It was put into a temperature cycle test of ° C. Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. In the test up to 2000 times, the structure 15 of the present embodiment did not show any defect due to the disappearance of the circuit function of the semiconductor device 11.

(Example 12) Structure 1 obtained in Example 11
No. 5 was applied to a lithium ion secondary battery as the electronic device 100. Electronic device (secondary battery, external size: 60
mm × 30 mm × 8 mm) 100 constitutes the circuit shown in FIG. 11, and the semiconductor device 11 or structure 1 mounted on the circuit
5 has a role as a protection circuit for preventing over-discharge, over-charge and over-current and for preventing over-heating of the secondary battery element.

The lithium-ion secondary battery 100 having the above-mentioned structure exhibited the same operation and effect as those of the third embodiment.

(Embodiment 13) In this embodiment, CSP (Chi
The p scale package type semiconductor device 11 and the structure 15 having the semiconductor device 11 mounted on an external wiring board will be described.

FIG. 26 is a schematic sectional view for explaining a semiconductor device of this embodiment and a structure using the same. The semiconductor device 11 is configured as shown in (a). Polyimide substrate
A wiring pattern (Cu, thickness: 25 μm, Ni plating with a thickness of 5 μm and Au plating with a thickness of 1 μm are sequentially formed) 4 is provided on the first main surface 1A of (11 mm × 11 mm × 0.3 mm) 1, The integrated circuit element substrate (1
A chip component composed of 0 mm × 10 mm × 0.3 mm 6 is conductively fixed (primary mounting soldering, working temperature: 270 ° C.) by a solder layer (pitch: 0.1 mm) 5. The solder layer 5 includes a matrix metal 5A made of Sn-3.5 wt% Ag alloy and zirconia (ZrO ₂ ) powder (particle size:
1.0 to 3.0 μm) 5B is dispersed in the composite, and the amount of zirconia powder 5B added is adjusted to 25 vol%. An epoxy resin 10 is filled in a space (about 50 μm) formed by the integrated circuit element substrate 6 and the polyimide substrate 1, and the solder layer 5 is sealed so as to be completely shielded from the outside air. The epoxy resin 10 is composed of bisphenol A, methylhexahydrophthalic anhydride as an anhydride type curing agent, amine as a curing accelerator and an organic acid. Here, a solder resist film 51 is provided on a predetermined portion (a portion other than the formation region of the solder layer 5) of the wiring pattern 4 provided on the first main surface 1A. Further, the wiring pattern 4 also serves as the external electrode layer 3, and the solder balls for external wiring connection (Sn-3wt% Ag-0.7wt% Cu, diameter: approximately) are provided toward the second main surface 1B side of the substrate 1. 0.15 mm) 12 is formed. Although the non-metal powder 5B is not added to the solder balls 12 for external wiring connection in this embodiment, it is preferable to add them as needed.

According to the semiconductor device 11 described above,
Since the solder layer 5 is composed of a composite material in which the zirconia powder 5B is dispersed in the matrix metal 5A made of Sn-3.5 wt% Ag alloy, even if remelting occurs in the secondary mounting soldering described later, the matrix It is possible to prevent the outflow of the metal 5A and the resulting short circuit and disconnection.

Next, the structure 15 using the above-mentioned semiconductor device 11 is constructed as shown in (b). Semiconductor device 1
Reference numeral 1 is fixed to an external wiring (Cu, thickness: 25 μm) 13 of a wiring board 14 made of the same material as that of the second embodiment by a solder ball 12 for external wiring connection. On this occasion,
Secondary mounting soldering with solder balls 12 is 260 ℃
It is carried out under.

Semiconductor Device 1 in Structure 15 of the Present Example
The failure rate of 1 (disappearance of circuit function due to short circuit or disconnection) was 0.0018%, which was an extremely low value. This is due to the effect of preventing the solder material 5 from flowing out by adding the zirconia powder 5B. This outflow prevention effect is obtained by suppressing the volume expansion of the remelted solder material 5 by the zirconia powder 5B, suppressing the fluidity, clogging phenomenon, and the molten matrix metal 5A.
Based on the reduction of the substantial contact area between the wiring pattern 4 and the wiring pattern 4.

In the structure 15 of this embodiment, −30 to 125 is included.
A temperature cycle test of ° C was performed. Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. In the test up to 2000 times, the structure 15 of the present embodiment did not show any defect due to the disappearance of the circuit function of the semiconductor device 11.

In this embodiment, the integrated circuit element substrate 6 is fixed to the wiring pattern 4 on the polyimide substrate 1 with the zirconia powder-added solder layer 5, and the epoxy resin is filled in the void formed by the integrated circuit element substrate 6 and the polyimide substrate 1. Semiconductor device 11 having structure filled with resin 10 and structure 1 using the same
5 was explained. In this embodiment, the semiconductor device 1
1 and the structure 15 are not limited to the above-mentioned form.

FIG. 27 is a schematic sectional view for explaining a CSP type semiconductor device of another form. As shown in (a) of the semiconductor device 11, the solder layer 5 composed of the non-metal powder 5B and the matrix metal 5A is interposed via the Au bumps 56 provided on the integrated circuit element substrate 6 by the wire bonding method.
Is fixed to the wiring pattern 4 of the substrate 1. Au
The bumps 56 may be formed by wire bonding Cu and Al. Further, the semiconductor device 11 shown in FIG.
Is a metal ball 56 such as Cu, Ni, or Cu-Sn alloy.
Is fixed to the wiring pattern 4 of the substrate 1 by the solder layer 5 composed of the non-metal powder 5B and the matrix metal 5A. Even in the semiconductor device 11 having the above configuration,
The same effect as the present embodiment can be obtained. Although illustration is omitted, the same effect as that of the present embodiment can be obtained also in the case of the structure 15 in which the semiconductor device 11 having such a structure is mounted on the wiring board 14.

The semiconductor device 11 and the structure 1 described above
5 can play the role of a package that requires a large number of pins, a small size, and a thin structure based on the necessity of increasing the scale, speed, and function of the integrated circuit. The semiconductor device 11 and the structure 15 as described above are suitable for mounting on a portable information terminal device or a camera-integrated VTR.

(Embodiment 14) In the present embodiment, another form of C is used.
The SP type semiconductor device 11 and the structure 15 having the SP type semiconductor device 11 mounted on an external wiring board will be described.

FIG. 28 is a schematic sectional view for explaining a semiconductor device of this embodiment and a structure using the same. The semiconductor device 11 is configured as shown in (a). As the wiring substrate 1, an aluminum nitride substrate, a silicon nitride substrate, a glass substrate and a beryllia substrate (12 mm × 12 mm × 0.3 mm) were used. On the first main surface 1A of the substrate 1, wiring patterns (Cu,
Thickness: 25 μm, 5 μm thick Ni plating and 1 μm thick
m Au plating 4) is provided, and an integrated circuit element substrate (10 mm × 10 mm × 0.1 mm) is provided on the wiring pattern 4.
3mm) 6 chip parts are solder layers (pitch: 0.
1 mm) 5 is electrically conductively fixed (first mounting soldering, working temperature: 270 ° C.). Solder layer 5 is Sn-
It is composed of a composite in which zirconia powder (particle size: 1.0 to 3.0 μm) 5B is dispersed in a matrix metal 5A made of a 3.5 wt% Ag alloy. In this embodiment, the amount of zirconia powder 5B added is adjusted to 25 vol%. A void (about 50 μm) formed by the integrated circuit element base 6 and the ceramics substrate 1 is filled with an epoxy resin 10, and the solder layer 5 is sealed so as to be completely shielded from the outside air. The epoxy resin 10 is composed of bisphenol A, methylhexahydrophthalic anhydride as an anhydride type curing agent, amine as a curing accelerator and an organic acid. The wiring pattern 4 also serves as the external electrode layer 3, and is formed to extend from the first main surface 1A of the substrate 1 toward the second main surface 1B side via the side surface.

According to the semiconductor device 11 described above,
Since the solder layer 5 is composed of a composite material in which the zirconia powder 5B is dispersed in the matrix metal 5A made of Sn-3.5 wt% Ag alloy, even if remelting occurs in the secondary mounting soldering described later, the matrix It is possible to prevent the outflow of the metal 5A and the resulting short circuit and disconnection.

Next, the structure 15 using the above-mentioned semiconductor device 11 is constructed as shown in (b). Semiconductor device 1
Reference numeral 1 is fixed to an external wiring (Cu, thickness: 25 μm) 13 of a wiring board 14 made of the same material as in Example 2 by a solder layer (Sn-3.5 wt% Ag alloy) 12 for external wiring connection. . At this time, the secondary mounting soldering with the solder layer 12 is performed at 260 ° C.

The occurrence rate of defects (disappearance of circuit function due to short circuit or disconnection) of the semiconductor device 11 in the structure 15 of the present embodiment is one of the wiring substrate 1 of the aluminum nitride substrate, the silicon nitride substrate, the glass substrate and the beryllia substrate. Even if it is 0.0
It was an extremely low value of 0033 to 0.0095%.
This is due to the effect of preventing the solder material 5 from flowing out by adding the zirconia powder 5B. This outflow prevention effect is based on the suppression of volume expansion of the remelted solder material 5 by the zirconia powder 5B, the suppression of fluidity, the clogging phenomenon, and the reduction of the substantial contact area between the molten matrix metal 5A and the wiring pattern 4.

The structure 15 of this embodiment has a structure of -30 to 125.
A temperature cycle test of ° C was performed. Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. Wiring board 1 in the test up to 2000 times
As the structure 15 using any of an aluminum nitride substrate, a silicon nitride substrate, a glass substrate, and a beryllia substrate, no defect due to the disappearance of the circuit function of the semiconductor device 11 was shown.

The semiconductor device 11 and the structure 1 described above
5 can play the role of a package that requires a large number of pins, a small size, and a thin structure based on the necessity of increasing the scale, speed, and function of the integrated circuit. The semiconductor device 11 and the structure 15 as described above are suitable for mounting on a portable information terminal device or a camera-integrated VTR.

Example 15 In this example, a CSP type semiconductor device 11 of another form and a structure 15 having the same mounted on an external wiring substrate will be described.

FIG. 29 is a schematic sectional view for explaining a semiconductor device of this embodiment and a structure using the same. The semiconductor device 11 is configured as shown in (a). The wiring board 1 is the same polyimide board as in Example 13, and the chip parts of the wiring pattern 4 and the integrated circuit element substrate (9 mm × 9 mm × 0.3 mm) 6 are TAB wiring (thickness: 60 μm polyimide tape). Thickness: Cu wiring of 25 μm is provided)
Solder layer (pitch: 0.1 mm) through 5'and 5 "
Conductively adheres to (primary mounting soldering, working temperature:
270 ° C). Solder layer 5 is Sn-3.5wt
% Sb alloy composed of a matrix metal 5A and zirconia powder (particle size: 1.0 to 3.0 μm) 5B dispersed therein, and the added amount of zirconia powder 5B is 40 vo.
It has been adjusted to l%. The integrated circuit element substrate 6 is an adhesive agent (not shown) made of an epoxy resin added with Ag powder.
Is bonded to the substrate 1. Integrated circuit element substrate 6,
TAB wiring 7, solder layers 5 ', 5 ", wiring pattern 4
Is sealed with the same epoxy resin layer 10 as in the first embodiment. The wiring pattern 4 also serves as the external electrode layer 3, and the solder balls for external wiring connection (Sn-3wt% Ag-0.7wt%) are provided toward the second main surface 1B side of the substrate 1.
Cu, diameter: about 0.15 mm) 12 is formed.

According to the semiconductor device 11 described above,
Since the solder layer 5 is composed of a composite body in which the zirconia powder 5B is dispersed in the matrix metal 5A made of Sn-3.5 wt% Sb alloy, even if remelting occurs in the secondary mounting soldering described later, the matrix It is possible to prevent the outflow of the metal 5A and the resulting short circuit and disconnection.

Next, the structure 15 using the above-mentioned semiconductor device 11 is constructed as shown in (b). Semiconductor device 1
1 is fixed to the external wiring (Cu, thickness: 25 μm) 13 of the wiring board 14 made of the same material as that of the second embodiment by the solder ball 12 for external wiring connection. At this time, the secondary mounting soldering with the solder balls 12 is performed at 265 ° C.

The occurrence rate of defects (disappearance of circuit function due to short circuit or disconnection) of the semiconductor device 11 in the structure 15 of this example was a very low value of 0.0043%. This is due to the effect of preventing the solder material 5 from flowing out by adding the zirconia powder 5B. This outflow prevention effect suppresses the volume expansion of the remelted solder material 5 by the zirconia powder 5B,
Suppression of fluidity, clogging phenomenon, molten matrix metal 5
This is based on the reduction of the substantial contact area between A and the wiring pattern 4.

The structure 15 of this embodiment has a structure of -30 to 125.
A temperature cycle test of ° C was performed. Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. In the test up to 2000 times, the structure 15 of the present embodiment did not show any defect due to the disappearance of the circuit function of the semiconductor device 11.

Example 16 In this example, BGA (Bal
A description will be given of a (Grid Array) type semiconductor device 11 and a structure 15 having the same mounted on an external wiring board.

FIG. 30 is a schematic sectional view for explaining a semiconductor device of this embodiment and a structure using the same. The semiconductor device 11 is configured as shown in (a). Polyimide substrate
A through hole is provided at the center of (15 mm × 15 mm × 0.4 mm) 1 and the integrated circuit element substrate 6 is arranged in this portion. The wiring pattern (C
u, thickness: 25 μm, Ni plating with a thickness of 5 μm and Au plating with a thickness of 1 μm are sequentially formed) 4 are embedded, and a part of the wiring pattern 4 is formed so as to project to the through hole side.
The protruding wiring pattern 4 and the integrated circuit element substrate (10 mm ×
The chip component composed of 10 mm × 0.3 mm) 6 is conductively fixed (primary mounting soldering, working temperature: 270 ° C.) by a solder layer (pitch: 0.1 mm) 5. The solder layer 5 includes a matrix metal 5A made of Sn-3.5 wt% Sb alloy and silicon carbide (SiC) powder (particle size: 2.0 to 5.0).
0 μm) 5B is dispersed in the composite, and the amount of silicon carbide powder 5B added is adjusted to 30 vol%. The integrated circuit element substrate 6, the polyimide substrate 1, the wiring pattern 4, and the solder layer 5 are molded with an epoxy resin 10, and in particular, the solder layer 5 is sealed so as to be completely shielded from the outside air. The epoxy resin 10 is made of the same material as in the first embodiment. Further, a part of the wiring pattern 4 also serves as the external electrode layer 3, and the solder ball (Sn-3 wt% for external wiring) for connecting the external wiring is directed toward the second main surface 1B side of the substrate 1.
Ag-0.7 wt% Cu, diameter: about 0.25 mm) 12 is formed. Therefore, the wiring pattern 4 arranged on the outer peripheral side of the substrate 1 which also serves as the external electrode layer 3 is electrically connected to the protruding wiring pattern 4 and the integrated circuit element substrate 6. Although the non-metal powder 5B is not added to the solder balls 12 for external wiring connection in this embodiment, it is preferable to add them as needed.

According to the semiconductor device 11 described above,
Since the solder layer 5 is composed of a composite body in which the silicon carbide powder 5B is dispersed in the matrix metal 5A made of Sn-3.5 wt% Sb alloy, even if remelting occurs in the secondary mounting soldering described later, It is possible to prevent outflow of the matrix metal 5A and the resulting short circuit and disconnection.

Next, the structure 15 using the above-described semiconductor device 11 is constructed as shown in (b). Semiconductor device 1
1 is fixed to the external wiring (Cu, thickness: 25 μm) 13 of the wiring board 14 made of the same material as that of the second embodiment by the solder ball 12 for external wiring connection. At this time, the secondary mounting soldering with the solder balls 12 is performed at 265 ° C.

The occurrence rate of defects (disappearance of circuit function due to short circuit or disconnection) of the semiconductor device 11 in the structure 15 of this example was a very low value of 0.0046%. This is due to the effect of preventing the solder material 5 from flowing out by adding the silicon carbide powder 5B. This outflow prevention effect suppresses the volume expansion of the remelted solder material 5 by the silicon carbide powder 5B,
Suppression of fluidity, clogging phenomenon, molten matrix metal 5
This is based on the reduction of the substantial contact area between A and the wiring pattern 4.

In the structure 15 of this embodiment, −30 to 125 is used.
A temperature cycle test of ° C was performed. Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. In the test up to 2000 times, the structure 15 of the present embodiment did not show a defect due to the disappearance of the circuit function of the semiconductor device 11.

The semiconductor device 11 and the structure 15 of this embodiment.
Then, the integrated circuit element substrate 6 is fixed to the wiring pattern 4 on the polyimide substrate 1. However, the semiconductor device 11 and the structure 15 are not limited to the above-mentioned form. For example, instead of the polyimide substrate 1, a glass epoxy material (a composite material in which glass fiber cloth is impregnated with epoxy resin,
The base material may have a coefficient of thermal expansion of 9.0 ppm / ° C. and a Young's modulus of 35 GPa). Even a semiconductor device having such a form and a structure using this semiconductor device,
The same excellent performance and effect as described above can be obtained.

[0166] The semiconductor device 11 and the structure 1 described above
5 can play the role of a package that requires a large number of pins, a small size, and a thin structure based on the necessity of increasing the scale, speed, and function of the integrated circuit. The semiconductor device 11 and the structure 15 as described above are suitable for mounting on a portable information terminal device or a camera-integrated VTR.

FIG. 31 is a schematic sectional view for explaining a modified example of the structure of this embodiment. This structure 15 is basically the same as the structure shown in FIG. 30, except for the following two points. First, the silicone resin 101 is filled between the semiconductor device 11 and the wiring board 14, and the solder balls 12 for external wiring connection are completely sealed. Second
Is an external wiring connection solder ball 12 Sn-3wt%
Matrix metal 12 composed of Ag-0.7 wt% Cu
A and silica powder (particle size: about 3.0 μm, addition amount: 35 vo
1%) 12B. According to such a configuration, when the structure 15 is integrated with or electrically connected to another member by heat treatment, even if the solder balls 12 for external wiring connection are remelted, the outflow of the matrix metal 12A and this may occur. It is possible to prevent accompanying short circuit and disconnection. Here, the matrix metal 12A and the non-metal powder 12
In B, the above-mentioned matrix metal 5A and non-metal powder 5
B can be applied. At this time, the appropriate particle size and the addition amount of the non-metal powder 12B can be selected as the same values as those of the non-metal powder 5B.

(Embodiment 17) In this embodiment, COC (Ch
The ip on chip type semiconductor device 11 and the structure 15 having the same mounted on an external wiring board will be described.

FIG. 32 is a schematic sectional view for explaining a semiconductor device of this embodiment and a structure using the same. The semiconductor device 11 is configured as shown in (a). The substrate 1 is a Si substrate (15 mm × 15 mm × 0.3 mm) and also serves as the second integrated circuit element substrate 6 '. Second integrated circuit element substrate 6 '
The first integrated circuit device substrate (12 mm × 12 mm × 0.
3mm) 6 chip parts are solder layers (pitch: 0.
08mm) 5 conductively fixed (primary mounting soldering,
Working temperature: 270 ° C). Solder layer 5 is Sn-
It is composed of a composite material in which zirconia powder (particle size: 0.05 to 0.1 μm) 5B is dispersed in matrix metal 5A made of 3.5 wt% Ag alloy, and the addition amount of zirconia powder 5B is adjusted to 5 vol%. There is. Although not shown, Al wiring (thickness: 1.75 μm) is provided on the first integrated circuit element substrate 6, and Ti (0. 18 μm) -C
A u (1.75 μm) -Ni (15 μm) laminated metal layer is selectively provided. On the other hand, the second integrated circuit element substrate 6 '
In addition, Al wiring and Ti similar to those of the first integrated circuit element substrate 6 are used.
A -Cu-Ni laminated metal layer is provided. The laminated metal layer of the second integrated circuit element substrate 6'also serves as the wiring pattern 4. The void (about 70 μm) formed by the first integrated circuit element substrate 6 and the second integrated circuit element substrate 6'is filled with the epoxy resin 10, and the solder layer 5 is sealed so as to be completely shielded from the outside air. Has been done. Epoxy resin 10
Is composed of bisphenol A, methylhexahydrophthalic anhydride as an anhydride type curing agent, amine and an organic acid as a curing accelerator. The second integrated circuit element substrate 6'is mounted on the pedestal 50 with a silver paste adhesive (not shown). An Al wiring layer is provided in the peripheral region of the second integrated circuit element substrate 6 '(not shown), and this Al wiring layer is provided with the external terminals 3 and Au thin wires (diameter:
25 μm) 7 wire bonding. Here, the pedestal 50 and the external terminal 3 are made of Fe-42.
The lead frame was composed of a wt% Ni alloy (thickness: 0.1 mm, Sn plating). Each of the members described above has the transfer molding method (180 ° C., 4.9 MPa, 3 min, 180 ° C.) except for a part of the external terminal 3.
It is sealed with an epoxy resin (thermal expansion coefficient after curing: 16 ppm / ° C., elastic modulus: 15.7 GPa, glass transition point: 155 ° C.) 101 provided by (× 6 h). Such transfer mold epoxy resin 101,
Thermal expansion coefficient after curing: 5-220 ppm / ° C, Young's modulus: 1
A resin having physical properties of ˜50 GPa and glass transition point: 120 to 160 ° C. can be substituted.

According to the semiconductor device 11 described above,
Since the solder layer 5 is composed of a composite material in which the zirconia powder 5B is dispersed in the matrix metal 5A made of Sn-3.5 wt% Ag alloy, even if remelting occurs in the secondary mounting soldering described later, the matrix It is possible to prevent the outflow of the metal 5A and the resulting short circuit and disconnection.
Further, the semiconductor device 11 of this embodiment has the following features. That is, (1) the first integrated circuit element substrate 6 and the second
Although the integrated circuit element substrate 6'is a heterogeneous device that plays different electrical roles, the mounting area can be reduced by face-to-face bonding, and (2) metal bonding suitable for high-speed communication with less electrical signal loss is performed. ing.

The semiconductor device 11 of this embodiment has a temperature of 150 ° C.
The connection resistance of the solder joint between the first integrated circuit element substrate 6 and the second integrated circuit element substrate 6 ′ was traced by a 1000 h high temperature storage test. The resistance value was 58 mΩ after 1000 h with respect to the initial value of 50 mΩ, showing excellent stability. Further, the semiconductor device 11 has (1) 85 ° C. and 85% R
H, 50V high temperature and high humidity blocking test, (2) 150
C., 500h high temperature storage test, (3) -55-150
A temperature cycle test was conducted 1000 ° C. and 1000 times. In all the tests, the number of defects due to the deterioration of the circuit function was zero with respect to the number of input samples of 15, which showed excellent reliability.

Next, the structure 15 using the above-described semiconductor device 11 is constructed as shown in (b). Semiconductor device 1
Between the external terminal 3 of No. 1 and the external wiring (Cu, thickness: 25 μm) 13 of the wiring board 14 made of the same material as in Example 2, the external wiring connection solder (Sn-3 wt% Ag-0.
7 wt% Cu) 12 is fixed. The secondary mounting soldering at this time is performed at 255 ° C.

The occurrence rate of defects (disappearance of circuit function due to short circuit or disconnection) of the semiconductor device 11 in the structure 15 of this example was a very low value of 0.00056%. This is due to the effect of preventing the solder material 5 from flowing out by adding the zirconia powder 5B. This outflow prevention effect suppresses the volume expansion of the remelted solder material 5 by the zirconia powder 5B,
Suppression of fluidity, clogging phenomenon, molten matrix metal 5
Based on the reduction of the substantial contact area between A and the metal to be connected.

The structure 15 of this example has a temperature of -30 to 125 ° C.
Was subjected to a temperature cycle test. In the test up to 2000 times, the structure 15 of the present embodiment did not show any defect due to the disappearance of the circuit function of the semiconductor device 11.

In this embodiment, the first integrated circuit element substrate 6
The semiconductor device 11 and the structure 15 having a structure in which the void formed by the second integrated circuit element substrate 6'and the epoxy resin 10 is filled and further sealed with the epoxy resin 101 by the transfer molding method have been described. However, in the present embodiment, the semiconductor device 11 and the structure 15 are not limited to the above-mentioned form.

FIG. 33 is a schematic sectional view for explaining a COC type semiconductor device of another form. In this semiconductor device 11,
An epoxy resin 101 formed by a transfer molding method is filled in a space formed by the first integrated circuit element substrate 6 and the second integrated circuit element substrate 6 '. Even with the semiconductor device 11 having such a configuration, the same effect as that of the present embodiment can be obtained. Although detailed description is omitted,
Also in the case of the structure 15 in which the semiconductor device 11 having such a structure is mounted on the wiring board 14, the same effect as this embodiment can be obtained.

The semiconductor device 11 and the structure 1 described above
5 can play the role of a package that requires a large number of pins, a small size, and a thin structure based on the necessity of increasing the scale, speed, and function of the integrated circuit. The semiconductor device 11 and the structure 15 as described above are suitable for mounting on a portable information terminal device or a camera-integrated VTR.

(Embodiment 18) In this embodiment, a semiconductor device 11 as a microminiature DC / DC converter for portable equipment and a structure 15 having the semiconductor device 11 mounted on an external wiring board will be described.

FIG. 34 is a schematic sectional view for explaining a semiconductor device of this embodiment and a structure using the same. The semiconductor device 11 is configured as shown in (a). Inside the multi-layer glass epoxy substrate (25 mm × 10 mm × 0.4 mm) 1, an inner wiring layer (Cu, thickness: 15 μm, not shown) 2 and through-hole wiring (Cu, plating, not shown) 2
A is provided. A wiring pattern (Cu, thickness: 25 μm, Ni plating having a thickness of 5 μm and Au plating having a thickness of 1 μm is sequentially formed) 4 is provided on the first main surface 1A of the substrate 1, and a thin film is formed on the wiring pattern 4. Inductor 110,
PWM control integrated circuit substrate 6A, MOS FET device substrate 6B as a switching element, rectifying diode 6C
The chip components such as the chip resistor 8 and the capacitor 9 (not shown) are conductively fixed by the solder layer 5 (primary mounting soldering, working temperature: 270 ° C.). Solder layer 5
Is a matrix metal 5 made of Sn-5 wt% Sb alloy
It is composed of a composite in which a mixed powder (particle size: 2.0 to 3.0 μm) 5B composed of zirconia powder and alumina powder is dispersed in A, and the addition amount of the mixed powder 5B is adjusted to 30 vol%. Further, Au is provided between the semiconductor element substrates 6A and 6B and the thin film inductor 110 and a predetermined portion of the wiring pattern 4.
A thin metal wire 7 made of is bonded (diameter 40 μm). These chip parts, thin metal wires 7, wiring pattern 4, and first main surface 1A are resin layers whose main component is an epoxy material (the physical properties after curing are: thermal expansion coefficient: 9.0 ppm / ° C., Young's modulus: 24. 5 GPa, glass transition point: 150 ° C., filler addition amount: 85 wt%) 10 so as to be completely shielded from the outside air. This resin layer (Dimension: 23mm
× 9 mm × 0.8 mm) 10 is formed by the potting method. The external terminal layer (Cu, thickness: 25 μm, thickness 5 μm) extends from the first main surface 1A of the substrate 1 to the side surface 1C.
Ni plating and 1 μm thick Au plating are sequentially formed)
3 is provided as an extension. The external terminal layer 3 is an inner wiring layer 2 or through-hole wiring 2A provided inside the substrate 1.
And is electrically connected to the wiring pattern 4.
As described above, each chip component is
Completely sealed by the wiring pattern 4 and the resin layer 10,
The solder layer 5 fixing these chip components is also completely sealed by the chip component, the wiring pattern 4, and the resin layer 10.

According to the semiconductor device 11 described above,
Since the solder layer 5 is composed of a composite in which a mixed powder (particle size: 2.0 to 3.0 μm) 5B made of zirconia powder and alumina powder is dispersed in a matrix metal 5A made of Sn-5 wt% Sb alloy. Even if remelting occurs in the secondary mounting soldering described later, the matrix metal 5A
It is possible to prevent the outflow of water and the resulting short circuit and disconnection.

FIG. 35 is a diagram for explaining the circuit of the semiconductor device of this embodiment. The semiconductor device 11 constitutes a 5 MHz switching DC / DC converter circuit. A lithium-ion secondary battery (voltage: 3.0) on the input side (Vi)
~ 4.2V, average voltage: 3.6V), multiple loads are connected to the output side (Vo), maximum output while boosting or stepping down or inverting depending on the voltage required by each load. Voltage: 4.7V, Maximum output current: 600mA
Electric power of (maximum output: about 3 W) is supplied. This DC /
The DC converter circuit is suitable for mobile phones and book-type personal computers that require communication functions, display functions, and high-speed image information processing functions.

The structure 15 of this embodiment, in which the semiconductor device 11 is incorporated, is constructed as shown in FIG.
The semiconductor device 11 has an external wiring (Cu, thickness: 25 μm) 13 of a wiring board 14 made of the same material as that of the second embodiment, and external wiring connection solder (Sn-5 wt% Sb-0.
6 wt% Ni-0.05 wt% P) 12. At this time, the secondary mounting soldering with the external wiring connecting solder 12 is performed at 270 ° C.

The occurrence rate of defects (disappearance of circuit function due to short circuit or disconnection) of the semiconductor device 11 in the structure 15 of this example was a very low value of 0.0038%. This is due to the effect of preventing the solder material 5 from flowing out by adding the zirconia powder and the alumina powder 5B. This outflow prevention effect is obtained by suppressing the volume expansion of the remelted solder material 5 by the mixed powder 5B of zirconia and alumina, the suppression of fluidity, the clogging phenomenon, the molten matrix metal 5A and the wiring pattern 4.
Based on the reduction of the substantial contact area between.

Using the structure 15 of this example, DC / D
The control characteristics as a C converter were investigated. 3V to 4.
It was confirmed that the output voltage had a fluctuation of ± 3% or less with respect to the fluctuation of the input voltage up to 2 V, and the structure 15 had excellent controllability.

FIG. 36 is a graph for explaining the relationship between the output current and the conversion efficiency of the structure of this example. Although the figure shows the case where the input voltage (Vin) is 3.0V, 3.6V and 4.2V, especially when the output current is 300mA, the average voltage of the lithium-ion secondary battery is 3.6% and 80% or more. And high efficiency is obtained.

(Embodiment 19) In this embodiment, a semiconductor device 11 for an alternator device for an automobile and a structure 15 using the semiconductor device 11 will be described.

FIG. 37 is a schematic sectional view for explaining the semiconductor device of this embodiment. Reference numeral 1 is a Cu container as a wiring member, and a Ni plating layer (thickness: 3 to 7 μm, not shown) is formed on the surface thereof. Solder layer 5 "on the bottom of container 1
The thermal expansion alleviating member 19 is attached to the semiconductor substrate 6 fixed by the solder layer 5 on the thermal expansion alleviating member 19 and the Cu on the semiconductor substrate 6 via the solder layer 5 ′.
The lead 7 is fixed. Further, the thermal expansion alleviating member 1
9, Cu lead 7, solder layer 5, 5 ′, 5 ″ and resin layer covering the surface of the semiconductor substrate 6 (coefficient of thermal expansion: 450 ppm
/ ° C, Young's modulus: 1.27 MPa, silicone resin (75
%) And calcium carbonate (25%) RTV silicone rubber) 10. Thermal expansion alleviating member 19
Is a laminated structure of dissimilar metal plates [Cu (thickness: 0.2 mm)-
Invar (0.2 mm) -Cu (0.2 mm)], and processed into a disk shape with a diameter of 5 mm. The thermal expansion coefficient of this thermal expansion relaxation member 19 is 10.6 ppm / ° C. and the thermal conductivity is 3
It has 0.3 W / m · K (vertical direction) and 262 W / m · K (horizontal direction). A Ni plating layer (thickness: 3 to 7 μm, not shown) is formed on the surface of the disk-shaped thermal expansion relaxation member 19. A similar Ni plating layer is also formed on the surface of the Cu lead 7. The semiconductor substrate 6 is a diode made of Si and is processed into a disk shape having a thickness of 0.3 mm and a diameter of about 4 mm.

Here, the solder layers 5, 5 ', 5 "are made of Pb.
-50 wt% Sn-1.5 wt% Ag alloy Matrix metal 5A with zirconia powder (particle size: 3 μm) 5
It is composed of a composite in which B is dispersed, and the addition amount of the mixed powder 5B is adjusted to 20 vol%. Cu is used for soldering
Sheet-shaped solder materials 5, 5 ', 5 "are arranged in layers between the container, the thermal expansion relaxation member 19, the semiconductor substrate 6 and the Cu leads 7, and these are heat-treated at 350 ° C in a hydrogen atmosphere. It is being carried out.

The thickness of the solder layers 5, 5 ', 5 "is 20 to 3
The thickness may be in the range of 00 μm, but in consideration of the reliability, workability, yield, etc. required for the semiconductor device 11, it is 50 to 2
The range of 00 μm is more desirable.

As the lead 7, in addition to Cu, an alloy containing Cu as a base material may be used. At this time, in order to impart solder wettability, it is desirable to plate the surface with a metal such as Ag or Au in addition to Ni.

The thermal expansion relaxation member 19 is made of Mo, W, Cu-W.
Composite material, Cu-Mo composite material, Cu-Cu2O composite material, A
It is possible to substitute a material having a thermal expansion coefficient close to that of a semiconductor substrate and a high thermal conductivity, such as an l-SiC composite material.

The resin layer 10 has, for example, a coefficient of thermal expansion of 1 to 3 pp.
m / ° C, Young's modulus: 1960 MPa phenol resin (calcium carbonate added), thermal expansion coefficient: 30 ppm / ° C, Young's modulus: 11000 MPa silicone resin, thermal expansion coefficient: 35-75 ppm / ° C, Young's modulus: 8800 MPa polybutylene Terephthalate resin, coefficient of thermal expansion: 19-2
2 ppm / ° C, Young's modulus: 11700 to 13700 MPa
Polyphenylene sulfide resin (containing 40% glass fiber), coefficient of thermal expansion: 950 ppm / ° C, Young's modulus: 0.02
It is possible to substitute a silicone gel resin of MPa.

As described above, the members mounted on the semiconductor device 11, especially the solder layers 5, 5 ', 5 "are the container 1, the thermal expansion alleviating member 19, the semiconductor substrate 6, the Cu lead 7, the resin layer 10. With the semiconductor device 11 having such a structure, the solder layer 5,
5 ', 5 "is Pb-50wt% Sn-1.5wt% Ag
Matrix metal 5A made of alloy and zirconia powder 5
Since it is composed of a composite in which B is dispersed, even if remelting occurs in the secondary mounting soldering described later, the matrix metal 5A flows out and a short circuit is caused by the outflow (in particular, the thermal expansion relaxation member 19 and the semiconductor substrate 6). (Between the semiconductor substrate 6 and the Cu lead 7) can be prevented.

FIG. 38 is a graph for explaining the transition of thermal resistance in the temperature cycle test of the semiconductor device of this example. In the figure, A is the semiconductor device 11 of this embodiment, and B is the comparative semiconductor device. Here, the comparative semiconductor device is the solder layer 5 of the semiconductor device 11 of the present embodiment.
The part corresponding to 5 ', 5 "is Pb-50wt% Sn-
It is composed of only a 1.5 wt% Ag alloy (without adding non-metal powder), and the other structures are the same as those of the present embodiment.
The amount of increase in thermal resistance with respect to the initial value on the vertical axis is represented by the ratio of (thermal resistance after test / initial thermal resistance). In the samples A and B, the thermal resistance did not increase in the test up to 10,000 cycles, and the initial thermal resistance value was maintained. This result shows that the semiconductor device 11 according to the present embodiment.
It is suggested that even when the non-metal powder 5B is added to the solder layers 5, 5 ′ and 5 ″ as described above, the same reliability as in the case where the non-metal powder is not added can be secured.

FIG. 39 is a graph for explaining the transition of thermal resistance in the power cycle test of the semiconductor device of this example. In this test, the temperature of the container 1 is 30 to 125.
The semiconductor device 11 was intermittently energized so as to cause a change in temperature. A and B in the figure are the same as in the case of the temperature cycle test shown in FIG. Also, the view of the vertical axis is the same as in the case of FIG. Samples A and B both showed a thermal resistance equivalent to the initial value up to about 50,000 cycles, and the increase in thermal resistance occurred after exceeding 50,000 cycles. Also from this result, as in the semiconductor device 11 of this embodiment, the solder layers 5, 5 ′,
It can be confirmed that even when the nonmetallic powder 5B is added to 5 ″, the same level of reliability as in the case where the nonmetallic powder is not added can be secured.

The semiconductor device 11 described above is applied to a full-wave rectifier as the structure 15. FIG. 40 is a plan view and a sectional view for explaining the full-wave rectifier. (A) is structure 1
5 is a plan view of the full-wave rectifier as 5, and (b) is A-
It is an A'cross section figure. In the figure, the semiconductor device 11 is C
u container 1, thermal expansion relaxation member 19 fixed to the bottom of container 1 by solder layer 5 ″, semiconductor substrate 6 fixed on thermal expansion relaxation member 19 by solder layer 5, solder layer 5 ′ on semiconductor substrate 6 The Cu container 7 of the three semiconductor devices 11 includes the Cu leads 7 fixed via the external leads 13 and the external wiring substrate 14 via the external wiring connection layer 12. It is adhered to the first heat dissipation plate 90 which also serves a role, and three semiconductor devices 11 are similarly mounted on the second heat dissipation plate 91. That is,
First heat dissipation plate 9 in which a plurality of semiconductor devices 11 are paired with each other
The heat radiating plates are mounted on the zero and second heat radiating plates 91 so that the rectifying directions are aligned in each heat radiating plate and the rectifying directions are different between the heat radiating plates. Here, pressed Cu plates are used for the first heat radiating plate 90 and the second heat radiating plate 91. The role of the heat sinks 90 and 91 is to efficiently transfer the heat emitted from the semiconductor device 11 to the outside and to efficiently transfer the electric power. From this viewpoint, the heat sink 9
It is also possible to use an Al plate for 0 and 91. The first heat radiating plate 90 and the second heat radiating plate 91 form a pair, and are attached to a terminal block 92 made of epoxy resin or the like via a mounting member 93. The Cu lead 7 is made of Cu which is embedded in the terminal block 92 in advance through the solder material 94.
It is joined to the terminal 95. A Pb-63 wt% Sn alloy is applied to the solder material 94 and the external wiring connection layer 12, and these solderings are performed by heat treatment at 260 ° C. This alloy has (1) Pb-5 wt% Sn-1.5
wt% Ag, Pb-10 wt% Sn, Pb-50 wt
% Sn, Pb-63 wt% Pb-Sn alloy material such as Sn, (2) Sn-based metal or (3) Sn, Sb, A
An alloy material containing at least two selected from the group consisting of g, Cu, Ni, P, Bi, Zn, Au and In may be used instead.

The occurrence rate of defects (disappearance of circuit function due to short circuit) of the semiconductor device 11 in the structure 15 of the present embodiment is 0.
It was an extremely low value of 0,004%. This is due to the effect of preventing the solder material 5 from flowing out by adding the zirconia powder 5B. This outflow prevention effect is obtained by using zirconia powder 5
This is based on the suppression of volume expansion of the remelted solder material 5 due to B, the suppression of fluidity, and the clogging phenomenon.

FIG. 41 is a circuit diagram for explaining the full-wave rectifier circuit of the structure of this embodiment. This full-wave rectifier 15 was attached to a three-phase AC generator for vehicles. Rotational power generated by the engine of the vehicle is transmitted to the rotor, and the rotor coil attached to the rotor is excited to generate alternating current in the stator coil. U of full-wave rectifier 15,
The V and W terminals are connected to the stator coil described above. Therefore, the alternating current passing through the U, V, W terminals is converted into direct current by each semiconductor device 11, and is supplied to the load as DC power through the terminals A and B.

The full-wave rectifier 15 was installed in the engine room of the automobile together with the three-phase AC generator 100 to which it was attached. This car was subjected to a driving test of 200,000 km. Although the three-phase AC generator 100 and the full-wave rectifier 15 were always in operation during this running test period, their electrical functions were maintained at the same level as in the initial state. As a reason why such excellent durability performance was obtained,
(1) Solder layer 5 inside the semiconductor device 11
The point that outflow due to remelting of 5 ', 5 "was completely suppressed,
(2) Each member in the semiconductor device 11 has solder layers 5, 5 ', 5 "with excellent reliability as shown in FIGS.
The points connected by.

The full-wave rectifier is not limited to the form shown in this embodiment. FIG. 42 is a schematic sectional view illustrating a full-wave rectifier of another form. In the figure, the semiconductor device 11
Is fixed to the through holes of the first heat radiating plate 90 and the second heat radiating plate 91 by the external wiring connecting solder layer 12. An insulating sheet 96 made of silicone resin is sandwiched between the first heat radiating plate 90 and the second heat radiating plate 91. That is, a plurality of semiconductor devices 11 are fixed on the first heat radiating plate 90 and the second heat radiating plate 91 which are paired with each other, the rectifying directions are aligned in the respective heat radiating plates, and the rectifying directions are different between the heat radiating plates. Is attached to. The first heat dissipation plate 90 and the second heat dissipation plate 91 are paired with each other. In each semiconductor device 11, the Cu lead 7 is joined to the metal terminal 95 previously attached to the terminal block 92 via the solder material 94. The full-wave rectifier 15 having the above structure constitutes the full-wave rectifier circuit shown in FIG. This full-wave rectifier 15 can also be attached to a three-phase AC generator for vehicles and used.

(Embodiment 20) In this embodiment, MCM (Mul
The ti Chip Module) type semiconductor device 11 and the structure 15 in which the semiconductor device 11 is mounted on an external wiring board will be described.

FIG. 43 is a schematic sectional view for explaining a semiconductor device of this embodiment and a structure using the same. The semiconductor device 11 is configured as shown in (a). On the first main surface 1A of the glass epoxy substrate (18.8 mm × 16.8 mm × 0.65 mm, 4-layer wiring), a wiring pattern (Cu, thickness:
25 μm, 5 μm thick Ni plating and 1 μm thick A
4 is provided on the wiring pattern 4, and four kinds of integrated circuit element substrates (4.7 mm × 8.2 mm) are provided on the wiring pattern 4.
X 0.35mm, 3.9mm x 4.9mm x 0.35mm, 4.9mm
X 4.7mm x 0.35mm, 6.0mm x 6.0mm x 0.35m
m) 6 chip parts are solder layers (pitch: 0.1 mm
) 5 electrically conductively fixed. Solder layer 5 is S
Matrix metal 5 composed of n-3.5 wt% Ag alloy 5
It is composed of a composite in which alumina powder (particle size: 0.05 to 15 μm) 5B is dispersed in A, and the addition amount of alumina powder 5B is adjusted to 20 vol%. Integrated circuit element base 6
And the glass epoxy substrate 1 (about 50μ
m) is filled with epoxy resin 10 and the solder layer 5 is sealed so as to be completely shielded from the outside air. The epoxy resin 10 is composed of bisphenol A, methylhexahydrophthalic anhydride as an anhydride-based curing agent, amine and an organic acid as a curing accelerator. Where the first
The solder resist film 51 is formed on a predetermined portion (a portion other than the formation region of the solder layer 5) of the wiring pattern provided on the main surface 1A.
Is provided. The wiring pattern 4 also serves as the external electrode layer 3, and the solder ball (diameter: about 0.15 mm) 1 for external wiring connection is provided toward the second main surface 1B side of the substrate 1.
2 is formed. Solder ball 12 is Sn-3wt
Matrix metal composed of% Ag-0.7wt% Cu 1
2A is composed of a composite in which 15 vol% of a non-metal powder 12B made of silica powder (particle size: 0.05 to 25 μm) is added.

According to the semiconductor device 11 described above,
The solder layer 5 includes a matrix metal 5A made of Sn-3.5 wt% Ag alloy and alumina powder (particle size: 0.05 to 15).
(μm) 5B is composed of a composite in which
Even if remelting occurs in the secondary mounting soldering described later, it is possible to prevent the matrix metal 5A from flowing out and the resulting short circuit or disconnection.

Next, the structure 15 using the above-mentioned semiconductor device 11 is constructed as shown in (b). Semiconductor device 1
1 is fixed to the external wiring (Cu, thickness: 25 μm) 13 of the wiring board 14 made of the same material as that of the second embodiment by the solder ball 12 for external wiring connection. At this time, the secondary mounting soldering with the solder balls 12 is performed at 260 ° C.

The semiconductor device 1 in the structure 15 of the present embodiment
The failure rate of 1 (disappearance of circuit function due to short circuit or disconnection) was 0.0012%, which was an extremely low value. This is due to the effect of preventing the solder material 5 from flowing out by adding the alumina powder 5B. This outflow preventing effect is based on the suppression of volume expansion, the suppression of fluidity, the clogging phenomenon, and the substantial contact area between the molten matrix metal 5A and the wiring pattern 4 of the remelted solder material 5 due to the alumina powder 5B. Further, since silica powder 12B is added to the external wiring connection solder balls 12 of the structure 15 of the present embodiment, when the structure 15 is mounted on another substrate by heat treatment (3rd mounting soldering: execution Even at a temperature of 250 to 270 ° C., the outflow of the matrix metal 12A and the resulting short circuit or disconnection can be prevented.

In the structure 12 of this embodiment, −30 to 125 is used.
A temperature cycle test of ° C was performed. Here, attention is paid to the disappearance of the circuit function of the semiconductor device 11 due to the crack destruction of the solder layer 5. In the test up to 2000 times, the structure 15 of the present embodiment did not show a defect due to the disappearance of the circuit function of the semiconductor device 11.

The semiconductor device 11 and the structure 1 described above
Finally, No. 5 was installed in a compact radio with TV function equipped with three bands (AM / FM stereo / TV) with a size of 80 × 40 × 12.8 mm.

(Embodiment 21) FIG. 44 is a plan view and a sectional schematic view for explaining a power module device according to another embodiment of the present invention. This insulating semiconductor device 11 is of the 400 A class. After fixing the ceramic insulating substrate 122 and the semiconductor element substrate 6 on the supporting member 125, the epoxy resin case 1
The figure shows a state in which the metal thin wire 7, the epoxy resin lid 131, and the silicone gel resin 10 are filled in the case. (A) is a plan view, (b) is A in (a)
-A 'cross section, (c) shows the BB' cross section in (a), respectively. Here, the ceramic insulating substrate 122 on the supporting member 125 is fixed by solder (thickness: 200 μm) 5 ′, and on the copper plate 4a of the ceramic insulating substrate 122, eight MOS FET element bases (size: 7 m) are formed.
m × 7mm × 0.3mm) 6 is the solder layer (thickness: 200μm)
It is fixed by 5. Each element substrate 6 is wire-bonded with an Al wire (diameter: 400 μm) 7 and is attached to the source electrode 4b, the drain electrode 4a, and the epoxy resin case 130 in advance.
And the auxiliary terminal 141. Further, the temperature detecting thermistor element 340 is brazed by the solder layer 5 (not shown) on the copper plate 4c on the ceramic insulating substrate 122, and the metal plate 7 is used for wire bonding between the copper plate 4c and the auxiliary terminal 141. Then, it is contacted to the outside. Although not shown in the drawing, a silicone adhesive resin is used to fix the epoxy resin case 130 and the supporting member 125. The epoxy resin lid 131 is provided with a recess 225 in its thick portion and the main terminal 140 is provided with a hole 140 ', and a screw (not shown) for connecting the insulated semiconductor device 11 to an external circuit wiring is housed therein. It is like this. The main terminal 140 and the auxiliary terminal 141 are punched into a predetermined shape in advance and are formed by plating a copper plate with Ni plating, and are attached to the epoxy resin case 130 by a transfer molding method.

Here, in the solder layers 5 and 5 ', 10 vol% of alumina powder (particle size: 2 to 7 μm) 5B is added to Sn-5 wt% Sb alloy as the matrix metal 5A.

The supporting member 125 is made of an Al-SiC composite metal member, and has a coefficient of thermal expansion of 8.0 ppm / ° C and a coefficient of thermal conductivity of 17
It has a physical property of 0 W / m · K. The base material of the support member 125 is composed of the SiC particles 12 in the Al matrix 125A.
This is a composite in which 5B is dispersed, and a Ni plating layer (thickness: 5 μm) is formed on the surface. The support member 125 has a size of 74.0 mm × 42.4 mm × 3 mm, and a mounting hole (diameter: 5.6 mm) 125E is provided in the peripheral portion thereof.

The ceramic insulating substrate 122 has a size of 50 mm.
AlN sintered body having a size of × 30 mm × 0.63 mm (coefficient of thermal expansion:
Copper plates 4a (also serving as drain electrodes), 4b (also serving as source electrodes), 4c (for mounting the thermistor) having a thickness of 300 μm are provided on both surfaces of 420 ppm of 4.3 ppm / ° C, thermal conductivity: 160 W / mK. Ag-28 wt% Cu in which 2 wt% of Ti as an active metal is added to a copper plate 4d having a thickness of 250 μm
They are joined by brazing (not shown, thickness: 20 μm). On these surfaces, a Ni layer having a thickness of 5 μm is formed by electroless plating. As a substitute for the AlN sintered body 420, a silicon nitride sintered body (coefficient of thermal expansion:
3.1 ppm / ° C., thermal conductivity: 120 w / m · K) can be used.

According to the above structure, even when the semiconductor element substrate 6 is overheated during operation of the semiconductor device 11 and the solder layer 5 or 5'is remelted, the solder layer 5 or 5'outflows, the semiconductor element substrate is discharged. 6, thermistor element 340
It is possible to prevent the occurrence of problems such as the positional deviation of the. As a result, the predetermined performance of the semiconductor device 11 can be maintained.

[0213]

As described above, according to the present invention, the semiconductor device in which the chip component is mounted on the wiring member by the solder material and the soldered portion is resin-sealed is secondarily mounted on the external wiring member. Outflow of solder material and short circuit due to this
Semiconductor device that can prevent disconnection and misalignment of chip parts,
A structure using this semiconductor device and an electronic device using these can be provided.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional view of a solder layer applied to the semiconductor device of the present invention.

FIG. 3 is a schematic sectional view illustrating a problem when the solder layer is composed of only a matrix metal.

FIG. 4 is a graph illustrating a melting point decrease when Au is fused with Sn-10 wt% Sb solder material.

FIG. 5: Pb-12 wt% Sn-8 wt% Sb-1 wt
It is a graph explaining melting | fusing point fall when Sn fuses to% Ag solder material.

FIG. 6 is a schematic sectional view of the structure of the present invention.

FIG. 7 is a graph illustrating the effect of alumina powder particle size on the short-circuit failure rate after secondary mounting.

FIG. 8 is a graph illustrating the effect of the amount of alumina powder added on the short-circuit failure rate after secondary mounting.

FIG. 9 is a graph illustrating the influence of the amount of alumina powder added on the disconnection failure rate of the structure of the present invention.

FIG. 10 is a schematic cross-sectional view of a lithium ion secondary battery which is an example of the electronic device of the present invention.

FIG. 11 is a circuit block diagram of a semiconductor device incorporated in a lithium ion secondary battery which is an example of an electronic device.

FIG. 12 is a diagram illustrating a multilayer glass ceramic substrate applied to a semiconductor device according to an embodiment.

FIG. 13 is a cross-sectional view showing a manufacturing process of one semiconductor device.

FIG. 14 is a graph illustrating a short circuit failure rate of a structure obtained by applying a semiconductor device exposed to a high temperature and high humidity atmosphere.

FIG. 15 is a circuit block diagram of a power multiplication circuit device as a semiconductor device of one embodiment.

FIG. 16 is a configuration diagram of a magnetic field generation unit.

FIG. 17 is a schematic sectional view illustrating a high frequency power module as a semiconductor device according to another embodiment.

FIG. 18 is a circuit diagram illustrating a semiconductor device according to another embodiment.

FIG. 19 is a schematic cross-sectional view illustrating a structure for a mobile phone.

FIG. 20 is a circuit block diagram of a mobile phone to which the structure of another embodiment is applied.

FIG. 21 is a graph for explaining the disconnection defect rate and the thermal resistance increase defect rate of the structures of other examples.

FIG. 22 is a schematic sectional view illustrating a high frequency power module as a semiconductor device according to another embodiment.

FIG. 23 is a schematic sectional view illustrating a structure for a mobile phone.

FIG. 24 is a schematic sectional view illustrating a semiconductor device according to another embodiment.

FIG. 25 is a schematic sectional view illustrating a structure of another example.

FIG. 26 is a schematic sectional view illustrating a semiconductor device according to another example and a structure using the same.

FIG. 27 is a schematic sectional view illustrating a CSP type semiconductor device according to another embodiment.

FIG. 28 is a schematic sectional view illustrating a semiconductor device according to another embodiment and a structure using the same.

FIG. 29 is a schematic sectional view illustrating another example semiconductor device and a structure using the same.

FIG. 30 is a schematic sectional view illustrating a semiconductor device according to another embodiment and a structure using the same.

FIG. 31 is a schematic sectional view illustrating a modified example of the structure of another embodiment.

FIG. 32 is a schematic sectional view illustrating a semiconductor device according to another example and a structure using the same.

FIG. 33 is a schematic sectional view illustrating a COC semiconductor device of another form.

FIG. 34 is a schematic sectional view illustrating a semiconductor device according to another example and a structure using the same.

FIG. 35 is a diagram illustrating a circuit of a semiconductor device according to another embodiment.

FIG. 36 is a graph illustrating the relationship between the output current and the conversion efficiency of the structure of another example.

FIG. 37 is a schematic sectional view illustrating a semiconductor device according to another embodiment.

FIG. 38 is a graph illustrating the transition of thermal resistance in a temperature cycle test of another example semiconductor device.

FIG. 39 is a graph illustrating a transition of thermal resistance in a power cycle test of another example semiconductor device.

FIG. 40 is a plan view and a cross-sectional view illustrating a full-wave rectifier.

FIG. 41 is a circuit diagram illustrating a full-wave rectifier circuit of another embodiment structure.

FIG. 42 is a schematic sectional view illustrating a full-wave rectifier of another form.

FIG. 43 is a schematic sectional view illustrating a semiconductor device according to another example and a structure using the same.

FIG. 44 is a schematic plan view and a cross-sectional view illustrating a power module device according to another embodiment.

[Explanation of symbols]

1 ... Multilayer ceramic substrate, polyimide substrate, Si substrate, Cu container, 1A ... 1st main surface, 1B ... 2nd main surface, 1C
... Glass-ceramic material, 1D ... Side surface, 2 ... Inner layer wiring layer, 2A ... Through hole wiring, 3 ... External electrode layer, 4 ... Wiring pattern, 5, 5 ', 5 "... Solder layer, Solder material, 5
A ... Matrix metal, 5B ... Non-metal powder, 5a ... Molten solder material, 6 ... Semiconductor element substrate, 6A, 6 '... Integrated circuit element substrate, PWM control integrated circuit substrate, 6B ... FET element substrate, 6C ... Rectifying diode, 7 ... Metal fine wire, TAB wiring, Cu lead, 8 ... Chip resistance, 9 ... Capacitor, 1
0 ... Resin layer, 11 ... Semiconductor device, 12 ... External wiring connection layer, solder ball, 13 ... External wiring, 14 ... Wiring board,
15 ... Structure, 16 ... Break line, 18A, 18
B, 18C, 18D ... Paste, 19 ... Thermal expansion relaxation member, 20 ... Metal case, 21 ... Metal lid, 22 ... Insulating layer,
23 ... Positive electrode, 24 ... Safety valve, 25 ... Flexible printed circuit board, 26, 34, 38 ... Hole, 27, 28 ... Insulation plate, 29 ... Heat shrink tube, 30, 31, 32 ... Connection part, 33 ... Terminal, 35 ... Positive electrode external terminal, 36 ... Negative electrode external terminal, 37 ... Ground terminal, 40 ... Blind type via, 41
... Thermal via, 42 ... Through via, 43 ... Cavity, 44 ... Metal cap, 50 ... Pedestal, 51 ... Solder resist film, 52 ... Antenna duplexer, 55 ... Ni plate, 5
6 ... Au bump, 61 ... FET element for over-discharge prevention, 62
... FET element for overvoltage prevention, 63 ... First green sheet, 64 ... Second green sheet, 70 ... Hall effect element, 71, 72 ... Resistors, 73, 74 ... Input terminal, 75
... voltage conversion circuit, 76 ... voltage-current conversion circuit, 77 ... control current terminal, 78 ... movable terminal, 79, 80 ... voltage output terminal, 81 ... variable resistor, 82, 83 ... output terminal, 84 ...
Core, 85 ... current coil, 86 ... magnetic field gap, 90,
91 ... Heat sink, 92 ... Terminal block, 93 ... Mounting member, 9
4 ... Solder material, 95 ... Cu terminal, 96 ... Insulation sheet, 1
00 ... Electronic device (secondary battery), 101 ... Epoxy resin,
105 ... Electrode, 110 ... Thin film inductor, 122 ... Ceramic insulating substrate, 125 ... Support member, 130 ... Epoxy resin case, 131 ... Epoxy resin lid, 140 ... Main terminal, 140 '... Hole, 141 ... Auxiliary terminal, 225 ... Recess ,
340 ... Thermistor element for temperature detection, 605 ... Laminated metal layer.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasutoshi Kurihara             7-1-1, Omika-cho, Hitachi-shi, Ibaraki Prefecture             Inside the Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Hironori Kodama             7-1-1, Omika-cho, Hitachi-shi, Ibaraki Prefecture             Inside the Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Tsuneo Endo             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Yosuke Sakurai             15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture Hitachi Higashi             Department Semiconductor Co., Ltd. (72) Inventor Koichi Nakajima             15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture Hitachi Higashi             Department Semiconductor Co., Ltd. (72) Inventor Mikio Negishi             15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture Hitachi Higashi             Department Semiconductor Co., Ltd. F-term (reference) 5F044 KK02 LL01

Claims (18)

[Claims] 1. A semiconductor characterized in that a solder layer in which a chip component and a wiring member are fixed to each other is sealed with a resin layer, and the solder layer is composed of a composite in which a nonmetal powder is dispersed in a matrix metal. apparatus. 2. The semiconductor device according to claim 1, wherein the non-metal powder has a melting point higher than a melting point of the matrix metal. 3. The metal according to claim 1, wherein the matrix metal in the solder layer is a metal containing Sn as a main component or Sn, Sb, Zn, Cu, Ni, Au, Ag, P, B.
i, In, Mn, Mg, Si, Ge, Ti, Zr, V,
It is an alloy consisting of two or more kinds selected from the group of Hf and Pd, and the non-metal powder is an oxide, a nitride, a boride, a carbide, a sulfide, a phosphide, a silicide, a fluoride, a simple substance of silicon, A semiconductor device comprising a substance containing at least one selected from the group consisting of germanium simple substance, carbon simple substance, and boron simple substance. 4. The relationship between the density ρ1 of the solder layer and the density ρ2 of the non-metal powder is ρ1 ≧.
A semiconductor device characterized by being ρ2. 5. A semiconductor device according to any one of claims 1 to 4, wherein the non-metal powder having a particle size of 0.05 to 60 μm is added to the matrix metal in an amount of 3 to 75 vol%. 6. The resin layer according to claim 1, wherein the resin layer has a Young's modulus of 90 Pa to 50 GPa or a thermal expansion coefficient of 5 to 9
A semiconductor device having 600 ppm / ° C. 7. The resin layer according to claim 1, wherein the resin layer is an epoxy resin, a silicone resin, a polybutylene terephthalate resin, a polyphenylene sulfide resin,
A semiconductor device comprising at least one selected from the group consisting of polyethylene terephthalate resin, silicone gel resin, silicone rubber resin, polyurethane resin, and phenol resin. 8. The wiring member according to claim 1, wherein the wiring member is a wiring member in which a metal wiring is provided on a base material made of ceramics, resin or semiconductor, or a wiring member using a metal as a base material. A semiconductor device characterized by the above. 9. The wiring member according to claim 1, wherein the wiring member is one kind of ceramic selected from the group consisting of glass ceramics, alumina, aluminum nitride, silicon nitride, glass and beryllia, or glass cloth or glass. Non-woven fabric,
Composite resin obtained by impregnating one kind of base material selected from the group of paper with one kind of resin material selected from the group of epoxy resin, phenol resin, polyimide resin, bismaleide resin and triazine resin, or polyester, polyimide, A semiconductor device characterized in that a film-shaped resin selected from the group of polyimide amides is used as a base material and metal wiring is formed on the base material. 10. The semiconductor device according to claim 1, wherein the wiring member is made of a metal or an alloy containing Cu, Fe, Ni, Co and Al as main components. 11. The semiconductor device according to claim 10, wherein the wiring member is formed in a lead frame shape. 12. A structure, wherein the semiconductor device according to claim 1 is fixed to an external wiring member via a connection layer. 13. The structure according to claim 12, wherein the melting point of the connection layer is higher than the melting point of the solder layer in the semiconductor device. 14. The structure according to claim 13, wherein the material of the connection layer is a Pb-free solder material. 15. The structure according to claim 12, wherein the connection layer is composed of a composite material in which a nonmetal powder is dispersed in a matrix metal. 16. The structure according to claim 12, wherein the external wiring member is superior in heat resistance to the base material of the wiring member provided with the base metal wiring. 17. A semiconductor device in which a solder layer in which a chip component and a wiring member are fixed is sealed with a sealing resin, and the solder layer is composed of a composite material in which a nonmetal powder is dispersed in a matrix metal. An electronic device characterized by the above. 18. A semiconductor device comprising: a solder layer in which a chip component and a wiring member are fixedly sealed with a sealing resin; and the solder layer made of a composite material in which a nonmetal powder is dispersed in a matrix metal. An electronic device in which a structure fixed to an external wiring member is incorporated via the.