JPH1079453A - Molded electronic component and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit an outflow of a molten solder material by a method, wherein a Pb concentration in a solder alloy material is prepared at a specified value or lower. SOLUTION: A semiconductor device 40 is constituted into a structure, wherein a semiconductor base body 21, a chip resistor 22 made of ceramics, a chip capacitor 23 and a terminal 24 are secured conductively and mechanically on a circuit board 10 of a structure, wherein a copper wiring layer 3 is selectively formed on the main surface of an Al plate 1 via an insulating resin layer 2 with a solder material 25. This solder material 25 contains two or more kinds of metals, which are selected from a group of Sn, Sb, Ag, Cu, Zn, In and Bi, and Pb as its main component. A Pb concentration in the solder material 25 is prepared at about 10wt.% or lower. Moreover, a bonding is performed on the base body 21 using a metal wire, and these mounted components 21 to 25 and the board 10 are hermetically sealed with a molding resin 30 with selected coefficient of thermal expansion of about 10 to 20ppm/ deg.C. Thereby, a thermal fatigue resistance and airtightness of soldered parts are enhanced, and a refusion of solder in a thermal process is inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a molded electronic component which is excellent in thermal fatigue resistance and airtightness of a soldered portion and is suitable for suppressing a short circuit in a circuit wiring, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Heretofore, a member for supporting a semiconductor element substrate often also serves as one electrode of a non-insulated semiconductor device.
For example, a power transistor chip is mounted on a copper base with Pb
In a power transistor device integrally mounted with -Sn solder material, a copper base (metal support member) also serves as a collector electrode and a support member of the transistor. In such a semiconductor device, a collector current of several amperes or more flows, and the transistor chip generates heat. In order to avoid instability of characteristics and deterioration of life due to the heat generation, the copper base also serves as a member for heat dissipation. Further, when a semiconductor element substrate having a high withstand voltage and a high frequency and capable of flowing a large current is directly soldered and mounted on the copper base, the role of the copper base as a heat dissipation relay member becomes more important.

In addition, a structure has emerged in which all electrodes of a semiconductor device are electrically insulated from a metal support member, thereby increasing the degree of freedom in circuit application of the semiconductor device. In such an insulated semiconductor device, all the electrodes are insulated from all the package members including the metal supporting member by the insulating member and are drawn out to the outside. Therefore, even in a usage example in which the pair of main electrodes is floating from the ground potential on the circuit, the package can be fixed to the ground potential portion regardless of the electrode potential, so that the semiconductor device can be easily mounted.

[0004] Even in an insulated semiconductor device, in order to operate a semiconductor element safely and stably, it is necessary to efficiently dissipate heat generated during operation of the semiconductor device to the outside of a package. This heat dissipation is usually achieved by transferring heat from the semiconductor substrate, which is a heat source, to the air through the members adhered to the semiconductor substrate. In an insulated semiconductor device, the heat transfer path includes an adhesive layer used for a portion for bonding an insulator, a semiconductor substrate, and the like.

Further, as the power handled by a circuit including a semiconductor device increases, or as the required reliability (eg, stability over time, moisture resistance, heat resistance, etc.) increases, complete insulation is required. The heat resistance referred to here includes not only the case where the ambient temperature of the semiconductor device rises due to an external factor, but also the heat resistance when the power handled by the semiconductor device is large and the heat generated in the semiconductor base is large.

On the other hand, in a hybrid integrated circuit device or a semiconductor module device, since a certain electric circuit including a semiconductor element is generally incorporated, at least a part of the circuit and a metal portion such as a support member or a heat radiation member of these devices are included. Must be electrically insulated. For example, the first
"IMST Substrate" by Kazami Akira as a prior art example: Industrial Materials (Vol. 30, No. 3), pp. 22-26 (19)
1983) has a thin alumite layer on both sides (14-30μ)
A substrate for a hybrid integrated circuit device in which a copper foil (35 μm) is formed on one surface of an aluminum substrate (1-2 mm) on which an m) is formed via an epoxy-based insulating resin layer (28 μm). Also disclosed is a hybrid integrated circuit device in which a power semiconductor element and a passive element are mounted by soldering on the hybrid integrated circuit device substrate on which the copper foil is selectively etched and circuit wiring is provided.

As a second prior art example, “An Improvement on SolderJoint Reliability for
Aluminum Based IMST Substrate ”: IMC 1922Proceedin
gs, pp. 525-532 (1992), a power transistor element, a ceramic chip capacitor, and a chip resistor are mounted on the above-mentioned hybrid integrated circuit board with Pb-60 wt% Sn-based solder material, and these mounted elements are made of aluminum. Hybrid IC molded with epoxy resin having the same coefficient of thermal expansion (25 ppm / ° C)
An apparatus is disclosed. This prior art example discloses that it is preferable to mold with a resin of 25 ppm / ° C. whose thermal expansion coefficient is substantially equivalent to that of the substrate (Al).

The hybrid integrated circuit devices based on the prior art examples 1 and 2 are excellent in mass productivity and have many economic advantages, and are widely used in the field of semiconductor mounting.

The hybrid integrated circuit device and the hybrid IC device based on the above-mentioned prior art examples 1 and 2 are mechanically attached to a heat sink such as an aluminum fin or the like, in order to promote heat radiation, or printed with an external circuit formed thereon. It is used after being soldered to something like a circuit board.

[0010]

In the case of a hybrid integrated circuit device or a hybrid IC device (hereinafter referred to as a semiconductor device) based on prior art examples 1 and 2, a mounted component having a small coefficient of thermal expansion [for example, a semiconductor element substrate] : 3.5 ppm / ° C (S
i), chip resistor: 7 ppm / ° C. (alumina), chip capacitor: 10 ppm / ° C. (barium titanate)], but P on a circuit board (Al: 25 ppm / ° C.) having a large coefficient of thermal expansion.
The b-Sn alloy material is fixed by soldering. The soldering portion fixes the mounted component at a predetermined position on the substrate and plays a role of wiring and a heat dissipation path of the semiconductor device. However, the above-mentioned semiconductor device is repeatedly subjected to thermal stress during operation or at rest, which eventually causes thermal fatigue failure of the soldered portion. In particular, if the coefficient of thermal expansion of the mold resin is not properly adjusted with respect to the circuit board, excessive residual stress will be inherent in the interface between the two, and the thermal stress during operation of the semiconductor device will be superimposed on this. Then, the thermal fatigue fracture of the soldered portion is further accelerated. When this thermal fatigue fracture progresses, adverse effects such as disconnection and interruption of a heat dissipation path occur. As a result, the semiconductor device loses its circuit function.

In addition, Pb-60 is used for soldering mounted components.
When the wt% Sn alloy material is used, the following problems occur when the semiconductor device is soldered to the printed wiring board. Generally, a semiconductor device is mounted on a printed wiring board using Pb-60 wt% Sn (melting point: 183 ° C., working temperature: 220 ° C.). At this time, a part of the Pb-60 wt% Sn alloy material to which the mounted components are fixed is also melted.
The molten solder material expands in volume and generates a large pressure, and peels off the bonding portion between the circuit board and the mold resin. As a result, the molten solder flows out through the separation gap, causing an electrical short circuit between the wirings, thereby impairing the circuit function of the semiconductor device. On the other hand, when the Pb-5 wt% Sn alloy material having a high melting point is used for soldering the mounted components, the outflow of the molten solder material does not occur as described above. However, for soldering, it is necessary to heat the circuit board to 300 ° C. or higher. In this case, the dielectric strength of the circuit board is reduced due to the thermal deterioration of the insulating resin layer in the circuit board. This also leads to a decrease in the circuit function of the semiconductor device.

Furthermore, in the case of the semiconductor devices based on the prior art examples 1 and 2, if the coefficient of thermal expansion of the mold resin with respect to the circuit board is not properly adjusted, excessive residual stress is present at the joint interface between them. However, thermal stress during operation of the semiconductor device is superimposed thereon, and peeling of the bonding interface between the circuit board and the mold resin further progresses. In such a case, moisture enters the inside of the semiconductor device and impairs the internal circuit function.

The above technical problems, particularly the problem of the outflow of the molten solder material, occur in a semiconductor device in which mounted components are soldered on a circuit board having metal wiring on a ceramics plate, and this is hermetically sealed with a resin. Also common.

It is therefore an object of the present invention to provide an improved molded electronic component which solves the above-mentioned problems, particularly the problem of outflow of molten solder.

[0015]

According to the present invention, there is provided a molded electronic component in which a mounting component comprising a semiconductor element substrate and a passive element is conductively and mechanically fixed on a circuit board having a metal wiring layer. In a semiconductor device in which a mounted component is covered with a mold resin, the mounted component is
Two or more metals selected from the group consisting of n, Sb, Ag, Cu, Zn, In and Bi are fixed by an alloy material containing Pb as a main component, and the Pb concentration in the alloy material is adjusted to 10 wt% or less. This is a first feature.

In the electronic device according to the present invention, a mounting component including at least one selected from the group consisting of a semiconductor element base, a passive element, and a terminal is fixed on a circuit board provided with a metal wiring with a first alloy material. The circuit board and the mounted components are covered with a mold resin, and the first alloy material is Sn,
Two or more kinds of metals selected from the group consisting of Sb, Ag, Cu, Zn, In and Bi, and an electronic component which is an alloy containing Pb as a main component and having a Pb concentration adjusted to 10 wt% or less, are formed on an external circuit board. The fact that the second alloy material has fixed
The feature of.

According to the method of manufacturing a molded electronic component of the present invention, a mounted component including at least one selected from the group consisting of a semiconductor element base, a passive element, and a terminal is fixed on a circuit board provided with metal wiring by an alloy material. In a method of manufacturing a semiconductor device in which the circuit board and the mounted components are covered with a mold resin, a Pb-Sn alloy layer is provided on the mounted components,
The mounting component is fixed on the metal wiring with a brazing material made of two or more kinds of metals selected from the group consisting of n, Sb, Ag, Cu, Zn, In and Bi, and Sn, Sb, Ag, C
An alloy comprising Pb and two or more metals selected from the group consisting of u, Zn, In and Bi is formed, and the Pb concentration in the alloy is adjusted to 10 wt% or less.

The above configuration will be described with reference to the drawings.

FIG. 1 is a sectional view illustrating a semiconductor device according to the present invention. The semiconductor device 40 includes a semiconductor element substrate 21, a ceramic chip resistor 22, and a chip capacitor 23 on a circuit board 10 in which a copper wiring layer 3 is selectively formed on the main surface of an Al plate 1 via an insulating resin layer 2. And the terminal 24 made of phosphor bronze is Sn, Sb, Ag, C
Two or more kinds of metals selected from the group consisting of u, Zn, In and Bi are conductively and mechanically fixed by a solder material 25 containing Pb as a main component, and bonding to the semiconductor element substrate 21 by a metal wire 26 is performed. These mounted components 2
1, 22, 23, 24, 25, 26 and the substrate 10 are molded resin 30 having a coefficient of thermal expansion of 10 to 20 ppm / ° C.
And the P in the solder material 25
The b concentration was adjusted to 10% by weight or less.

The Pb in the solder material 25 is particularly the passive element 2
A Pb-Sn-based alloy material layer provided in advance on the surface of the soldering portion of the mounted component such as the terminals 2, 23 and the terminals 24 is used as an introduction source. The surface Pb-Sn-based alloy material layer is provided for the purpose of imparting wettability to the solder material of the mounted component.

FIG. 2 is a schematic sectional view for explaining a semiconductor device of the present invention having the second feature. In the semiconductor device 40, the terminals 24 are fixed to an external circuit board 50, such as a printed board, on which circuit wiring is provided, by a second alloy material 51 containing Pb and Sn as main components. At this time, although not shown, a passive element including a semiconductor element base 21, a ceramic chip resistor 22, and a chip capacitor 23,
The terminals 24 made of phosphor bronze are Sn, Sb, Ag,
It is fixed on the circuit board 10 by a first alloy material 25 containing two or more kinds of metals selected from the group consisting of Cu, Zn, In and Bi as main components.

The solder material 25 according to the present invention is for electrically and firmly fixing the mounted components, and is required to have an essentially high thermal fatigue resistance. FIG. 3 shows the thermal fatigue resistance of the solder material 25 as the temperature cycle number dependency of the thermal resistance between the heat radiation paths from the semiconductor element substrate 21 to the Al plate 1. In the figure, A is Sn-5 wt% Sb material as solder material 25, B is Pb-60 wt% Sn material,
C shows the case where a Pb-5 wt% Sn material is applied.
In the case of A, the change in thermal resistance is hardly exhibited until the number of temperature cycles reaches 500. On the other hand, in the case of B and C, the fluctuation (increase in thermal resistance) starts to occur from about 50 times. The increase in thermal resistance is caused by cracking of the solder material due to fatigue destruction due to thermal fluctuations, thereby interrupting the heat radiation path. As described above, when the alloy material A according to the present invention is applied, the resistance to thermal fatigue fracture is superior to the case where the conventional component mounting solder materials B and C are applied. This is based on the fact that the rigidity of the Sn-5wt% Sb material is higher than that of the Pb-60wt% Sn material or the Pb-5wt% Sn material, and is less likely to be plastically deformed. As an alternative to the alloy material A, for example, Sn-3.5 wt% Ag-1.
5 wt% In-7.5 wt% Pb, Sn-10 wt% Zn-
1.5 wt% In-0.5 wt% Pb, Sn-4 wt% Ag-2
wt% Zn-2wt% Bi-3.5wt% Pb, Sn-4.5wt
% Cu-1.7 wt% Pb, Sn-4 wt% Cu-3 wt% A
g-5.2 wt% Pb, Sn-2 wt% Sb-1 wt% Cu-
2wt% Ag-2wt% Zn-4.2wt% Pb
An alloy material mainly composed of Pb and two or more kinds of metals selected from the group consisting of Sn, Sb, Ag, Cu, Zn, In and Bi may be used. In this case, the alloy material has a low Pb content, which helps to solve the problem of environmental pollution due to the toxicity of Pb.

The mold resin 30 of the present invention is for protecting the mounted components mechanically or hermetically sealing them. Further, the mold resin 30 is integrated with the circuit board 10, and at this time, it is desirable that no internal stress is introduced into the integrated interface. The first reason is that the circuit board 1
The components 21, 22, 23, 24, 25, and 26 are soldered and mounted on the soldering material 0, and when the internal stress accompanying the integration is introduced into the solder material 25 fixing these components, the subsequent operation is performed. This is because the stress caused by the temperature change at the time is superimposed, so that thermal fatigue fracture is likely to occur. The second reason is that if an internal stress is built into the integrated interface 27 or 27 '(see FIG. 1) between the mold resin 30 and the circuit board 10, the stress caused by a temperature change during the subsequent operation is superimposed and becomes excessive. The interface 27 or 27 'is peeled off due to the generation of a large interfacial stress. As a result, moisture in the operating environment is reduced to the interface 27 or 2
7 ', the circuit wiring 3, circuit elements 21, 22, 23, terminals 24, metal wires 2
6 and impairs the normal circuit function of the semiconductor device 40.

FIG. 4 is a graph for explaining the amount of warpage of the integrated product of the mold resin 30 and the circuit board 10. here,
The dimensions of the circuit board 10 are 20.5 mm × 38 mm × 1.5 mm, and the thickness of the mold resin 30 is 2 mm. A plus amount of warpage means that the substrate 10 side is convex, and a minus amount of warpage means that the mold resin 30 side is convex. Curve A is Sn-5
The wt% Sb material and the curve B represent the case where components are mounted using the Pb-60 wt% Sn material. Longitudinal direction (38mm)
Indicates a large positive value as the coefficient of thermal expansion of the mold resin 30 increases. The initial warp amount in the longitudinal direction of the substrate 10 is 20 μm (broken line in the figure). In order to prevent the interface internal stress from being introduced after the transfer molding, the warpage after the molding needs to be close to the initial warpage of the substrate 10 (preferably within ± 10 μm). Judging from such a viewpoint, the molding resin 3
It is desirable that the coefficient of thermal expansion of 0 is selected in the range of 10 to 20 ppm / ° C. On the other hand, in the case of B, 22 to 30 ppm
It shows that the range of / ° C is appropriate. Pb-6
Since the 0 wt% Sn material is soft and easily deformed plastically, it easily absorbs stress based on the difference in thermal expansion coefficient between the mounting component having a relatively low thermal expansion coefficient and the circuit board 10. As a result, the amount of warpage is hardly affected by the coefficient of thermal expansion of the mounted component. On the other hand, in the case of the Sn-5 wt% Sb material 25, since the material has high rigidity and is not easily plastically deformed, the stress based on the difference in thermal expansion coefficient between the mounted component and the circuit board 10 is hardly absorbed. As a result, the amount of warpage tends to be affected by the coefficient of thermal expansion of the mounted component. This is the main reason why the appropriate expansion coefficient range of the mold resin 30 differs between A and B,
This is a new technical problem in the case of the Sn-5 wt% Sb material 25.

For example, as the solder material 25, Sn-4.3w
A semiconductor device 40 using a combination of t% Sb-1.4 wt% Pb material and a mold resin 30 having a thermal expansion coefficient of 15 ppm / ° C.
In the case of, a temperature cycle test (−55 to 150 ° C., 50
00) after high temperature and high humidity bias test (80 ° C, 85% R)
H, the applied voltage between wires: 500 V, 1000 h) does not impair the circuit function of the semiconductor device.
On the other hand, as the solder material 25, Pb-60wt% Sn material or Sn
-4.5 wt% Sb-10.4 wt% Pb material, molding resin 3
In the case of a semiconductor device using an epoxy resin having a thermal expansion coefficient of 8 ppm / ° C. and 25 ppm / ° C. as 0, the mounted components (21, 22, 23, 24, 25) are obtained from 2500 times of a single temperature cycle test (−55 to 150 ° C.) , 26) Fatigue rupture of the solder connection portion 25 occurs, and the circuit function of the device is impaired.
In addition, a single high temperature and high humidity bias test (85 ° C, 85% R
H, the applied voltage between wirings: 500 V) also causes a short circuit due to migration between the wirings 3 for a test time of 500 h. This is because the bonding interface between the mold resin 30 and the substrate 10 is separated and moisture is easily introduced into the device 40.

Therefore, according to the present invention, Sn, Sb, Ag, Cu, Z having an essentially high thermal fatigue fracture resistance.
two or more metals selected from the group consisting of n, In and Bi, a solder material 25 containing Pb as a main component, and a thermal expansion coefficient of 10
By combining with the mold resin 30 adjusted to 20 ppm / ° C. and adjusting the Pb concentration in the solder material 25 to 10 wt% or less, it is possible to provide the semiconductor device 40 in which the component mounting portion is more highly reliable.

However, when the Pb concentration in the solder material 25 is high, the following problem occurs. FIG.
4 shows a differential scanning calorimetry curve of an Sb-based solder material and a Sn-Sb-Pb-based solder material. (A) Sn-4.5 wt% Sb
186.6 ° C and 224.9 for -10.4 wt% Pb material
° C (hereinafter, the lower end is referred to as a first endothermic peak, and the higher end is referred to as a second endothermic peak).
In the case of Sn-5 wt% Sb of (b), an endothermic peak is shown at 242.6 ° C. As described above, if an excessive amount of Pb is contained in the solder material 25, Sn-5 wt%
Melting starts at a temperature significantly lower than the original melting point of the Sb alloy. FIG. 6 shows a schematic sectional view of the component mounting portion. The passive element 22 is soldered 25 on the metal wiring layer 3 and covered with a mold resin 30. Solder this part to the printed wiring board (Pb-60 wt% Sn, melting point: 18
(3.degree. C., working temperature: 225.degree. C.), the element 22 is fixed to Sn-4.5 wt% Sb-10.4.
The wt% Pb material 25 changes from a solid phase to a completely molten state, and during this time, a 1.16-fold volume expansion occurs. At this time, the molten solder 25 receives a compressive force in a closed space formed by the mold resin 30, the circuit board 10, and the element 22. Assuming that the volume expansion rate of the solder material 25 is β (3800 ppm / ° C., estimated from the volume expansion) and the compressibility is κ (0.2 GPa- ¹ ), the melting start (186.6 ° C.) to the melting end (224.9 ° C.) The pressure change dP of the solder material 25 generated in the process is expressed by the following equation (1).

DP = (β / κ) dT (1) Here, if dT: (melting end temperature) − (melting start temperature), dP is about 81 kgf / mm ² , and the pressure is greatly increased. Occurs force F ₁ in the mold resin 30 of the element 22 mounting portion in accordance with the pressure increase, the interface of the soldered portion substrate 10 and the molding resin 30 in the vicinity in conjunction acts peel force F _2. On the other hand, the adhesive force at the interface between the substrate 10 and the mold resin 30 is as small as about 5 kgf / mm ^2, and the interface is easily peeled off by the action of the peeling force F ₂ . As a result, the molten solder material 25 passes through the gap caused by the peeling, thereby forming the nearby metal wiring layer 3 ′.
Spill to the electrical outlet and cause an electrical short.

According to the present invention, the Pb concentration of the solder material 25 is adjusted to 10 wt% or less as a measure for suppressing the above-mentioned solder outflow and the accompanying short circuit between wirings. FIG. 7 shows Sn—Sb—Pb
4 shows the Pb concentration dependency of the endothermic peak intensity of a system solder material.
Here, the endothermic peak strength is represented by an endothermic amount per 1 mg of the solder material. The first endothermic peak intensity increases with concentration, while the second endothermic peak intensity decreases. FIG. 8 shows the Pb concentration dependence of the endothermic peak temperature of the Sn—Sb—Pb-based solder material. While the first endothermic peak temperature increases slowly with concentration, the second endothermic peak temperature shows a significant decrease from 243 ° C (0 wt%) to 210 ° C (about 20 wt%). In order to suppress the melting of the solder material in the process of raising the temperature to 225 ° C., it is necessary that the first endothermic peak strength is low and the second endothermic peak temperature is high.
At this time, it is desirable that the first endothermic peak intensity is 0.5 mW / mg or less and the second endothermic peak temperature is 225 ° C. or more. The Pb concentration selected from such a viewpoint is 10 wt%.
It is as follows.

According to the above countermeasures, even when the heat treatment for soldering the printed wiring board is performed, the semiconductor device 40
Out of the solder material and short circuit between the wirings can be prevented.

In the present invention, Pb-
A Sn alloy layer is provided, and Sn, Sb, Ag, Cu, Zn, I
The mounting component is fixed on the metal wiring with a brazing material made of two or more kinds of metals selected from the group consisting of Sn, Bi, and Sn,
An alloy consisting of two or more metals selected from the group consisting of Sb, Ag, Cu, Zn, In and Bi and Pb is formed, and the Pb concentration in the alloy is adjusted to 10 wt% or less. At this time, the composition or thickness of the Pb—Sn alloy layer, or the weight or volume of the brazing material is adjusted. _{Specifically, C = A · ρ p ·} t p / ρ p · t p + ρ s · t s ... (2) where, C: Pb concentration in the alloy A: of Pb in Pb-Sn alloy layer the weight ratio [rho _p: specific gravity of Pb-Sn alloy layer t _p: thickness of the Pb-Sn alloy layer [rho _s: density of the braze t _s: C is the a calculated in becomes thick formula of the brazing material, [rho _p, t _p, is adjusted by at least 1 selected from the group of ρ _s, t _s.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to embodiments.

[Embodiment 1] The semiconductor device 40 of this embodiment
As shown in FIG. 1, a circuit board 10 (20.5 mm × 38 mm × 1) in which a copper wiring layer 3 (70 μm) is selectively formed on a main surface of an Al plate 1 via an insulating resin layer 2 (80 μm). .5m
m) A power MOSFET device 2 as a semiconductor device substrate
1, ceramic chip resistor 22, chip capacitor 2
3 and a terminal 24 made of phosphor bronze
Are conductively and mechanically fixed by a Sn-4.3 wt% Sb-1.4 wt% Pb solder material 25, and
Are bonded by metal wires 26 (not shown), and these mounted components 21, 22, 23, 24, 2
5, 26 and the substrate 10 are transfer-molded with an epoxy resin 30 having a coefficient of thermal expansion of 16 ppm / ° C. and hermetically sealed.

The semiconductor device 40 of the present embodiment has a structure shown in FIG.
As shown in the block diagram of the semiconductor device of the present embodiment, a gate drive circuit for driving the semiconductor element 21 and a control unit for controlling the drive circuit are built in. This semiconductor device employs a resonance power supply control IC, houses a power MOS transistor with a withstand voltage of 200 V, and is a compact, high-efficiency, low-noise resonance-type power supply device.
Particularly, it is suitable for a power supply of a resonance type AC / DC converter. In the case of the resonance type AC / DC converter, a performance with an efficiency of 90% or more is obtained at a switching frequency of 1 MHz. This includes (1) overcurrent and overvoltage protection functions, (2) overheat protection functions, (3) gate drive circuits, (4) soft start functions, and (5) two built-in power MOS transistors with uniform characteristics. Based on what you do.

The semiconductor device 40 is mounted on a printed circuit board 50 by soldering the terminals 24 with a Pb-60 wt% Sn alloy 51 as shown in FIG. Say). In this soldering, Pb-60wt% Sn is added to a predetermined portion of the printed circuit board.
After printing the solder paste, the semiconductor device is mounted so that the terminals 24 correspond to the printed portions, and these are heated to 225 ° C. In the semiconductor device 40 of the present embodiment,
Circuit components 21, 22, 23, 24, 25, 2 inside the device
All of Nos. 6 were connected with Sn-4.3 wt% Sb-1.4 wt% Pb solder material 25 having a first endothermic peak intensity as low as 0.1 mW / mg or less and a second endothermic peak temperature as high as about 241 ° C. Therefore, there is no re-melting of the solder material 25 in the printed circuit board soldering process. Therefore,
The circuit constants in the apparatus do not change even after the printed circuit board has been soldered.

On the other hand, Pb-60 wt% Sn solder material and Sn-Sb-Pb based solder material (Pb concentration: 15 wt%)
In the case of the comparative example semiconductor device in which the circuit components 21, 22, 23, 24, 25, and 26 are mounted on the circuit board 10,
In the printed circuit board soldering process at 25 ° C., the above-mentioned solder material was re-melted, and the circuit constant in the device fluctuated. Also,
Pb-60wt% Sn solder material and Sn-Sb-Pb-based solder material (Pb concentration: 15wt%) are 1.16 by re-melting.
Double volume expansion occurs. At this time, the circuit components 21, 22,
23, 24, 25, 26, the pressure applied to the molten solder material in the enclosed space constituted by the mold resin 30 and the circuit board 10 reaches 80 kg / mm ² or more, and the mold resin 30 separates from the circuit board 10 and melts at the same time. The solder material flows out through the peel gap.

When the leak current was measured between the wirings having an interval of 2 mm, the semiconductor device 40 of this example showed that all of the ten samples were as low as 0.1 μA or less (applied voltage: 200 V).
Good insulation was maintained. On the other hand, in the case of the semiconductor device of the comparative example, 7 out of 10 samples (Pb-60 wt% Sn
3 out of 10 samples (Sn-
Sb-Pb based solder material) showed a high value of 100 mA or more (applied voltage: 1 V), and good insulation was not obtained. This is based on the short circuit between the wirings 3 due to the outflow described above. Further, in the semiconductor device 40 of the present embodiment, since re-melting does not occur in the printed board soldering step, the wiring 3
There is no short circuit between them.

For example, the circuit components 21, 22, 23,
In order to mount 24, 25, and 26 on the circuit board 10 using a Pb-5 wt% Sn material having a high melting point, it is necessary to heat to a temperature of 300 ° C. or more. In this case, the dielectric strength of the resin layer 2 is reduced due to the thermal deterioration of the insulating resin layer 2 in the circuit board 10 (the wiring 2-the Al plate 1 is short-circuited by applying an AC effective value voltage of 1500 V). However, in the semiconductor device 40 of the present embodiment, the insulating resin layer 2 is not deteriorated because it has not passed through a heat process of 300 ° C. or more, and the electrical insulation between the wiring 2 and the Al plate 1 is good even when the AC voltage is applied. Shows sex.

FIG. 10 shows a thermal fatigue rupture life of a soldered portion of a chip resistor by a temperature cycle test. In the drawing, the mark ○ indicates the case where the mold resin 30 is not provided, and the mark □ indicates the case where the mold resin 30 is provided. When the mold resin 30 is not provided, the number of rupture cycles changes due to the temperature difference between the high temperature and the low temperature during the temperature cycle. When a straight line is applied to the lower limit of the number of break cycles, a solid line is obtained.
This represents the thermal fatigue rupture life of the non-mold structure soldered portion. On the other hand, when the mold resin 30 is provided, no break is observed at the time of 6000 times even under the condition of the temperature difference of 205 deg (square mark). When the result of the non-mold structure is applied to the square mark by applying the linear damage rule, the life characteristic indicated by a broken line is obtained. From the life characteristics of the mold structure, when the rupture life of the semiconductor device under actual operating conditions (temperature difference: 70 deg) is estimated, it is estimated to be about 170,000 times or more. The reason why such a long rupture life was obtained in this embodiment is that (1) the solder material 25 itself has excellent heat-resistant fatigue characteristics,
(2) It is based on the fact that no internal stress is built into the integrated interface between the mold resin 30 and the circuit board 10, and no excessive stress acts on the soldered portion even when an external thermal stress is superimposed.

FIG. 11 shows a thermal fatigue rupture life of a soldered portion of a chip capacitor by a temperature cycle test. The way to read the figure is the same as in FIG. The breaking life under actual operating conditions (temperature difference: 70 ° C.) in the case of a capacitor is
It is estimated to be about 1 million times or more. The reason why such a long breaking life was obtained is basically the same as that of the chip resistor. Note that a longer life can be obtained with a chip capacitor than with a chip resistor. This is because the chip capacitor (base material: barium titanate) is more excellent in the matching of the coefficient of thermal expansion with the substrate 10 than the chip resistor (base material: alumina).

FIG. 12 shows the transition of the thermal resistance of the power MOS FET element mounting portion. The curve A in the figure is the semiconductor device 40 of the present embodiment, and the curves B and C are the cases where the coefficient of thermal expansion of the mold resin is 8 ppm / ° C. and 25 ppm / ° C., respectively (Comparative Example, solder material: Sn—Sn—Pb, Pb Concentration: 5 wt%).
Curve A shows no increase in thermal resistance in tests up to 20,000 temperature cycles, whereas curves B and C show 2
It shows an increase after 000 times and 4000 times. The reason why the long break life was obtained in the case of the semiconductor device 40 of the present embodiment is basically based on the same reason as in the case of the chip resistor. Conversely, in the case of the comparative example, since an internal stress is built into the integrated interface between the mold resin and the circuit board, an excessive thermal stress is superimposed and an excessive stress acts on the soldered portion. This is the reason why the thermal fatigue rupture of the soldered portion easily occurs in the comparative example.

FIG. 13 shows the thermal fatigue rupture characteristics of the terminal soldered portion. The curve A in the figure indicates the semiconductor device 40 of the present embodiment,
Curves B and C are respectively 8 ppm of thermal expansion coefficient of mold resin.
/ ° C and 25 ppm / ° C (Comparative example, solder material:
(Sn—Sb—Pb system, Pb concentration: 15 wt%, terminal: phosphor bronze). Curve A shows a 0% rupture rate in a test with 20,000 temperature cycles, while curves B and C show an increase in the rupture rate after 500 and 1000 times, respectively. The reason why the semiconductor device 40 of the present embodiment has a long life of rupture and the case of the comparative example has a short life is based on basically the same reason as in the case of the chip resistor.

As described above, Pb in the solder material 25
Is based on a solder plating layer provided in advance on the surface of the mounted component to ensure solder wettability. At this time, in this example, the Pb concentration was adjusted by the following method. FIG. 14 is a schematic sectional view of a component mounting portion before and after soldering. Before soldering, for example, Pb-60 wt% Sn (specific gravity: 8.5 g / c) having a thickness of 5 μm is formed on the part 22 side.
m ³ ) The plating layer 25A and the Sn-
5 wt% Sb solder paste 25B (converted thickness of metal:
30 μm, specific gravity of metal: 7.3 g / cm ³ ). When these are soldered, the plating layer 25A and the solder 25B fuse, and the Sn-Sb-Pb-based solder material 2
5 are formed. In this model, the concentration of the constituent metal in the solder material 25 is expressed by equation (2).

[0044] _{C = A · ρ p · t} p + B · ρ s · t s / ρ p · t p + ρ s · t s ... (3) Here, ρ _p and ρ _s is and solder each plating layer 25A 25B specific gravity, the thickness of t _p and t _s is solder respectively plating layer 25A 25B, and, a and B plated layer 25A
And the weight ratio of each metal in the solder 25B.

FIG. 15 shows the Pb concentration in the solder material after soldering calculated by the equation (2). Here, the curve A indicates that the plating layer 25A is composed of Pb-5wt% Sn (specific gravity: 10.
7 g / cm ³ ), curve B is Pb-60 wt% Sn, and
Curve C is for the case composed of Pb-90 wt% Sn (specific gravity: 7.4 g / cm ³ ). The Pb concentration decreases as the thickness of the solder 25B increases. Curve A: Solder 25B is 65μ
m and more than 20 μm in the case of the curve B, the Pb concentration becomes 10 wt% or less. In the case of the curve C, the Pb concentration can be adjusted to 10% by weight or less even when the solder 25B is 5 μm or less. In this case, if the concentration is 5 μm or more, the Pb concentration is 1
0 wt% or less can be satisfied. FIG. 16 shows Pb-Sn
The composition of the plating and the thickness of the solder material at which the Pb concentration becomes 10% by weight or less are shown. Here, the curve A has a thickness of the plating layer 25A of 2.5 μm, the curve B has a thickness of 5 μm, and the curve C has a thickness of 10 μm.
μm. In any case, if the solder layer 25B is adjusted to have a thickness equal to or greater than the thickness represented by the curve, the Pb concentration can be controlled to 10 wt% or less.

As described above, in this embodiment, the solder material 25
Is the composition or thickness of the plating layer 25A, or
It was controlled by adjusting the thickness of the solder 25B. The Pb concentration of the solder material 25 can be controlled by other methods. For example, the plating layer 25A can be formed by a technique such as vapor deposition or sputtering. At this time, the composition can be adjusted together. Also, solder 25B
Is not limited to a paste. For example, a sheet-like material may be used.

[Embodiment 2] In this embodiment, a semiconductor device equipped with an IGBT element base and a diode element base as heating elements will be described.

FIG. 17 is a sectional view illustrating a semiconductor device 40 according to the present embodiment. The semiconductor device 40 has a copper wiring layer (thickness 10 mm) on the main surface of an Al plate (thickness 3 mm, area 55 mm × 70 mm) 1 via an epoxy insulating resin layer (thickness 35 μm) 2.
0 μm) on the circuit board 10 on which 3 is selectively formed.
T element base (13 mm × 13 mm, 4 pieces) 21 a, diode element base (13 mm × 13 mm, 2 pieces) 21 b, and terminal 24 are provided on copper wiring layer 3 with Sn-4.5 wt% Sb-4.4.
It is conductively and mechanically fixed by a wt% Pb solder material (thickness: 200 μm) 25. Further, the bases 21a, 21
b between the copper wiring layer 3 and the Al wire 26 having a diameter of 300 μm.
(Not shown) bonding is performed. These mounted components 21a, 21b, 24, 26 and the substrate 10
Is hermetically sealed by transfer molding using an epoxy resin 30 having a coefficient of thermal expansion of 12 ppm / ° C.

The semiconductor device 40 having the above configuration has a warp on the epoxy resin 30 side. The warpage amount was as small as 33 μm. The initial warpage of the Al plate 1 was 26 μm (the mounting side of the components 21a, 21b, 24, and 26 was convex), and the fluctuation of the warpage after the completion of the semiconductor device 40 was extremely small. Therefore, the component 21
a, 21b, 24, and 26, the solder material 25 of the mounting portion includes:
Less stress remains. On the other hand, the coefficient of thermal expansion is 9 ppm /
In the case of the comparative example semiconductor device in which the transfer molding was performed using the epoxy resin 30 at a temperature of 2 ° C., the amount of warpage after completion of the device was as small as 2 μm (the amount of warpage: 22 μm).
m).

The semiconductor device 40 of the present embodiment and the semiconductor device of the comparative example were completely energized so that the temperature of the substrate 10 fluctuated within a range of 30 to 100 ° C. Number of complete energization 5
The thermal resistance between the element (21a, 21b) and the Al plate 1 after 10,000 times is 1.07 of the initial thermal resistance in the semiconductor device 40 of this embodiment.
On the other hand, it was 2.25 times in the comparative example semiconductor device. The reason why the thermal resistance of the semiconductor device 40 of the present embodiment is small is that the solder material 2
This is because interruption of the heat flow path due to the destruction of the solder material is suppressed due to the fact that no excessive thermal stress acts on the solder material 5 and the excellent thermal fatigue resistance of the solder material 25 itself. on the other hand,
The semiconductor device of the comparative example uses a solder material of the same quality as that of the semiconductor device 40 of the present embodiment, but has a large thermal resistance variation. This is because the stress based on the mismatch in the coefficient of thermal expansion between the [mold resin 30 and the Al plate 1] is superimposed on the thermal stress due to the complete energization and acts on the solder material to promote its destruction. The semiconductor device 40 of the present embodiment and the semiconductor device of the comparative example were subjected to a high-temperature and high-humidity bias test (85 ° C., 85% RH,
(Between wiring 3 and Al plate 1) applied voltage: 500 V)
00h. As a result, the leakage current ([applied voltage 1
(200 V, room temperature) was about 0.1 μA, which was almost equal to the initial leak current value. On the other hand, in the case of the semiconductor device of the comparative example, [Wiring 3-Al plate 1
Short circuit). Thus, the semiconductor device 4 of the present embodiment is
0 and the comparative semiconductor device [Wiring 3-Al plate 1
The reason for the apparent difference in the dielectric strength between the [mold resin 30 and the Al plate 1] is that the interfacial bonding strength between the [mold resin 30 and the Al plate 1] is the same as described above. On the other hand, the comparative example semiconductor device was significantly introduced.

The above semiconductor device 40 constitutes a circuit in which four IGBT elements 21a and two diode elements 21b are connected in parallel as shown in FIG. This semiconductor device 40 is incorporated in an inverter circuit for controlling the rotation speed of the electric motor. When incorporated in the inverter circuit, the semiconductor device 40 is heated to 225 ° C.
And the external wiring were connected by soldering. After the heat treatment, the leakage current between the wirings 3 (interval: 2 mm) was measured. In the semiconductor device 40 of this embodiment, all of the ten samples were 0.1 μA or less (applied voltage: 12
00V) and good insulation was maintained. This is because the component mounting solder material 25 was not remelted in the above-described soldering process, and the outflow between the wirings 3 was suppressed.
On the other hand, in the comparative example semiconductor device manufactured simultaneously, six out of ten samples (Pb-60 wt% Sn solder material applied),
And 4 out of 10 samples (Sn-Sb-Pb based solder material applied, Pb concentration: 12.6 wt%) showed a high value of 100 mA or more (applied voltage: 1 V), and good insulation was obtained. Did not. This is based on the short circuit between the wirings 3 due to the outflow of the solder material.

[Embodiment 3] The semiconductor device 40 of the embodiment 3
A circuit board 10 (20) having a structure similar to that of FIG. 1 and selectively forming a copper wiring layer 3 (70 μm) on one main surface of an Al—SiC composite material plate 1 via an insulating resin layer 2 (80 μm). .
5 mm × 38 mm × 1.5 mm), a passive element including a power MOS FET element 21 as a semiconductor element substrate, a ceramic chip resistor 22, a chip capacitor 23, and a terminal 24 made of copper are composed of Sn-3.5 wt% Ag-. 3.5wt
% Pb is electrically and mechanically fixed by a solder material 25, and the semiconductor element substrate 21 is bonded by a metal wire 26, and these mounted components 21, 22, 23, 2
4, 25, 26 and the substrate 10 are transfer-molded with an epoxy resin 30 having a thermal expansion coefficient of 16 ppm / ° C. and hermetically sealed.

In this embodiment, the Al—SiC composite material plate 1 is obtained by impregnating a compacted SiC compact having a particle size of 10 to 400 μm with molten Al (SiC content: 75).
%). The physical properties of the composite plate 1 were as follows: density: 3.02 g / cm ³ , thermal conductivity: 185 W / m · K, thermal expansion coefficient: 6.0 ppm / ° C.
Young's modulus: 255 GPa.

The semiconductor device 40 of the present embodiment has a structure shown in FIG.
Is formed. This semiconductor device 40
Adopts resonance power control IC, withstand voltage 200V
, A compact, high-efficiency, low-noise resonant power supply, especially a resonant AC / D
It is suitable for a C converter power supply. This is (1)
Overcurrent and overvoltage protection function, (2) overheat protection function, (3)
This is based on the fact that a gate drive circuit, (4) a soft start function, and (4) two power MOS transistors with uniform characteristics are built in.

In the present embodiment, a semiconductor device which was transfer-molded with an epoxy resin having a thermal expansion coefficient other than 16 ppm / ° C. was also manufactured. FIG. 19 is a graph illustrating the amount of warpage of the integrated product of the mold resin and the circuit board. The amount of warp shows a large positive value as the coefficient of thermal expansion of the mold resin increases. The initial amount of warpage of the substrate 10 is 20 μm (dashed line in the figure). Also in the case of the structure of this embodiment, in order to prevent the interface internal stress from being introduced after the transfer molding, the warpage of the substrate 10 after the molding needs to be controlled within ± 10 μm of the initial value. From this viewpoint, the thermal expansion coefficient of the mold resin 30 is also 10 to 20 ppm when the Al-SiC composite material plate 1 of the present embodiment is applied.
/ ° C is desirable.

Further, when the semiconductor device is dropped from a height of 1.5 on a concrete floor, the semiconductor device 30 in which the coefficient of thermal expansion of the mold resin 30 is adjusted to 10 to 20 ppm / ° C. In the test, the rate of occurrence of destruction of the substrate 10 was 1 for every 20 samples. On the other hand, in the semiconductor device (comparative example) in which the coefficient of thermal expansion of the mold resin was other than 10 to 20 ppm / ° C., the breakdown rate of the substrate 10 was as high as 11 out of 20 samples. As described above, in the case of the comparative example semiconductor device, the substrate 10 was significantly destructed because the internal stress at the interface between the [substrate and the mold resin] was large and the impact force at the time of drop was superimposed on this. -Mold resin], because destruction (cracking) from the interface between them is likely to occur. On the other hand, the coefficient of thermal expansion of the mold resin is 10 to 20 pp
In the semiconductor device 30 adjusted to m / ° C., even if the impact force at the time of drop is superimposed, the substrate 10 is not broken even if the internal stress at the interface is small.

FIG. 20 shows the thermal fatigue rupture life of the soldered portion of the chip resistor according to the temperature cycle test. In the figure, the symbol 〇 indicates the case where the mold resin 30 is not provided, and the symbol □ indicates the case where the mold resin 30 is provided. When the linear damage rule is applied from the fitted straight line when the mold resin 30 is not provided, the broken line indicates that the mold resin 30 is provided (square mark, no break is observed at 6000 times even under the condition of a temperature difference of 205 deg). The life characteristics shown are obtained. When the rupture life of the semiconductor device 40 under actual operating conditions (temperature difference: 70 deg) is estimated from the broken line, it is estimated to be about 170,000 times or more. The reason why such a long rupture life was obtained in the present embodiment is that, in addition to (1) the solder material 25 itself having excellent thermal fatigue resistance, (2) the mold resin 30 and the circuit board 10 This is based on the fact that no internal stress is built into the integrated interface of, and no excessive stress acts on the soldered portion even when thermal stress of an external factor is superimposed.

In the semiconductor device 40 of the present example, the chip capacitor soldering portion, the terminal soldering portion, and the semiconductor substrate soldering portion exhibited a long rupture life similar to that of the first embodiment. These are also based on the same reason as described above.

Further, the semiconductor device 40 is composed of Pb-60 wt% S
Solder to printed circuit board with n solder (225 ° C)
Was done. In the semiconductor device 40 of the present embodiment, all of the circuit components 21, 22, 23, 24, 25, 26 inside the device are
The first endothermic peak intensity is as low as 0.3 mW / mg or less, and the second endothermic peak temperature is as high as about 226 ° C., Sn-3.5 wt.
% Ag-3.5 wt% Pb Since the connection is made with the solder material 25, the solder material 2 in the printed circuit board soldering process is used.
No remelting of 5 occurs. Therefore, the circuit constant in the apparatus does not change even after the printed circuit board is soldered.

On the other hand, Pb-60 wt% Sn solder material and Sn-Ag-Pb type solder material (Pb concentration: 15 wt%)
In the case of the comparative example semiconductor device in which the circuit components 21, 22, 23, 24, 25, and 26 are mounted on the circuit board 10,
In the printed circuit board soldering process at 25 ° C., the above-mentioned solder material was re-melted, and the circuit constant in the device fluctuated. Also,
In the case of the comparative example semiconductor device, the molten solder material flowed out to the nearby wiring.

When the leak current was measured between the wirings having an interval of 2 mm, the semiconductor device 40 of this example showed that all of the ten samples were as low as 0.1 μA or less (applied voltage: 200 V).
Good insulation was maintained. This is because the re-melting of the solder material 25 in the printed circuit board soldering process does not occur. On the other hand, in the case of the comparative example semiconductor device, the number of samples is 1
7 out of 0 (Pb-60wt% Sn solder applied) and 7 out of 10 samples (Sn-Ag-Pb based solder applied) showed high values of 100mA or more (applied voltage: 1V). No good insulation was obtained. This is based on the short circuit between the wirings 3 due to the outflow described above.

The present invention has been described with reference to the embodiments. However, the invention can be applied outside the scope of the above description.

In the present invention, the Al plate 1 is made of, for example, copper,
Iron, nickel, molybdenum, tungsten, brass, iron
It can be replaced with other metals such as a nickel alloy, an iron-nickel-cobalt alloy, a copper-invar-copper laminate composite metal, and a copper-molybdenum-copper laminate composite metal. You can enjoy the benefits. Also, Al-SiC composite material plate 1 is, for example, can replace Al matrix copper, a metal such as nickel, and, SiC particles AlN, can be replaced by Al ₂ O _3, a ceramic powder such as BN. Any combination and composition of these matrix metal and ceramic powder can be selected as needed. Even in such a case, in order to bring out the effects of the present invention, as the solder material 25, two or more kinds of metals selected from the group of Sn, Sb, Ag, Cu, Zn, In and Bi and Pb as main components. It is necessary to apply a transfer mold made of an alloy material having a thermal expansion coefficient of 10 to 20 ppm / ° C.

In the present invention, the copper wiring layer 3 is made of nickel,
A metal such as aluminum or silver can be substituted, and a laminate of these metals including copper can be substituted. In these cases, an arbitrary thickness can be selected according to the current capacity of the semiconductor device.

In the present invention, the mold resin 30 is made of SiO ₂ (fused silica, crystalline silica) or ZnO as a filler.
A phenol-curable epoxy resin to which a powder is added is used. In this case, the filler is added in an amount of 50 to 90%, but an arbitrary composition can be selected according to a desired coefficient of thermal expansion and a mold processing temperature. Even when a rubber-modified epoxy resin is used, its coefficient of thermal expansion is 10 to 20.
As long as it is selected in the range of ppm / ° C., the effects of the present invention can be enjoyed.

FIG. 21 is a sectional view of a semiconductor device illustrating a modification of the present invention. The semiconductor device 40 includes a semiconductor element substrate 21, passive elements 22, 2 on a circuit board 10 in which a metal wiring layer 3 is selectively formed on a main surface of a ceramic plate 1.
3, the terminals 24 are conductively and mechanically fixed by a solder material 25, and the semiconductor element base 21 is bonded by metal wires 26, and these mounted components 21, 22,
23, 24, 26 and the substrate 10 have a coefficient of thermal expansion of 10 to 20 pp
m / ° C., and hermetically sealed with a mold resin 30 selected from the group consisting of Sn, Sb, Ag, and C.
Pb is a main component containing two or more metals selected from the group consisting of u, Zn, In and Bi, and the Pb concentration is adjusted to 10 wt% or less. Even in such a configuration, the effects of the present invention can be enjoyed. The ceramic plate 1 is made of alumina, aluminum nitride, beryllia, silicon carbide or the like. The metal wiring layer 3 is made of Cu, Ag, Ag-Pd,
A thick film made of Ag-Pt, Au or the like is applicable. The semiconductor device 40 may be used by being housed in a package made of metal or the like. For example, the ceramic plate 1 may be joined (soldered, resin-bonded) to a package material.

[0067]

As described above, according to the present invention, there is provided a mold-type electronic component which is excellent in thermal fatigue resistance and airtightness of a soldered portion and can suppress remelting of a soldered portion in a subsequent heat process. Can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating a thermal fatigue resistance of a solder material.

FIG. 4 is a graph showing the amount of warpage of an integrated product of a mold resin and a circuit board.

FIG. 5 is a graph of a differential scanning calorimetric analysis curve of a Sn—Sb-based solder material and a Sn—Sb—Pb-based solder material.

FIG. 6 is a schematic sectional view of a component mounting section.

FIG. 7 is a graph showing the Pb concentration dependency of the endothermic peak intensity of the Sn—Sb—Pb-based solder material.

FIG. 8 is a graph showing the Pb concentration dependency of the endothermic peak temperature of the Sn—Sb—Pb-based solder material.

FIG. 9 is a block diagram of a semiconductor device according to one embodiment.

FIG. 10 is a graph showing a thermal fatigue rupture life of a soldered portion of a chip resistor.

FIG. 11 is a graph showing a thermal fatigue rupture life of a soldered portion of a chip capacitor.

FIG. 12 is a graph showing a change in thermal resistance of a MOS FET element mounting portion.

FIG. 13 is a graph showing thermal fatigue rupture characteristics of a terminal soldering portion.

FIG. 14 is a schematic sectional view of a component mounting portion before and after soldering.

FIG. 15 is a graph showing a Pb concentration in a solder layer after soldering.

FIG. 16: Composition of Pb-Sn plating and Pb concentration of 10 wt.
5 is a graph showing the thickness of the solder layer to be less than or equal to%.

FIG. 17 is a cross-sectional view illustrating a semiconductor device of one example.

FIG. 18 is a diagram illustrating a circuit of a semiconductor device according to an example.

FIG. 19 is a graph showing the amount of warpage of an integrated product of a mold resin and a circuit board.

FIG. 20 is a graph showing a thermal fatigue rupture life of a soldered portion of a chip resistor.

FIG. 21 is a cross-sectional view of a semiconductor device illustrating a modification of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Metal plate, 2 ... Insulating resin layer, 3 ... Metal wiring layer, 10 ...
Circuit board, 21: Semiconductor element base, 22: Chip resistor, 23: Chip capacitor, 24: Terminal, 25: Solder material (first alloy material), 26: Fine metal wire, 27, 27 '
... Interface, 30 ... Mold resin, 40 ... Semiconductor device, 50
... external circuit board, 51 ... second alloy material.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Iwamichi Jindai 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. 5-2-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Tsuneo Endo 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Semiconductor Corporation Semiconductor Division, Hitachi Ltd. (72) Inventor Ichiji Yamada 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd.

Claims (9)

[Claims] 1. A mounting component including at least one selected from the group consisting of a semiconductor element base, a passive element, and a terminal is fixed on a circuit board provided with metal wiring with an alloy material. In a semiconductor device covered with a mold resin, the mounted components are Sn, Sb, Ag,
Two or more metals selected from the group consisting of Cu, Zn, In, and Bi, and an alloy material containing Pb as a main component;
A mold-type electronic component, wherein the Pb concentration in the alloy material is adjusted to 10% by weight or less. 2. The molded electronic component according to claim 1, wherein the coefficient of thermal expansion of the molded resin is selected to be 10 to 20 ppm / ° C. 3. The circuit board according to claim 1, wherein the circuit board has metal wiring formed on one main surface of a metal plate via a resin insulating layer, or a metal plate is formed on at least one main surface of the ceramic plate. A molded electronic component having wiring formed thereon. 4. The method according to claim 3, wherein the metal plate is made of aluminum, copper, iron, nickel, molybdenum, tungsten, brass, iron-nickel alloy, iron-nickel-cobalt alloy,
Copper-invar-copper laminate composite metal, copper-molybdenum-
One kind of metal selected from the group of copper laminate composite metal,
Alternatively, a matrix composed of one kind of metal selected from the group consisting of aluminum, copper, and nickel is provided with SiC, AlN, A
a composite metal obtained by dispersing at least one type of ceramic particles selected from the group consisting of l ₂ O ₃ and BN, wherein the metal wiring is made of at least one type selected from the group consisting of copper, aluminum, nickel and silver A molded electronic component characterized by the above-mentioned. 5. The ceramic plate according to claim 3, wherein said ceramic plate is made of one type of ceramic selected from the group consisting of alumina, aluminum nitride, silicon carbide, and beryllia, and said ceramic plate has Cu, Ag-Pd, Ag-Pt, A mold-type electronic component provided with one kind of thick film wiring selected from the group consisting of Au and Ag. 6. A mold electronic component according to claim 1, wherein said mold resin is mainly composed of an epoxy resin containing an inorganic filler. 7. A mounting component including at least one selected from the group consisting of a semiconductor element substrate, a passive element, and a terminal is fixed on a circuit board provided with metal wiring with a first alloy material. In a semiconductor device in which the mounted component is covered with a mold resin, the mounted component may be Sn, S
At least two metals selected from the group consisting of b, Ag, Cu, Zn, In and Bi were fixed to an alloy material containing Pb as a main component, and the Pb concentration in the alloy material was adjusted to 10 wt% or less. An electronic device, wherein a molded electronic component is fixed to an external circuit board with a second alloy material. 8. The mold electronic component according to claim 16, wherein said second alloy material has a eutectic composition. 9. A mounting component including at least one selected from the group consisting of a semiconductor element base, a passive element, and a terminal is fixed on a circuit board provided with metal wiring with an alloy material. In a method of manufacturing an electronic component covered with a mold resin, a Pb—Sn alloy layer is provided on the mounted component, and Sn, Sb, Ag, Cu, Zn, In and B
The mounting component is fixed on the metal wiring by a brazing material made of two or more types of metals selected from the group of i, Sn, S
An alloy material comprising Pb and two or more metals selected from the group consisting of b, Ag, Cu, Zn, In and Bi is formed, and the Pb concentration in the alloy material is adjusted to 10 wt% or less. Manufacturing method of mold type electronic parts.