JP2000349437A - Multilayered wiring board and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered wiring substrate which has superior surface flatness suitable for flip-chip mounting of a semiconductor element and the method by which it can easily be manufactured. SOLUTION: This is a multilayered wiring board C formed by forming an insulating layer 3 containing thermosetting resin, a 2nd wiring circuit layer 4 formed on the top surface of the insulating layer 3, and a wiring layer B having a via hole conductor 9 electrically connecting the 1st wiring layer 2 and the 2nd wiring layer 4, on the top surface of a core substrate A formed by adhering and forming the 1st wiring circuit layer 2 on the top surface of an insulating substrate 1. The 2nd wiring circuit layer 4 is formed of metal foil in an inverse trapezoid shape and embedded in the top surface of the insulating layer 3 in level with the top surface of the insulating layer 3, and a metal plating layer 8 is formed on the internal wall of a via hole 7 formed by irradiation with laser light so that the via hole conductor 9 penetrates the insulating layer 3 and reaches the 1st wiring circuit layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board suitable for, for example, a multilayer wiring board and a package for accommodating a semiconductor device, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, electronic devices have been reduced in size.
In recent years, with the development of portable information terminals and the spread of so-called mobile computing in which a computer is carried and operated, there is a tendency that a smaller, thinner, and higher-definition multilayer wiring board is required.

[0003] Further, electronic devices that require high-speed operation, such as communication devices, have been widely used. The requirement for high-speed operation includes various requirements such as accurate switching of high-frequency signals. In order to cope with such electronic devices, a multilayer printed wiring board suitable for high-speed operation is required.

In order to perform high-speed operation, it is necessary to reduce the length of wiring and shorten the time required for transmitting an electric signal. In order to reduce the length of the wiring, there is a tendency for a small, thin, and high-definition multilayer wiring substrate in which the width of the wiring is reduced and the gap between the wirings is reduced.

In order to meet such a demand for high-density wiring, a manufacturing method called a build-up method is used. The basic structure of the build-up method is classified into two types in the JPCA standard: (1) base + build-up method and (2) all-layer build-up method.

Therefore, (1) a base + build-up manufacturing method will be described with reference to FIG. a) First, a wiring circuit layer 22 is formed on the surface of an insulating substrate 21 such as a double-sided copper-clad glass epoxy substrate.
And a core substrate a on which the through-hole conductor 23 and the like are formed. b) A photosensitive resin is applied to the surface of the core substrate a to form a photosensitive insulating layer 25. c) The via hole 2 is formed by exposing the photosensitive insulating layer 25 to a via hole pattern.
4 is formed. d) A plating layer 26 of copper or the like is applied to the entire surface of the photosensitive insulating layer 25 in which the via holes 24 are formed.
e) A photosensitive resist is applied to the plating layer 26, a circuit pattern is exposed and developed, a non-resist forming portion is etched to form a circuit, and the resist is removed to form a wiring circuit layer 27. Then, if necessary, b) above
To e) to form a multilayer.

[0007] (2) A method of manufacturing an all-layer build-up is disclosed in, for example, Japanese Patent No. 2587593, in which a via hole is formed in an insulating layer with a laser or the like, and the via hole is filled with a conductive paste. Electrically connecting the wiring circuit layer formed on the surface of the to form a wiring layer,
The wiring layer thus manufactured is repeatedly formed to form a multilayer.

[0008]

However, in recent years, the problem has been clarified with the spread of the build-up method.
A first problem is that the material properties of an organic resin constituting an insulating layer of a multilayer wiring layer (hereinafter, referred to as a build-up layer) formed by a build-up method are inferior. (1) In the base + build-up method, a photosensitive epoxy resin or the like is frequently used as an insulating layer. However, the epoxy resin originally has a low glass transition point and is made photosensitive, so that the water absorption rate increases and the temperature and humidity are high. There is a problem that the reliability is lowered, for example, the insulation property is lowered when left untreated.

The second problem is that the smoothness of the wiring board surface is poor. The surface of the core substrate has irregularities corresponding to the thickness of the wiring circuit layer formed of copper foil. Since the photosensitive resin used in the build-up method is liquid, unevenness on the surface of the core substrate is reflected even on the surface of the multilayer wiring layer that has been built up, and unevenness is also formed on the surface of the finished product. For this purpose, DC that directly connects a silicon chip such as a flip chip, which is expected to become the mainstream in the future, on the substrate surface
The A method cannot be applied to such a wiring substrate having an uneven surface.

[0010] A third problem is that peeling occurs at the interface between the core substrate and the insulating layer of the build-up layer in a temperature cycle test or a high-temperature high-humidity test. This is because the insulating layer of the build-up layer is bonded to a core substrate manufactured in advance, so that the chemical bonding is weak and the adhesion strength is insufficient.

Various solutions to the above problem have been proposed, and are described in Electronics Packaging Technology Magazine 1998, 1 (V
ol. 14 No. 1) and JP-A-51-31862.
No. 1 describes a build-up substrate having a smooth substrate surface. However, the chemical bonding between the core substrate and the insulating resin of the build-up layer has not been improved, and there has been a problem in reliability.

In particular, in recent years, the handling of high-frequency signals exceeding 1 GHz has increased, and the use of organic resins having a low dielectric constant and a low dielectric loss, such as polyphenylene ether resin (hereinafter, referred to as PPE resin), has been increasing. However, PPE
Organic resins having a low dielectric constant and a low dielectric loss, such as resins, are weak in adhesion due to their molecular structure and tend to peel off. Therefore, the problem of peeling is becoming more serious as the handling of high-frequency signals increases.

In the above (2) all-layer build-up method, the via-hole conductor is formed by filling the via-hole with a conductive paste, but the electric resistance of the conductive paste is larger than that of the plating layer. In addition, when the via diameter is reduced to 60 μm or less, there is a problem that the via resistance increases and the reliability decreases.

The present applicant has disclosed a method of manufacturing a multilayer wiring board capable of easily forming a fine wiring circuit layer in Japanese Patent Laid-Open No. Hei 10-279.
No. 59, and the like. In this method, a via hole is formed by laser or punching in an insulating layer made of a mixture of a prepreg or a thermosetting resin and a filler used for a normal printed wiring board, and a conductive paste is filled in the hole, and then the surface is filled. Then, a transfer sheet in which a wiring circuit layer made of copper foil is formed in advance is laminated and pressed on the surface of the insulating layer on which the via-hole conductor is formed, and the wiring circuit layer is transferred to the insulating layer to form one wiring layer. Then, the wiring layers produced in the same manner are aligned and laminated, and heated and pressed to cure the thermosetting resin, thereby obtaining a multilayer wiring board.

However, in this method, a connection between circuit layers is made by filling a conductive paste into the via hole in order to increase the degree of freedom in designing the via hole conductor and simplify the process. As in the above-described all-layer build-up method, it was difficult to reduce the via diameter to 60 μm or less.

On the other hand, in semiconductor devices, as the amount of information to be processed increases, the number of terminals for inputting and outputting information (signals) has dramatically increased. For this reason, the number of pads (I / O pads) formed on the silicon chip increases, and it becomes necessary to form many pads on the lower surface of the silicon chip. For this reason, the density of the I / O pads of the silicon chip increases,
When the distance between the pads became less than 200μm,
It is predicted that necessary wiring will not be drawn.

An object of the present invention is to solve the problems of the conventional build-up method as described above. Specifically, the present invention has excellent surface flatness and adhesion of a build-up layer, and has a fine structure. It is an object of the present invention to provide a multilayer wiring board in which simple circuits are formed at a high density, and a method for manufacturing a multilayer wiring board which can be easily manufactured.

[0018]

According to the present invention, there is provided a multilayer wiring board comprising: a core substrate having a first wiring circuit layer formed on the surface of an insulating substrate; an insulating layer containing a thermosetting resin; A wiring layer including a second wiring circuit layer formed of a metal foil on the surface of the insulating layer, and a via-hole conductor that electrically connects the first wiring circuit layer and the second wiring circuit layer. A multilayer wiring board formed, wherein the second wiring circuit layer is embedded in the surface of the insulating layer so as to have an inverted trapezoidal cross section and to be flush with the surface of the insulating layer. A metal plating layer is formed in a via hole formed so that the via hole conductor penetrates through the insulating layer and reaches the first wiring circuit layer.

It is preferable that the wiring substrate be formed by heat curing the core substrate and the multilayer wiring layer at one time, and that the via holes be formed by laser irradiation. It is preferable that the second wiring circuit layer is formed on the outermost surface of the multilayer wiring layer.

Further, according to the method for manufacturing a multilayer wiring board of the present invention, (a) a thermosetting resin is contained on the surface of a core substrate in which a first wiring circuit layer is formed on an insulating substrate surface. (B) depositing and forming a second wiring circuit layer made of a metal foil on the surface of the insulating layer, and removing the second wiring circuit layer.
Embedding in the surface of the edge layer ; and (c) the second wiring circuit.
A release film is applied to the surface of the insulating layer
After being attached, a step of heating and thermally curing the insulating layer,
(D) forming a via hole that penetrates through the insulating layer on which the second wiring circuit layer is formed by laser light irradiation and reaches the first wiring circuit layer; (e)
Forming a metal plating layer on the inner wall of the via hole, and electrically connecting the first wiring circuit layer and the second wiring circuit layer.

Further, it is desirable that the release film in the step (c) is a film containing ethylene fluoride. Further, in the step (d), after attaching a release film to the surface of the insulating layer, the laser light is applied to penetrate the release film and the insulating layer, and the first wiring circuit It is desirable to form a via hole that reaches the layer. Further, in the step (e), it is preferable to form the metal plating layer only in and around the via hole by using the release film as a plating resist, and then to peel off the release film. The release film is transparent or translucent, and the second wiring circuit layer has a mark capable of image-recognizing a via hole formation position by a laser beam, and the laser beam irradiation position is corrected by the mark. It is desirable to do.

According to the multilayer wiring board of the present invention, since the wiring circuit layer is embedded so as to be flush with the surface of the insulating layer, the surface of the multilayer wiring board is excellent in smoothness. Therefore, even when the semiconductor element is flip-chip mounted on the surface of the multilayer wiring board, the mounting reliability can be improved.

In addition, since the via-hole conductor connecting the wiring circuit layer on the surface and the wiring circuit layer inside is formed by forming a metal plating layer on the inner wall of the via hole formed through the insulating layer, the conductive paste , The resistance between the wiring circuit layers can be reduced as compared with the via hole conductor, and the reliability of the circuit can be improved.

According to the manufacturing method of the present invention, the via hole conductor for connecting the wiring circuit layers in the multilayer wiring layer is formed by laser processing and applying a metal plating layer to the inner wall of the hole. Does not need to have photosensitivity, has a high glass transition point as an insulating layer material,
Any insulating material having excellent material properties such as low water absorption can be selected.

In addition, since the via hole is formed by irradiating a laser beam, a via hole conductor having a diameter of 50 μm or less can be formed, and the density of the I / O pads of the silicon chip has increased, and the distance between the pads has become 200 μm or less. In such a case, necessary wiring can be formed. Further, since the via hole is processed after the wiring circuit layer is formed on the insulating layer surface, a complicated process such as a build-up method is not required, and the confirmation and correction of the via processing position can be easily and accurately performed during laser processing. Therefore, the positional accuracy of laser processing, which was about ± 20 μm in the past, can be improved to ± 5 μm, the precision of the substrate can be improved, and the wiring density can be improved. Further, since the portion where the metal plating layer is formed is only the inner wall of the via hole, the amount of harmful drugs such as cyan and formalin contained in the plating solution can be reduced.

When the wiring circuit layer is formed by plating, the step of removing the plating layer is complicated and the thickness of the plating layer remains as irregularities on the surface of the substrate. When the circuit layer is formed by transferring a wiring circuit layer made of metal foil, the wiring circuit layer can be embedded on the surface of the insulating layer so that the wiring circuit layer is formed on the surface of the insulating layer and is flush with the surface of the insulating layer. In addition, the adhesiveness between the wiring circuit layer and the insulating layer is high, and the smoothness of the surface of the multilayer wiring board can be improved.

Furthermore, in the case where the cross-sectional shape of the wiring circuit layer in the multilayer wiring layer is an inverted trapezoid, the decomposition gas generated by laser processing is more smoothly discharged than in the case of a general rectangular shape. And a via shape having excellent uniform plating properties can be obtained.

Furthermore, after laminating the core substrate and the multilayer wiring layer in an uncured or semi-cured state, and then thermally curing them together, a strong chemical bond is obtained, and a low dielectric material such as PPE resin is obtained. Even when an organic resin having a low dielectric loss and a low dielectric loss is used, no delamination occurs between layers in the reliability evaluation.

Since the releasable resin film attached in the step of thermally curing the insulating layer is used as a plating resist,
Even if continuous plating is performed at a high temperature of 90 ° C. for more than 10 hours, the release resin film used as a plating resist does not deteriorate or peel off, so that thick plating by electroless plating is possible.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a multilayer wiring board according to the present invention will be described with reference to the drawings. FIG. 1 is a process chart for explaining an example of a method for manufacturing a multilayer wiring board according to the present invention.

As shown in FIG. 1A, first, a core substrate A having a first wiring circuit layer 2 formed on a surface of an insulating substrate 1 is formed.
A soft insulating layer 3 containing a thermosetting resin is laminated on the surface of the substrate.

As the core substrate A used here, any substrate can be used as long as the wiring circuit layer 2 is formed on the surface of the insulating substrate 1. For example, an insulating sheet is processed with a via hole using a laser, a conductive circuit is filled in the via hole, and a wiring circuit layer is formed on the sheet surface. A well-known printed wiring board such as a double-sided wiring board in which a via hole is formed with a drill and copper plating is formed on the inner wall thereof to connect a reliable wiring circuit layer, or an IVH board formed by laminating a plurality of layers, can be used. In particular, the core substrate A
It is desirable to have an insulating layer containing a fibrous body inside.

The first wiring circuit layer 2 is formed, for example, by adhering a metal foil to the entire surface of the insulating substrate 1 and then forming a photoresist, pattern exposure, development and removal of the resist according to a photoresist method. can do.

The insulating layer 3 formed on the surface of the core substrate A
Is desirably made of a thermosetting resin containing no fibrous body or an insulating composite material composed of a thermosetting resin and an inorganic filler.

If the insulating layer 3 contains a fibrous body, the via hole diameter tends to vary when the via hole is formed due to the non-uniformity of the glass woven fabric itself. In this case, when stored for a long time in a high humidity, adverse effects such as migration of water due to diffusion of water at the interface between the glass fiber and the organic resin occur.

The thickness of the insulating layer 3 is desirably 10 μm or more, particularly 40 μm or more, in order to sufficiently exhibit the above-mentioned effects. If the thickness is less than 10 μm,
When the insulating layer 3 is the outermost surface layer, it is difficult to sufficiently suppress the diffusion of the moisture in the outside air into the inside by the insulating layer 3, and migration easily occurs between the insulating layers.

The thermosetting resin in the insulating layer 3 includes
Resins such as PPE (polyphenylene ether), BT resin (bismaleimide triazine), epoxy resin, polyimide resin, fluorine resin, phenol resin, and polyamide bismaleimide are preferable. It is desirable that the thermal expansion characteristics of the core substrate A and the insulating substrate 1 be approximated by mixing an inorganic filler into the insulating layer 3.

As the inorganic filler used at this time, SiO ₂ , Al ₂ O ₃ , AlN and the like are suitable, and the shape of the filler is substantially spherical having an average particle diameter of 20 μm or less, particularly 10 μm or less, and optimally 7 μm or less. Shaped powder is used. The inorganic filler is mixed in a volume ratio of organic resin: inorganic filler of 15:85 to 95: 5.

The uncured insulating layer 3 is sufficiently mixed with a thermosetting organic resin or a composition such as a thermosetting organic resin and an inorganic filler by means of a kneader or a three-roll mill. It is manufactured by molding into a sheet by a method, an extrusion method, an injection method, a doctor blade method or the like. The softness means an uncured or semi-cured state, and the semi-cured state may be heated to a temperature slightly lower than a temperature sufficient for completely curing the thermosetting resin.

Next, as shown in FIGS. 1 (b ₁ ) to ₁ (b ₃ ), a second wiring circuit layer 4 made of metal foil is adhered to the surface of the soft insulating layer 3 and the second wiring circuit layer 4 is formed. Wiring circuit layer 4
Is embedded in the surface of the soft insulating layer 3.

The second wiring circuit layer 4 is formed, for example, by bonding a metal foil to the entire surface of the insulating layer 3 and forming a mirror image of the second wiring circuit layer 4 'through a known photoresist method. After that, the second wiring circuit layer 4 ′ can be formed by burying the surface of the insulating layer 3 by applying pressure to the second wiring circuit layer 4 ′. According to the present invention, the second wiring circuit layer 4 is formed by the transfer method. This is advantageous in that the formation and embedding of the second wiring circuit layer 4 on the surface of the insulating layer 3 can be performed at the same time, and the process of forming the via-hole conductor thereafter can be simplified.

Accordingly, formation of the wiring circuit layer 4 by the transfer method
Will be described below. First, an appropriate resin fill
After bonding the metal foil to the surface of the
Mirror image pattern of second wiring circuit layer by resist method etc.
1 '(FIG. 1 (b) ₁)).

Then, the resin film 5 having the pattern 4 ′ of the second wiring circuit layer in a mirror image is laminated on the surface of the soft insulating layer 3 and a pressure of 3 kg / cm ² or more is applied. By peeling (FIG. 1B ₂ ), the second wiring circuit layer 4 can be transferred to the surface of the insulating layer 3 and the second wiring circuit layer 4 can be embedded in the surface of the insulating layer. . In the above description, (a) after the step of forming the insulating layer 3 on the core substrate 1, (b) the insulating layer 3
Although the case of performing the step of transferring the second wiring circuit layer 4 to the surface has been described, the steps (a) and (b)
The second wiring circuit layer 4 may be formed at the same time, or the (a) step may be performed after the (b) step, that is, after the second wiring circuit layer 4 is transferred and embedded on the surface of the insulating layer 3.
May be formed on the surface of the core substrate 1.

According to the present invention, it is important that the cross-sectional shape of the second wiring circuit layer 4 is an inverted trapezoid. As shown in FIG. 2B, in the conventional laser processing on the substrate, when the decomposition gas generated by the laser is released from the via hole, the decomposition gas convects to the step formed at the end of the wiring circuit layer 4. As a result, the interface between the wiring circuit layer 4 and the insulating layer 3 was covered. When this cut-out part is formed, not only does the plating liquid stay and prevent plating when the plating layer is applied to the inner wall of the through hole, but also the remaining plating liquid causes defects such as reduced insulation and discoloration of the substrate. Becomes

On the other hand, according to the present invention, FIG.
When the cross-sectional shape of the wiring circuit layer 4 is an inverted trapezoid as shown in FIG. 7, a step is hardly formed at the end of the wiring circuit layer 4 and the decomposition gas is smoothly discharged from the via hole, so that the wiring circuit layer 4 is insulated. The interface with layer 3 is not excreted,
Uniform plating can be performed. The effect is recognized when the angle θ on the bottom side of the trapezoid of the cross section in the wiring circuit layer 4 is 85 °, and the effect becomes clearer when the angle is 75 °. And 30
°, the emission of cracked gas becomes worse, so the angle θ is 3
0 ° to 85 °, preferably 45 ° to 75 °. In addition, as shown by the dotted line in FIG. 2A, if the trapezoid has a shape in which the hypotenuse is recessed by 5% or more of the length of the hypotenuse inside the trapezoid, the discharge performance of the decomposition gas is further improved, and the plating failure is reduced. It is completely gone.

After forming the second wiring circuit layer 4 as described above, it is desirable that the insulating layer 3 is completely subjected to a thermosetting treatment. This is because when the insulating layer 3 is uncured or semi-cured, if a thermosetting treatment is performed after the formation of a via hole, which will be described later, the diameter of the via hole changes or the via hole formation position shifts due to shrinkage during thermosetting. In addition, there is a problem that the accuracy is reduced, and in the plating process, the plating solution penetrates into the uncured or semi-cured insulating layer 3, and the wiring circuit layer is short-circuited or disconnected due to acid. This is because it may occur.

In heat curing, as shown in FIG. 1 (b ₃ ), a transparent release film 6 such as ETFE (tetrafluoroethylene-ethylene copolymer) is adhered to the surface of the insulating layer 3. This can be performed by hot pressing at a temperature sufficient to cure the thermosetting resin in the insulating layer 3.

Further, by using an uncured or semi-cured core substrate A and simultaneously performing thermal curing of the insulating layer 3, the insulating layer 3 and the core substrate 1 are chemically and strongly adhered. Even when a resin having a low dielectric constant and a low dielectric loss, such as a PPE resin, in which adhesion between resins is weak due to their molecular structure and peeling is likely to occur, no interface peeling occurs.

After the completion of the thermosetting treatment, the release film 6 is usually peeled off. However, in the present invention, since the release film 6 can be used as a resist at the time of a plating process described later, the release film 6 is removed. It is desirable that the conductive film 6 be peeled off after the plating process.

Further, the release film 6 preferably contains ethylene fluoride. In the case of the present invention, unlike the conventional method of manufacturing a multilayer wiring board, the release film directly adheres not only to the copper foil but also to the insulating resin. Further, a resin film containing ethylene fluoride exhibits excellent performance as a material that does not cause peeling or deterioration even when immersed in an electroless plating solution containing formalin for a long time at high temperature and strong alkali. Examples of the resin containing ethylene fluoride include PTFE (tetrafluoroethylene resin), PFA (ethylene tetrafluoride / perfluoroalkoxyethylene copolymer resin), FEP (ethylene tetrafluoride / hexafluoropropylene copolymer resin) ETFE ( (Tetrafluoroethylene / ethylene copolymer resin).

The peel strength from the cured substrate is increased in the above listed order, so that peeling during the manufacturing process does not occur and the peeling after the substrate is cured is adjusted according to the process conditions. Can be selected. Further, the resin film containing ethylene fluoride is not limited to the above, and any resin film containing ethylene fluoride may be used in addition to the above.

Next, via holes 7 are formed in the insulating layer 3 by laser light irradiation. The via hole 7 is formed so as to penetrate the release film 6 and the insulating layer 3 and reach the first wiring circuit layer 2 as shown in FIG.

For forming the via hole 7, laser processing using carbon dioxide gas or the like is preferable. Fig. 1 Laser beam
As shown in (c), a part of the second wiring circuit layer 4 on the surface of the insulating layer 3 is touched and penetrated through the insulating layer 3 to form the first wiring circuit layer 2.
Stop at the surface of. Since the first wiring circuit layer 2 is formed of a metal such as copper, the metal is harder to be laser-processed than the insulating layer 3, so that an appropriate beam intensity can be selected relatively easily.

In particular, when the thermosetting treatment is performed before the formation of the via hole, the position of the second wiring circuit layer 4 may be shifted because the insulating layer 3 shrinks by about 0.1%. Therefore, it is necessary to correct this shrinkage when processing a via hole with a laser. For this reason, a mark is formed on the second wiring circuit layer 4 so that the via hole formation position can be image-recognized by the laser beam so that the via hole formation position of the second wiring circuit layer 4 is marked by a pattern and can be determined. Is desirable.

Even when the shrinkage ratio is corrected by the above operation, the laser generally has a variation in the processing position of about ± 20 μm. Therefore, the second wiring circuit layer 4
In order to make a reliable connection between the via wiring conductor and the via hole conductor, it is desirable to form a via-hole conductor forming portion in the second wiring circuit layer 4 widely. Specifically, when the laser beam diameter is 40 μm, as shown in FIG. 3, (a) an O-shaped mark having a 20 μm gap in the center, (b) a U-shaped mark, and (c) a U-shaped mark It is desirable to irradiate a laser beam having a diameter indicated by a dotted line beforehand. As a result, even when the position of the laser beam varies, electrical connection of the via is ensured. (B)
The U-shaped mark and (c) U-shaped mark tend to have a wide opening after laser processing, and the plating solution circulates from this portion, so that the deposition rate of plating is increased and plating of a film thickness is easy. There is a feature that can be formed.

However, when the via diameter is 100 μm or more, it is sufficiently large with respect to the variation in beam position (± 20 μm), so that it is not necessary to form such a special pattern. Via processing may be performed on any of the wirings.

Next, as shown in FIG. 1D, a metal plating layer 8 is formed on the inner wall of the via hole 7 formed as described above.

As a method for forming the metal plating layer 8 on the inner wall of the via hole 7, any method such as an electrolytic plating method or an electroless plating method can be adopted, but the electroless plating method is particularly easy.

In the case of the electroless plating method, the via holes 7
Is immersed in the catalyst solution, the catalyst is applied to the surface of the release film 6 and the inner wall of the via hole 7. After that, when the release film 6 is removed, the catalyst is applied only to the inner wall of the via hole 7. Therefore, when this substrate is immersed in the electroless plating solution, the metal plating layer 8 is formed only on the inner wall of the via hole 7 coated with the catalyst.
Is formed, and the via-hole conductor 9 can be formed.

When the metal plating layer 8 is formed by the electroless plating method, the metal plating layer 8 may be partially formed around the via-hole conductor 9 of the second wiring circuit layer 4. In this case, by adjusting the thickness of the plating layer 8, the influence on the flatness of the substrate surface can be prevented, and when flip-chip mounting is performed, the mounting on the second wiring circuit layer 4 is performed. Has little effect.

On the other hand, when employing the electrolytic plating method,
The substrate on which the via hole 7 is formed is immersed in a catalyst solution,
After applying the catalyst to the surface of the release film 6 and the inner wall of the via hole 7, the surface of the release film 6 and the via hole 7 are coated.
A thin metal plating layer is deposited on the inner wall by electroless plating, and a thick metal plating layer is formed by electrolytic plating. After that, apply photoresist on the whole surface, expose,
After the development, the metal plating layer other than the via hole is removed by etching, the release film 6 is removed, and the insulating layer 3 is removed.
In contrast, via-hole conductor 9 in which metal plating layer 8 is applied to the inner wall of via hole 7 can be formed. Here, the metal plating layer 8 is desirably Cu, Ni, Au, or the like.

As described above, the surface of the core substrate A on which the first wiring circuit layer 2 is formed on the surface of the insulating substrate 1
A wiring layer B in which a second wiring circuit layer 4 is formed is laminated on the surface of the insulating layer 3 of the first layer, and the first wiring circuit layer 2 and the second wiring circuit layer 4 A multilayer wiring board C electrically connected by the via-hole conductor 9 having the plating layer 8 formed thereon can be manufactured.

According to the multilayer wiring board of the present invention, the second wiring circuit layer 4 is suitable for flip chip mounting of a semiconductor element or the like such as flatness of the surface and reduction in the diameter of the via hole conductor. It is desirable that it is formed on the outermost surface of the multilayer wiring board C.

In the example shown in FIG. 1, a core substrate A having a single wiring circuit layer 2 formed on the surface of an insulating substrate 1 is used. However, the present invention is not limited to this. As shown in FIG. 4, the core substrate A is a multi-layer wiring substrate in which a plurality of wiring circuit layers 11 and a plurality of via-hole conductors 12 formed by filling a conductive paste are formed inside an insulating substrate 10. The wiring circuit layer formed on the outermost surface of the core substrate A was positioned as the first wiring circuit layer 2, and the second wiring circuit layer 4 was formed on the surface of the insulating layer 3 on the surface thereof. A multilayer in which a wiring layer B is formed by lamination and the first wiring circuit layer 2 and the second wiring circuit layer 4 are electrically connected by a via-hole conductor 9 in which a metal plating layer 8 is formed on the inner wall of the via hole 7. Wiring board can be obtained

The wiring layer B formed on the surface of the core substrate A includes one insulating layer 3 and one second wiring circuit layer 4.
In addition, as shown in FIG. 5, a plurality of insulating layers 3 and second wiring circuit layers 4 may be formed.

Further, in some cases, a through-hole is formed in the multilayer wiring board manufactured as described above using a microdrill or the like, and a metal plating layer is formed in the hole. A circuit can also be formed by electrically connecting the wiring layers and the internal wiring layers.

[0067]

Example 1 A polyphenylene ether resin (PPE resin) -based prepreg was prepared as a core substrate. CO _{2 is} added to this prepreg
Via hole processing was performed using a laser, and then the via hole portion was filled with a conductive paste. Further, a wiring circuit layer formed by etching a copper foil on the surface of the resin film in advance was transferred to the prepreg. Then, three layers of this prepreg were laminated and thermally cured to produce a core substrate.

A PPE resin was used for the insulating layer, spherical silica was used as the inorganic filler, and a composition in which the volume ratio of the PPE resin: the inorganic filler was 50:50 was used.
m, a semi-cured insulating layer was prepared and bonded to both surfaces of the core substrate.

On the other hand, the copper foil having a thickness of 12 μm
A wiring circuit layer for the front surface and a wiring circuit layer for the back surface were formed on a copper foil of a resin film made of ET by a photoresist method.

Next, the above resin film was positioned and laminated on the insulating layers adhered to both surfaces of the core substrate, and heated and pressed at 120 ° C. and 30 kg / cm ² to peel off the resin film. As a result, it was confirmed that the wiring circuit layer was transferred to the surface of the insulating layer, that the wiring circuit layer was buried in the surface of the insulating layer, and that the surface was formed on the same plane.

Thereafter, a fluororesin-based transparent release film is adhered to the surface of the insulating layer, and then heated at 200 ° C. for 1 hour while applying a pressure of 20 kgf / cm ² using a vacuum press device. And the core substrate was completely cured.

Then, with the release film attached,
Using a carbon dioxide laser, a via hole having a diameter of 50 μm was formed at a predetermined position on the surface of the insulating layer in contact with the wiring circuit layer.

Next, a metal plating layer made of copper was formed on the inner wall of the via hole. As the metal plating method, the following two methods 1) and 2) were employed.

1) The substrate on which the via hole was formed was immersed in an aqueous palladium catalyst solution to apply a catalyst to the surface of the release film and the inner wall of the via hole, and then electrolessly applied to the surface of the release film and the inner wall of the via hole. Copper plating was deposited to a thickness of 0.5 μm by a plating method, and copper was further deposited to a thickness of 12 μm by electrolytic plating. After that, a photoresist is applied to the entire surface, exposed and developed, copper in portions other than the via holes is etched away, the release film is removed, and a copper plating layer is applied to the inner wall of the via hole with respect to the insulating layer. A conductor was formed.

2) The substrate having the via hole formed thereon is tin-
After the catalyst was applied to the surface of the release film and the inner wall of the via hole by dipping in a catalyst solution of an aqueous palladium solution, the catalyst on the surface of the release film was removed. And, this substrate is made of copper sulfate, formalin, sodium hydroxide, chelating agent,
It was immersed in an electroless plating solution at 70 ° C. made of an additive for 24 hours, and copper was deposited and deposited only on the inner wall of the via hole at a thickness of 25 μm.

After buffing the raised portion of the plating, the release film is peeled off and the filled via (f) is generally removed.
A via-hole conductor was formed by filling the inside of the hole with copper plating called “illed-via).

Further, the above-described formation of the insulating layer, the formation of the wiring circuit layer, the formation of the via hole, and the formation of the metal plating layer are repeatedly performed, so that a total of six wiring circuit layers having three wiring circuit layers on both surfaces of the core substrate are provided. A multilayer wiring board was formed. The plating treatment was performed by the above-mentioned 1) electrolytic plating method to obtain a multilayer wiring board X, and the above-mentioned 2) electroless plating method to obtain a multilayer wiring board Y. Example 2 Polyphenylene ether (PPE resin) as a core substrate
A system prepreg was prepared. The prepreg was processed with a via hole using a CO ₂ laser, and the via hole was filled with a conductive paste. Further, a wiring circuit layer formed by etching a copper foil on the surface of the resin film in advance was transferred to the prepreg. Then, three layers of this prepreg were temporarily laminated to produce an uncured core substrate.

A PPE resin is used for the insulating layer, spherical silica is used as the inorganic filler, and a composition in which the volume ratio of the PPE resin: the inorganic filler is 55:45 is used.
m, a semi-cured insulating layer was prepared and bonded to both surfaces of the core substrate. Thereafter, a sample was prepared in the same manner as in the above example. Comparative Example A multilayer wiring layer was formed on the surface of a core substrate made of a normal printed wiring board by a build-up method according to the following method. First, various copper foils with an epoxy resin coated with a photosensitive epoxy resin were adhered to the surface of the core substrate with a hot roll, and then exposed and developed to form via holes. And
After forming a via-hole conductor by applying 20 μm copper plating to the entire surface by an electroless plating method, a dry film resist was pasted again on the entire surface, exposed and developed, and unnecessary portions were removed by etching with a ferric chloride solution. This series of steps was repeated to form a multilayer wiring board having a total of six wiring circuit layers each having three wiring circuit layers on both surfaces of the core substrate. (Evaluation) The undulation of the surface of the multilayer wiring board on which the multilayer wiring layer was formed by any of the above methods was measured by a stylus type surface roughness meter, and the flatness of the substrate surface was measured. Further, the substrate was heated at -65 ° C x 30 minutes and 125 ° C x 3
After the temperature cycle of 0 minutes was repeated 500 times, the cross section of the core substrate and the multilayer wiring layer was observed, and the connection state between the core substrate and the multilayer wiring layer was observed. In addition, the initial conduction resistance of the wiring was measured, and the resistance after the temperature cycle was measured, and the rate of change was calculated.

As a result, the flatness was improved in the first and second embodiments.
In each case, the multilayer wiring board X was as good as 7 μm and the multilayer wiring board Y was as good as 9 μm, whereas the multilayer wiring board of the comparative example by the build-up method had uneven thickness of the copper plating layer and flatness. Was as large as 35 μm, which was unsuitable for flip chip mounting. The initial conduction resistance of each substrate was as good as 3 × 10 ⁻⁸ Ω. The change in resistance after the heat cycle test was determined in Examples 1 and 2 of the present invention.
2% or less, and the substrate of the comparative example was as large as 4%.

Further, the sample after the heat cycle test was cut, the cross section was polished, and the cross section was observed. As a result, peeling was observed at the interface between the core substrate and the insulating layer of the build-up layer in all the substrates of the comparative examples. In the substrate of the present invention, slight peeling was observed in one of the ten substrates of Example 1. No peeling was observed on the substrate of Example 2.

[0081]

As described in detail above, according to the present invention,
It is possible to obtain a multilayer wiring board which is excellent in flatness of the substrate surface and at the same time lowers the resistance of the via-hole conductor, and is suitable for flip-chip mounting of a semiconductor element.

Further, according to the manufacturing method of the present invention, a multilayer wiring layer can be formed by a very simple process as compared with a conventional build-up method and the like, and a via hole for connecting between wiring circuit layers is formed by a laser. By forming it by processing and plating on the inner wall of the hole, it is not necessary to impart photosensitivity to the insulating layer, and it is possible to select any insulating material with high glass transition point and excellent material properties such as low water absorption. Also, a via-hole conductor having a small hole diameter can be easily formed.

[Brief description of the drawings]

FIG. 1 is a process diagram for explaining an example of a method for manufacturing a multilayer wiring board of the present invention.

FIGS. 2A and 2B are schematic diagrams for explaining a structure when a via hole is formed by a laser beam in a multilayer wiring layer of a multilayer wiring board of the present invention, wherein FIG. 2A shows a product of the present invention, and FIG.

FIG. 3 is a pattern diagram of a second wiring circuit layer in the multilayer wiring board of the present invention.

FIG. 4 is a schematic sectional view for explaining another example of the multilayer wiring board of the present invention.

FIG. 5 is a schematic sectional view for explaining still another example of the multilayer wiring board of the present invention.

FIG. 6 is a process chart for explaining a conventional base + build-up method.

[Explanation of symbols]

 Reference Signs List A core substrate B wiring layer C multilayer wiring board 1 insulating substrate 2 first wiring circuit layer 3 insulating layer 4 second wiring circuit layer 5 resin film 6 release film 7 via hole 8 metal plating layer 9 via hole conductor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 3/18 H05K 3/18 D 3/20 3/20 A // B23K 101: 42

Claims (9)

[Claims] An insulating layer containing a thermosetting resin is formed on a surface of a core substrate having a first wiring circuit layer adhered to the surface of the insulating substrate, and a metal foil is formed on the surface of the insulating layer. A second wiring circuit layer, the first wiring circuit layer, and the second wiring circuit layer;
A multilayer wiring board formed with a multilayer wiring layer having a via hole conductor for electrically connecting the wiring circuit layer to the second wiring circuit layer, wherein the second wiring circuit layer has an inverted trapezoidal cross section,
In a via hole formed so as to be buried in the surface of the insulating layer so as to be flush with the surface of the insulating layer and formed so that the via hole conductor penetrates the insulating layer and reaches the first wiring circuit layer. A multilayer wiring board characterized by forming a metal plating layer on the wiring board. 2. The semiconductor device according to claim 1, wherein said core substrate and said multilayer wiring layer are formed by thermal curing at one time.
Multilayer wiring board. 3. The multilayer wiring board according to claim 1, wherein said via hole is formed by laser irradiation. 4. The multilayer wiring board according to claim 1, wherein said second wiring circuit layer is formed on the outermost surface of said multilayer wiring layer. 5. A step of forming a soft insulating layer containing a thermosetting resin on a surface of a core substrate in which a first wiring circuit layer is formed on the surface of an insulating substrate. A) forming a second wiring circuit layer made of a metal foil on the surface of the insulating layer, and embedding the second wiring circuit layer on the surface of the insulating layer; Affixing a release film to the surface of the insulating layer on which the wiring circuit layer is formed, and then heating to thermally cure the insulating layer; and (d) irradiating the second layer with laser light. Wherein the wiring circuit layer penetrates the insulating layer formed and adhered,
Forming a via hole reaching the first wiring circuit layer; and (e) forming a metal plating layer on an inner wall of the via hole and electrically connecting the first wiring circuit layer and the second wiring circuit layer. A method of manufacturing a multilayer wiring board, comprising the steps of: 6. The method according to claim 5, wherein the release film in the step (c) is a film containing ethylene fluoride. 7. In the step (d), after attaching a release film to the surface of the insulating layer, the laser light is applied to penetrate the release film and the insulating layer, and 6. The method according to claim 5, wherein a via hole reaching the wiring circuit layer is formed. 8. In the step (e), a metal plating layer is formed only in and around the via hole by using the release film as a plating resist, and then the release film is peeled off. The method for manufacturing a multilayer wiring board according to claim 5, wherein 9. The release film is transparent or translucent, and the second wiring circuit layer has a mark capable of recognizing an image of a via-hole formed by a laser beam, and the mark is used for the laser beam. 9. The method for manufacturing a multilayer wiring board according to claim 5, wherein the irradiation position is corrected.