JP2000323493A - Wafer for semiconductor devices - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wafer for semiconductor devices wherein the life of a heterobipolar transistor can be improved by blocking defects appearing in a collector contact layer fromn propagating to upper layers than this layer. SOLUTION: As for a wafer for semiconductor devices which has an n-type conductivity collector contact layer 2, an n-type conductivity collector layer 3, a p-type conductivity GaAs crystal or InGaAs crystal or AlGaAs crystal base layer 4, an n-type conductivity AlGaAs crystal or InGaP crystal emitter layer 5 forming a heterojunction with the base layer 4, and an n-type conductivity emitter contact layer 6 on a GaAs substrate 1; an In planar doped layer 10 is formed between the collector contact layer 2 and the collector layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device wafer, and more particularly to a semiconductor device wafer capable of improving the life of a hetero bipolar transistor.

[0002]

2. Description of the Related Art Conventionally, in a hetero-bipolar transistor (HBT), the life of an element is improved by focusing on an emitter layer and a base layer constituting the HBT and improving crystallinity and an interface between them. Attempts have been made to do so.
Therefore, the relationship between the crystallinity of the collector layer and the collector contact layer below the base layer and the reliability of the device has not been well studied.

[0003] The collector contact layer is used to form a contact with a metal electrode for drawing out a wiring and to form a wiring up to the electrode pad as the name implies, and the wiring is further miniaturized. is there.

However, it has recently been found that a collector contact layer doped with a high concentration of n-type impurities affects the current amplification factor β, which is one of the important characteristics of the HBT, and deteriorates β. Was.

That is, an increase in the contact resistance and external resistance of the wiring formed in the collector contact layer deteriorates the device characteristics. Therefore, it is required to use a sufficiently low resistance layer for the collector contact layer.

For this reason, a collector contact layer which is doped with an n-type impurity at a high concentration and has a low resistance is used. Generally, an n-type impurity doped to about 5 × 10 ¹⁸ cm ⁻³ is used.

[0007]

However, in recent years,
The impurity concentration of the collector contact layer is 3 × 10 ¹⁸ cm ⁻³
It has been found that the current amplification factor β is reduced when the value exceeds.

This is because, when the collector contact layer is doped with a high concentration of n-type impurity, the n-type impurity penetrates into the antisite to cause a crystal defect, and the defect propagates to the base layer and the emitter layer, where the defect is propagated. A model is conceivable in which the current amplification factor β is reduced by increasing the recombination current.

That is, it is known that there is a correlation between the current amplification factor β and the lifetime of the device, and it is known that the higher the β, the longer the lifetime of the device. Doping with a high concentration of impurities reduces the lifetime of the device. I was

It is an object of the present invention to suppress the generation of defects in the collector contact layer or to prevent the defects generated in the layer from propagating to a layer above the collector contact layer. It is an object of the present invention to provide a semiconductor device wafer which can improve the performance.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a gallium arsenide substrate having a collector contact layer and a collector layer exhibiting n-type conduction, and a gallium exhibiting p-type conduction. A base layer made of arsenic crystal or indium gallium arsenide crystal or aluminum gallium arsenide crystal; an emitter layer made of aluminum gallium arsenide crystal or indium gallium phosphide crystal heterojunctioned to the base layer and exhibiting n-type conduction; A semiconductor device wafer having an emitter contact layer exhibiting the above-mentioned conduction, wherein an indium planar doped layer is formed between the collector contact layer and the collector layer.

According to a second aspect of the present invention, an indium arsenide layer is formed in place of the indium planar doped layer.

According to a third aspect of the present invention, the indium sheet concentration of the indium planar doped layer or the indium arsenide layer is at least 1 × 10 ¹¹ cm ⁻² or more.

According to a fourth aspect of the present invention, the indium arsenide layer has a thickness of 0.5 to 3 nm.

According to a fifth aspect of the present invention, each of the layers is formed by MOVPE.
Grown by the MBE method or the MBE method.

That is, the gist of the present invention is to solve the above-mentioned problem by providing In between the collector contact layer and the collector layer.
Is to prevent the defects generated in the collector contact layer from propagating into the epitaxial layer grown thereon.

According to the above configuration, the In or InAs planar dope layer prevents defects generated in the collector contact layer from propagating into the epitaxial layer grown thereon, thereby improving the current amplification factor β suppressed by the defects. As a result, the life of the device is greatly improved.

[0018]

Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic view showing the structure of an HBT epi-wafer according to the present invention.

As shown in FIG. 1, the HBT epi-wafer is
S. N ⁺ GaAs on an I (semi-insulating) GaAs substrate 1
Layer (collector contact layer) 2, n ^- GaAs layer (collector layer) 3, p ⁺ GaAs layer (base layer) 4, nAl _x
Ga _1-x As layer (emitter layer) 5, nAl _x Ga _1-x A
s graded layer (emitter contact layer) 6, n ⁺ G
aAs layer _{^{7, n + In y Ga 1}} -y As is graded layer 8 and n ⁺ In _y Ga _{1- y} As layer 9, are sequentially stacked, indium at the interface of the collector contact layer 2 and the collector layer 3 ( It has a structure in which an indium planar doped layer 10 in which In) is planar-doped is formed.

Each of these layers will be described in detail. I
The GaAs substrate 1 has a thickness of 600 μm.

N ⁺ GaAs layer (collector contact layer)
No. 2 has a thickness of 500 nm and a concentration of 5 × 10 ¹⁸ cm ⁻³ and is formed by doping with Si.

[0023] ⁿ - GaAs layer (collector layer) 3 having a thickness of 500 nm, are formed by Si doping concentration is 2 × 10 ¹⁶ cm ^-3.

The p ⁺ GaAs layer (base layer) 4 has a thickness of 70 nm and a concentration of 4 × 10 ¹⁹ cm ^-3 and is C-doped.

NAl _x Ga _{1 -x} As layer (emitter layer) 5
Has a thickness of 100 nm, a mixed crystal ratio of x = 0.3,
It is formed at a concentration of 5 × 10 ¹⁷ cm ^-3 and doped with Si.

The nAl _x Ga _{1 -x} As graded layer (emitter contact layer) 6 has a thickness of 50 nm, a mixed crystal ratio of x = 0.3 → 0, and a concentration of 5 × 10 ¹⁷ → 5 ×. 10
It is formed by doping with Si at ¹⁸ cm ^-3 .

The n ⁺ GaAs layer 7 has a thickness of 100 nm.
And is formed by doping with Si at a concentration of 5 × 10 ¹⁸ cm ⁻³ .

N ⁺ In _y Ga _{1 -y} As graded layer 8
Has a thickness of 50 nm, a mixed crystal ratio of y = 0 → 0.5, a concentration of 1 × 10 ¹⁹ → 4 × 10 ¹⁹ cm ⁻³ , and is formed by Se doping.

The n ⁺ In _y Ga _{1 -y} As layer 9 has a thickness of 5
0 nm, the mixed crystal ratio is y = 0.5, and the concentration is 4 × 10
It is formed by Se-doping at ¹⁹ cm ^-3 .

If the sheet concentration of the indium planar doped layer 10 is lower than 1 × 10 ¹¹ cm ⁻² , the effect of improving the current amplification factor β is recognized. Although the upper limit is not well understood, even at 4 × 10 ¹² cm ⁻² , the effect of improving the current amplification factor β is recognized.

Next, a method of manufacturing a semiconductor device wafer according to the present invention will be described together with its operation.

In this embodiment, an example in which a MOVPE (organic metal vapor phase epitaxy) method is used as a method for growing a semiconductor device wafer will be described, but an MBE (molecular beam epitaxy) method may be used.

First, the S.A. Each source gas containing Ga and As and n such as Si are formed on the I GaAs substrate 1.
The collector contact layer 2 showing n-type conduction is grown while flowing a type dopant or the like.

Then, an In planar dopant layer 10 is formed on the collector contact layer 2 by doping In with a planar dopant.

Further, the In planar dopant layer 1
A collector layer 3 having the same n-type conductivity is grown on the layer 0 with a dopant concentration lower than that of the collector contact layer 2.

On this collector layer 3, Ga, A
s or p, while flowing a source gas containing In, Ga, As or Al, Ga, As and a p-type dopant such as C, etc.
A base layer 4 exhibiting mold conduction is grown.

Further, on the base layer 4, the base layer 4
N-type dopants such as Si exhibiting n-type conduction to form a heterojunction with Al, Ga, As or In, G
The emitter layer 5 is grown by flowing each source gas containing a and P.

Then, an emitter contact layer 6 having the same n-type conductivity is grown on the emitter layer 5 with a lower dopant concentration than that of the emitter layer 5 to manufacture an epitaxial wafer.

The epitaxial wafer having the structure in which the In planar doped layer 10 is provided between the collector contact layer 2 and the collector
The defect generated in the step does not propagate into the epitaxial layers 3 and 4 grown thereon, and the current amplification β
Is improved. As a result, the life of the hetero bipolar transistor manufactured from the epitaxial wafer is significantly improved.

As a modification of this embodiment, In
Instead of planar doping the interface between the collector contact layer 2 and the collector layer 3 with indium arsenide (InA).
A similar effect can be obtained by using s).

However, in this case, since there is a lattice mismatch,
If the thickness is not less than the critical film thickness (about 3 nm), the crystal itself will be broken, and the characteristics described above will worsen rather than lose the above-mentioned effects. As for the lower limit, the current amplification factor β is improved by laminating two or more atomic layers. Specifically, I
The nAs layer has a thickness of 0.5 to 3 nm.

Next, the current amplification factor β in the present invention was examined.

The conventional structure (a structure without a planar dopant at the interface between the collector layer and the collector contact layer) and the H structure of the present invention structure
A BT epiwafer was grown, an evaluation HBT having an emitter size of 100 μm square was fabricated by a simple process, and the current amplification factor β at an emitter current density of 10 ³ A / cm ² was compared.

The planar doping amount of In was set to 1 × 10 ¹² cm ^{−2 in} sheet concentration.

In order to compare only the effect of planar doping of In, epi growth conditions other than planar doping were exactly the same.

As a result of evaluating the current amplification factor β of the epi-wafer manufactured as described above, the current amplification factor β of the HBT manufactured using the conventional epi-wafer was about 100, while the current amplification factor β of the HBT manufactured using the conventional epi-wafer was evaluated. The current amplification factor β of the HBT thus obtained exceeded 150, and the current amplification factor β could be improved by about 1.5 times.

In this embodiment, each epi layer is formed with a predetermined thickness, a mixed crystal ratio, and a doping amount, but it is needless to say that the present invention is not limited to these values.

[0048]

In summary, according to the present invention, even if a defect occurs due to a high concentration of impurity doping into the collector contact layer, the In planar doped layer or the InAs planar doped layer prevents the propagation of the defect. , The current amplification factor β, which has been suppressed, is improved, and the life of an element manufactured using the same can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of an HBT epi-wafer showing an embodiment of the present invention.

[Explanation of symbols]

1 S. I GaAs substrate 2 n ⁺ GaAs layer (collector contact layer) 3 n ^- GaAs layer (collector layer) 4 p ⁺ GaAs layer (base layer) 5 n Al _x Ga _{1 -x} As layer (emitter layer) 6 nAl _x Ga _{1- x} As graded layer (the emitter contact layer) 7 n ⁺ GaAs layer _{^{8 n + In y Ga 1-}} y As graded layer _{^{9 n + In y Ga 1-}} y As layer 10 an In planar-doped layer

Claims (5)

[Claims] 1. A collector contact layer and a collector layer exhibiting n-type conduction on a gallium arsenide substrate, and a base layer made of gallium arsenide crystal, indium gallium arsenide crystal or aluminum gallium arsenide crystal exhibiting p-type conduction, In a semiconductor device wafer having an emitter layer made of an aluminum gallium arsenide crystal or an indium gallium phosphide crystal which is heterojunctioned to the base layer and exhibits n-type conduction, and an emitter contact layer exhibiting n-type conduction, A semiconductor device wafer having an indium planar doped layer formed between a contact layer and a collector layer. 2. The semiconductor device wafer according to claim 1, wherein an indium arsenide layer is formed instead of the indium planar doped layer. 3. An indium planar doped layer or an indium arsenide layer having an indium sheet concentration of at least 1 ×.
3. The semiconductor device wafer according to claim 1, which has a ^{size of} 10 ¹¹ cm ^-2 or more. 4. The indium arsenide layer has a thickness of 0.5 to 3 n.
3. The semiconductor device wafer according to claim 2, wherein the semiconductor device wafer is formed in m. 5. The semiconductor device wafer according to claim 1, wherein each layer is grown by MOVPE or MBE.