JP2000124444A - Semiconductor device and epitaxial wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent defects caused by a GaAs substrate from propagating in an epitaxial layer in a HBT and an epitaxial wafer. SOLUTION: A semiconductor device has the following layers formed on a GaAs substrate 1 directly or via a buffer layer: a collector contact layer 2 showing an n-type conduction, a collector layer 3 showing an n-type conduction, a base layer 4 made of a GaAs crystal, an InGaAs crystal or an AlGaAs crystal showing a p-type conduction, an emitter layer 5 made of an AlGaAs crystal or an InGaP crystal forming a heterojunction to the base layer 4 and showing an n-type conduction, and an emitter contact layer 6 showing an n-type conduction. Here, a planar layer doped with In is made between the GaAs substrate 1 and the collector contact layer 2 or the buffer layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a hetero-bipolar transistor (HBT) and an epitaxial wafer serving as a substrate for forming the semiconductor device, in particular, AlGa.
The present invention relates to improvement of current amplification factor β and life of As / GaAs-based HBT.

[0002]

2. Description of the Related Art A semiconductor device such as a heterojunction bipolar transistor (HBT) or a heterojunction FET (HEMT) is a compound semiconductor wafer (on a semiconductor substrate) cut out of an ingot of a III-V compound semiconductor crystal such as GaAs. Then, it is manufactured using an epitaxial wafer obtained by epitaxially growing various semiconductor layers.

[0003] This epitaxial wafer is made of GaAs.
(Gallium arsenide), InP (indium gallium phosphide)
, A ternary system such as InGaAs (indium gallium arsenide), a quaternary system such as InGaAsP (indium gallium arsenide phosphorus), and even InAlGa.
It has a multilayer structure of various compound semiconductors such as a quinary system such as AsP (indium aluminum gallium arsenide phosphorus).

For example, AlGaAs / GaAs HBTs
Describes a method in which an n-type GaAs collector contact layer, an n-type GaAs collector layer, a p-type GaAs base layer, an n-type AlGaAs (aluminum gallium arsenide) emitter layer, and an emitter contact layer showing n-type conduction are sequentially laminated on a GaAs substrate. It is composed. Moreover, InGaAs is used for the base layer.
Crystal or AlGaAs crystal, or the emitter layer
There is also a type using an nGaP crystal.

However, until now, attention has been paid to the emitter layer and the base layer to improve the crystallinity and the interface between them,
Attempts have been made to improve the reliability of the device. Therefore, little research has been conducted on the interface between the substrate and the epitaxial layer that is first grown thereon. In the conventional method, the collector contact layer (before growing the collector contact layer immediately before the collector contact layer is grown) without any particular operation on the substrate. (Including a buffer layer for gettering oxygen and the like).

[0006]

However, according to the conventional method, since the collector contact layer and the buffer layer are immediately grown on the semiconductor substrate without any particular operation, defects latent in the substrate propagate directly to the epitaxial layer. Had been done. For this reason, defects due to the substrate propagate to the base layer, the emitter layer, and their interfaces, which are important in the characteristics of the HBT, and the current increase / subtraction ratio β is reduced, and the reliability of the element is also reduced. Had dropped.

In order to solve the above problem, it is necessary to prevent defects caused by the substrate from propagating into the epitaxial layer.

An object of the present invention is to provide a semiconductor device and an epitaxial wafer which solve the above-mentioned problems and prevent a defect caused by a substrate from propagating into an epitaxial layer.

[0009]

In order to achieve the above object, a semiconductor device according to the present invention comprises GaAs (gallium arsenide).
A collector contact layer exhibiting n-type conduction, a collector layer exhibiting n-type conduction, and GaAs (gallium arsenide) exhibiting p-type conduction on a substrate directly or through a buffer layer.
A base layer made of one of a crystal, an InGaAs (indium gallium arsenide) crystal and an AlGaAs (aluminum gallium arsenide) crystal, and an AlGaAs exhibiting n-type conductivity forming a heterojunction with the base layer.
An emitter layer made of (aluminum gallium arsenide) crystal or InGaP (indium gallium phosphide) crystal;
A semiconductor device in which emitter contact layers exhibiting a positive conduction are sequentially stacked, wherein a planar doped layer of In (indium) is provided between the GaAs substrate and the collector contact layer or between the GaAs substrate and the buffer layer. (Claims 1 and 2).

Further, the epitaxial wafer of the present invention comprises:
A collector contact layer exhibiting n-type conduction on a GaAs substrate, directly or via a buffer layer, by MOVPE (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy); A collector layer exhibiting conduction of
GaAs crystal, InGaAs crystal or A
a base layer composed of one of the lGaAs crystals, an emitter layer composed of an AlGaAs crystal or an InGaP crystal exhibiting n-type conduction forming a heterojunction with the base layer, and an emitter contact layer exhibiting n-type conduction Are sequentially grown on the epitaxial wafer.
In is planar-doped with In between the As substrate and the collector contact layer or between the GaAs substrate and the buffer layer.

In the semiconductor device or the epitaxial wafer, it is preferable that the sheet concentration of the planar doped In is at least 1 × 10 ¹¹ cm ⁻² or more.

Further, in the semiconductor device or the epitaxial wafer of the present invention, a planar doped layer of InAs (indium arsenide) may be provided instead of the planar doped layer of In.

The main point of the present invention is to meet the above-mentioned problem of the hetero bipolar transistor (HBT) by forming an interface between a GaAs substrate and a collector contact layer grown on the GaAs substrate.
It has been found that the planar doping of n prevents defects caused by the GaAs substrate from propagating into the epitaxial layer grown thereon, thereby improving the current increase rate β suppressed by the propagated defects. In this case, the reliability of the HBT element can be greatly improved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the illustrated embodiment.

FIG. 1 shows an AlGaAs / G to which the present invention is applied.
1 shows the structure of an epitaxial wafer for aAs-based HBT.

In FIG. 1, a collector contact layer 2 and a collector layer 3 are laminated on a semi-insulating GaAs substrate 1. The collector contact layer 2 has a thickness of 500
nm, an n ⁺ -type GaAs layer having a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ , and the collector layer 3 is formed of an n ⁻ -type GaAs layer having a thickness of 500 nm and a carrier concentration of 2 × 10 ¹⁶ cm ⁻³ . .

A p ⁺ -type GaAs base layer 4 having a thickness of 70 nm and a carrier concentration of 4 × 10 ¹⁹ cm ⁻³ is formed on the collector layer 3, and an emitter layer 5 is formed thereon.

The emitter layer 5 is made of n-type Al _0.3 G having a carrier concentration of 5 × 10 ¹⁷ cm ^-3 and a thickness of 100 nm by Si doping.
a _0.7 As layer 5a and a carrier concentration of 5 × 10 ¹⁷ cm with a thickness of about 50 nm and grown on this layer 5a by gradually decreasing the AlAs mixed crystal ratio x from 0.3 to 0.
^And an n ⁺ -type Al _x Ga _{1 -x} As graded layer 5b of ^-3 to 5 × 10 ¹⁸ cm ^-3 .

On the emitter layer 5, an n ⁺ -type GaAs layer 6 a having a thickness of 100 nm and a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ by Si doping is formed as an emitter contact layer 6.
And a thickness of 50 nm formed on this layer 6a and a carrier concentration by Se doping of 1 × 10 ¹⁹ cm ⁻³ to 4 × 10 ¹⁹
cm ⁻³ n ⁺ -type In _y Ga _{1 -y} As (y = 0 → 0.5) graded layer 6 b, 50 nm thick formed on graded layer 6 b, carrier concentration by Se doping 4
× 10 ¹⁹ cm ⁻³ n ⁺ type In _0.5 Ga _0.5 As layers 6c are sequentially stacked.

Further, this HBT wafer has a semi-insulating Ga
At the interface between the As substrate 1 and the collector contact layer 2, In is planar-doped as indicated by an arrow 7.

Next, a method of manufacturing the above-described epitaxial wafer for HBT will be described.

Metalorganic vapor phase epitaxy MOVPE method
The wafer structure shown in FIG. 1 is epitaxially grown. As a growth material, triethyl gallium (T
EGa), TMAl (trimethylaluminum) or TEAl (triethylaluminum) as an Al raw material, A
AsH ₃ (arsine) is used as a raw material. further,
disilane (Si ₂ H ₆ ) as an n-type dopant material,
Hydrogen selenide (H ₂ Se) is used as a p-type dopant raw material for a carbon (C) halide (CBr ₄ , CCl).
₄ etc.).

A semi-insulating GaAs substrate 1 is placed on a susceptor in a reaction tube (not shown), and the susceptor is heated by a high-frequency coil to warm the GaAs substrate 1.

When growing the GaAs layers 2, ₃ , 4, and 6a, TEG (triethyl gallium) and AsH ₃ (arsine) are fed into a reaction tube, and thermal decomposition of TEG and AsH ₃ is caused on the GaAs substrate 1. A GaAs crystal is grown. In the case of crystals of the AlGaAs layers 5a and 5b, TEG, TMAl (trimethylaluminum) and A
Simultaneously flow sH ₃ and grow continuously in the same reaction tube.

When growing the compound semiconductors of the collector contact layer 2, the collector layer 3, the base layer 4, the emitter layer 5, and the emitter contact layer 6, the growth temperature is set to a constant temperature in the range of 500 ° C. to 550 ° C. Keep and grow.

As for the doping material, the collector contact layer 2 and the collector layer 3 are doped with Si using disilane Si ₂ H ₆ as a dopant material. Here, CBr ₄ is used as a doping material of the base layer 4 as a halide of C. The n-type Al _0.25 Ga _0.75 As layer 5a of the emitter layer 5 is also doped with Si using Si ₂ H ₆ . Then, for the n ⁺ -type InGaAs emitter contact layer 6, hydrogen selenide (H ₂
Se is doped using Se).

First, when growing an n ⁺ -type GaAs crystal as the collector contact layer 2 on the semi-insulating GaAs substrate 1, prior to growing the n ⁺ -type GaAs crystal on the upper surface of the semi-insulating GaAs substrate 1, the concentration of In is reduced to a planar sheet concentration. 1 × 10 ¹¹ cm ^-2 to 4
× 10 ¹² cm ^−2, and then doping is performed. Then, the dopant gas S is added to TEGa and AsH ₃ gas.
GaAs crystal is grown while i ₂ H ₆ (disilane) is simultaneously flowed and a large amount of Si is doped into the gas. When an n ⁻ -type GaAs crystal is grown thereon as the collector layer 3, Si ₂ H ₆ is simultaneously flowed into TMG and AsH ₃ gas, and n ⁻ -type Ga
A As crystal is grown.

The base layer 4 has a carrier concentration of 4 × using a halide CBr _{4 of} C as a doping material.
A p-type GaAs of 10 ¹⁹ cm ^-3 and a thickness of about 100 nm is grown. In this case, the supply amount of the halide of C is fixed,
The carrier concentration and the film thickness of the base layer 4 made of p-type GaAs can be controlled by changing the supply amount of the group V raw material and controlling the C concentration. Here, the growth temperature is 520 ° C., the CBr ₄ flow rate is 4.9 × 10 ⁻² cc / min,
The EGa flow rate was 2.0 cc / min. Under these conditions,
When the AsH ₃ flow rate was changed from 13 to 98 cc / min, the carrier concentration changed from 0.6 to 3.3 × 10 ¹⁹ cm ⁻³ . On the other hand, the growth rate is constant even when the flow rate of AsH ₃ is changed.
The reason why carbon (C) was employed as the GaAs p-type dopant for the base layer 4 is that C has a small diffusion constant and thus H
This is because the BT element has a long life and high reliability.

Next, the crystal of the emitter layer 5 is grown continuously at the same temperature as that of the base layer 4, that is, at 520 ° C. without any interruption time for raising the temperature. This emitter layer 5
AlGaAs n-type AlGaAs layer 5a, when growing 5b crystals, TEGa, flow Si ₂ H ₆ dopant gas in the gas TMAl and AsH ₃ (the disilane) simultaneously, while Si doping in the gas as Grow crystals.

As the emitter contact layer 6, n ⁺ Type Ga
When growing a crystal of an As layer, TEGa and AsH _{3 are used.}
Of hydrogen selenide (H ₂
Se) is simultaneously flowed, and an n ⁺ -type GaAs crystal is grown while doping Se into the gas in a large amount.

With respect to the above-described structure, a conventional structure (a structure in which the interface between the substrate and the collector contact layer is not planar-doped) and an HBT epitaxial wafer having the above-described structure of the present invention are grown, respectively. To make an HBT with an emitter size of 100 microns square.
The current increase rate β at a current density of 10 ³ A / cm ² of the emitter was compared.

The planar doping amount of In was 1 × 10 ¹² cm ^{−2 in} sheet concentration. In addition, in order to compare only the effect of planar doping of In, epitaxial growth conditions other than planar doping were the same for both.

As a result of evaluating the current increase rate β, in the structure used this time, the β of HBT grown by the conventional method without planar doping is about 100, whereas the β of the present invention is In the HBT grown by the method, β exceeded 150, and the current increase rate β could be improved about 1.5 times.

It is considered that the improvement of the current increase rate β was made possible by greatly reducing defects in the epitaxial layer. In addition, there is a relationship between the current increase rate β and the reliability, and it has been found that in the same structure, the higher the current increase rate β is, the higher the reliability is.

Therefore, it can be said that the present invention can greatly improve the current increase rate β, and that the reliability of the HBT element can be considerably improved.

The numerical range of the sheet concentration of planarly doped In was examined. As a result, when the lower limit was higher than 1 × 10 ¹¹ cm ^{−2, the} effect of improving the current increase rate β was recognized. I'm not sure about the upper limit,
Even at 4 × 10 ¹² cm ⁻² , the effect of improving the current increase rate β was recognized.

In the above embodiment, In the embodiment in which the collector contact layer is grown immediately on the substrate, In is planar-doped at the interface between the substrate and the collector contact layer.
In a mode of growing a buffer layer for the purpose of gettering oxygen or the like before growing a collector contact layer,
Similarly, when In was planar-doped at the interface between the substrate and the buffer layer, the effect of improving the current increase rate β was also observed.

In the above embodiment, In is planar-doped at the interface between the substrate and the collector contact layer.
The same effect of improving the current increase rate β was obtained by planar doping using InAs instead of using In.
However, since there is lattice mismatch, unless the thickness of the InAs planar doped layer is set to a critical thickness (about 3 nm) or less, the crystal itself is broken, and the effect is lost. As for the lower limit, improvement of the current increase rate β was observed when two or more atomic layers were stacked.

Further, in the above embodiment, the MOVPE
A case in which a semiconductor device or an epitaxial wafer is manufactured using the method has been described, but the present invention is not limited to this, and the present invention is applied to a form manufactured using another thin film growth method such as an MBE method (molecular beam epitaxy method). Even in this case, the same effect as above can be obtained.

[0040]

According to the semiconductor device and the epitaxial wafer of the present invention, since the interface between the GaAs substrate and the collector contact layer or the buffer layer grown thereon is planar-doped with In, the defect caused by the substrate is obtained. Does not propagate into the epitaxial layer grown thereon. For this reason, in a semiconductor device such as an HBT, the current increase ratio β suppressed by the propagated defect can be improved, and the reliability of the element can be greatly improved. Further, according to the present invention, it is possible to provide an epitaxial wafer for HBT with improved current enhancement rate β and reliability.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structural example of an epitaxial wafer for HBT to which the present invention is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semi-insulating GaAs substrate 2 Collector contact layer 3 Collector layer 4 Base layer 5 Emitter layer 6 Emitter contact layer 7 Arrow (In planar doping)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/338 29/812 F-term (Reference) 5F003 AZ07 BB05 BC01 BC05 BE01 BE05 BF06 BM03 BP08 BP31 BP32 5F052 JA05 KA02 KA05 5F102 GJ05 HC01

Claims (8)

[Claims] 1. A collector contact layer showing n-type conductivity, a collector layer showing n-type conductivity on a GaAs substrate,
a base layer made of one of a GaAs crystal, an InGaAs crystal and an AlGaAs crystal exhibiting p-type conduction, and an emitter made of an AlGaAs crystal or an InGaP crystal exhibiting n-type conduction forming a heterojunction with the base layer A semiconductor device in which a layer and an emitter contact layer exhibiting n-type conduction are sequentially stacked, wherein a planar doped layer of In is provided between the GaAs substrate and the collector contact layer. A buffer layer, a collector contact layer exhibiting n-type conduction, a collector layer exhibiting n-type conduction, a GaAs crystal exhibiting p-type conduction, and InG.
a base layer made of one of an aAs crystal or an AlGaAs crystal, an emitter layer made of an AlGaAs crystal or an InGaP crystal showing an n-type conduction forming a heterojunction with the base layer, and showing an n-type conduction A semiconductor device in which an emitter contact layer is sequentially stacked, wherein a planar dope layer of In is provided between the GaAs substrate and the buffer layer. 3. The semiconductor device according to claim 1, wherein the sheet concentration of the planar-doped In is at least 1 × 10 ¹¹ cm ⁻² or more. 4. The semiconductor device according to claim 1, wherein InAs is used instead of said In-planar doped layer.
A semiconductor device provided with a planar doped layer. 5. The method according to claim 1, wherein the GaVPE method or the MBE method is used.
On an As substrate, a collector contact layer showing n-type conduction, a collector layer showing n-type conduction, and a base layer made of one of GaAs crystal, InGaAs crystal, or AlGaAs crystal showing p-type conduction. AlGaAs showing n-type conductivity forming a heterojunction with the base layer
In an epitaxial wafer in which an emitter layer made of a crystal or InGaP crystal and an emitter contact layer exhibiting n-type conduction are sequentially grown, In is planar-doped between the GaAs substrate and the collector contact layer. Epitaxial wafer. 6. The method according to claim 1, wherein the GaVPE method or the MBE method is used.
A buffer layer, a collector contact layer exhibiting n-type conduction, a collector layer exhibiting n-type conduction,
GaAs crystal, InGaAs crystal or A
a base layer made of one of lGaAs crystals, an emitter layer made of AlGaAs crystal or InGaP crystal showing n-type conductivity forming a heterojunction with the base layer, and an emitter contact layer showing n-type conductivity 1. An epitaxial wafer, wherein In is planar-doped between the GaAs substrate and the buffer layer. 7. The epitaxial wafer according to claim 5, wherein the sheet concentration of the planar-doped In is at least 1 × 10 ¹¹ cm ⁻² or more. 8. The epitaxial wafer according to claim 5, wherein said In is planarly doped instead of In.
An epitaxial wafer characterized by planar doping of InAs.