JP2000311976A - High-frequency bipolar transistor - Google Patents

High-frequency bipolar transistor

Info

Publication number
JP2000311976A
JP2000311976A JP11120090A JP12009099A JP2000311976A JP 2000311976 A JP2000311976 A JP 2000311976A JP 11120090 A JP11120090 A JP 11120090A JP 12009099 A JP12009099 A JP 12009099A JP 2000311976 A JP2000311976 A JP 2000311976A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor chip
collector
bipolar transistor
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11120090A
Other languages
Japanese (ja)
Other versions
JP3307361B2 (en
Inventor
Hiroshi Kato
博 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12009099A priority Critical patent/JP3307361B2/en
Priority to DE10019250A priority patent/DE10019250A1/en
Priority to KR10-2000-0022372A priority patent/KR100447460B1/en
Publication of JP2000311976A publication Critical patent/JP2000311976A/en
Application granted granted Critical
Publication of JP3307361B2 publication Critical patent/JP3307361B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
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    • H01L2924/30107—Inductance

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Bipolar Transistors (AREA)
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Abstract

PROBLEM TO BE SOLVED: To obtain a high-frequency bipolar transistor, which is increased in cut-off frequency and improved in high-frequency characteristics. SOLUTION: A high-frequency bipolar transistor is composed of a semiconductor chip 1, a base 3, collector 4, and emitter electrode 2 of the chip 1, bonding wires 6, 7, and 5 which connect the bonding pads to the electrodes 3, 4, and 2, and a sealing resin 8 which seals up these component parts, where the semiconductor chip 1 is arranged on the emitter electrode 2, and the base electrode 3 and the collector electrode 4 are provided sandwiching the emitter electrode 2 between them.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、高周波バイポーラ
トランジスタに係わり、特に、遮断周波数を上昇させ、
高周波特性を改善した高周波バイポーラトランジスタに
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency bipolar transistor, and more particularly, to increasing a cut-off frequency.
The present invention relates to a high-frequency bipolar transistor having improved high-frequency characteristics.

【０００２】[0002]

【従来の技術】主な高周波特性である遮断周波数ｆTは
次式で示される。 ｆT ＝１／２π（τｅ＋τｂ＋τｃ＋τｘ） τｅ＝ｋＴＣｔｅ／ｑＩｃ τｂ＝ＷＢ2 ／ＮＤｎ Ｄｎ＝ｋＴμＢ τｃ＝ｒｃｓ＊Ｃｃｂ τｘ＝Ｘｓ／２ｖｘ ここで、ｋ：ボルツマン定数 Ｔ：絶対温度 Ｃｔｅ：エミッタ容量 ｑ ：電子の単位電価量 Ｉｃ ：コレクタ電流 ＷＢ：ベース幅 Ｎ ：定数 μＢ：電子の移動度 ｒｃｓ：コレクタ対抗 Ｃｃｂ：コレクタ容量 Ｘｓ ：コレクタ空乏層幅 ｖｘ ：コレクタ空乏層走行飽和速度 このように、ｆT は、コレクタ容量によって増減する。
コレクタ容量を極力小さくすることがｆT 向上には望ま
しいが、実際の半導体装置には能動部のコレクタ容量だ
けでなくパッケージによる容量、即ち、寄生容量が存在
し、ｆT 向上のさまたげになっている。例えば、図４に
示した特開平６−２２４３２０号公報のトランジスタで
は、ベース電極１１とコレクタ電極１３とが隣り合うか
ら、１．０ｍｍ×０．５ｍｍサイズのパッケージでは、
０．１ｐＦのパッケージ寄生容量が存在し、この為、遮
断周波数の上昇には、限度があった。Cut-off frequency f T is the Related Art The main high-frequency characteristics are represented by the following formula. f T = 1 / 2π (τe + τb + τc + τx) τe = kTCte / qIc τb = WB 2 / NDn Dn = kTμB τc = rcs * Ccb τx = Xs / 2vx where k: Boltzmann constant T: absolute temperature Cte: emitter capacity q: Unit charge of electrons Ic: Collector current WB: Base width N: Constant μB: Electron mobility rcs: Collector resistance Ccb: Collector capacitance Xs: Collector depletion layer width vx: Collector depletion layer running saturation speed Thus, f T increases or decreases depending on the collector capacitance.
It is desirable to reduce the collector capacitance as much as possible to improve f T. However, in an actual semiconductor device, not only the collector capacitance of the active portion but also the capacitance due to the package, that is, the parasitic capacitance exists, hindering the improvement of f T. I have. For example, in the transistor disclosed in JP-A-6-224320 shown in FIG. 4, the base electrode 11 and the collector electrode 13 are adjacent to each other.
There is a package parasitic capacitance of 0.1 pF, which limits the cutoff frequency rise.

【０００３】[0003]

【発明が解決しようとする課題】本発明の目的は、上記
した従来技術の欠点を改良し、特に、遮断周波数を上昇
させ、高周波特性を改善した新規な高周波バイポーラト
ランジスタを提供するものである。SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art, and in particular to provide a novel high-frequency bipolar transistor having an increased cut-off frequency and improved high-frequency characteristics.

【０００４】[0004]

【課題を解決するための手段】本発明は上記した目的を
達成するため、基本的には、以下に記載されたような技
術構成を採用するものである。即ち、本発明に係わる高
周波バイポーラトランジスタの第１態様は、半導体チッ
プと、この半導体チップのベース、コレクタ、エミッタ
電極と、前記半導体チップのボンディングパッドと前記
各電極とを接続するボンディングワイヤと、これらを封
止する封止樹脂とで構成した高周波バイポーラトランジ
スタにおいて、前記半導体チップをエミッタ電極上に配
置し、前記エミッタ電極を挟んで、ベース電極、コレク
タ電極を設けたことを特徴とするものであり、叉、第２
態様は、半導体チップと、この半導体チップのベース、
コレクタ、エミッタ電極と、前記半導体チップのボンデ
ィングパッドと前記各電極とを接続するボンディングワ
イヤと、これらを封止する封止樹脂とで構成した高周波
バイポーラトランジスタにおいて、前記半導体チップを
コレクタ電極上に配置し、前記エミッタ電極を挟んで、
ベース電極、コレクタ電極を設けたことを特徴とするも
のであり、叉、第３態様は、前記トランジスタをエッミ
タ接地回路で用いることを特徴とするものであり、叉、
第４態様は、前記夫々の電極の一部を前記封止樹脂より
露出せしめたリードレスパッケージであることを特徴と
するものであり、叉、第５態様は、前記各電極は、封止
樹脂の一方の面にのみ露出せしめたことを特徴とするも
のであり、叉、第６態様は、前記各電極を略一直線に配
置したことを特徴とするものである。SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, a first aspect of the high-frequency bipolar transistor according to the present invention includes a semiconductor chip, a base, a collector, and an emitter electrode of the semiconductor chip, a bonding wire connecting the bonding pad of the semiconductor chip to each of the electrodes, and And a sealing resin for sealing the semiconductor chip, wherein the semiconductor chip is disposed on an emitter electrode, and a base electrode and a collector electrode are provided with the emitter electrode interposed therebetween. The second
Aspects include a semiconductor chip and a base of the semiconductor chip,
In a high-frequency bipolar transistor including a collector, an emitter electrode, a bonding wire connecting the bonding pad of the semiconductor chip and each of the electrodes, and a sealing resin for sealing the semiconductor chip, the semiconductor chip is disposed on the collector electrode Then, with the emitter electrode interposed,
A third aspect is characterized in that a base electrode and a collector electrode are provided, and a third aspect is characterized in that the transistor is used in an EMI emitter grounding circuit.
A fourth aspect is a leadless package in which a part of each of the electrodes is exposed from the sealing resin, and a fifth aspect is that each of the electrodes is formed of a sealing resin. The sixth aspect is characterized in that the electrodes are arranged substantially in a straight line.

【０００５】[0005]

【発明の実施の形態】本発明に係わる高周波バイポーラ
トランジスタは、半導体チップと、この半導体チップの
ベース、コレクタ、エミッタ電極と、前記半導体チップ
のボンディングパッドと前記各電極とを接続するボンデ
ィングワイヤと、これらを封止する封止樹脂とで構成し
た高周波バイポーラトランジスタにおいて、前記半導体
チップをエミッタ電極上に配置し、前記エミッタ電極を
挟んで、ベース電極、コレクタ電極を設けたことを特徴
とするものである。DETAILED DESCRIPTION OF THE INVENTION A high frequency bipolar transistor according to the present invention comprises a semiconductor chip, a base, a collector and an emitter electrode of the semiconductor chip, a bonding wire connecting a bonding pad of the semiconductor chip and each of the electrodes, and In a high-frequency bipolar transistor composed of a sealing resin for sealing them, the semiconductor chip is arranged on an emitter electrode, and a base electrode and a collector electrode are provided with the emitter electrode interposed therebetween. is there.

【０００６】本発明のトランジスタは、特に、エッミタ
接地回路に用いて顕著な効果を奏する。The transistor of the present invention has a remarkable effect particularly when used in an emitter grounding circuit.

【０００７】[0007]

【実施例】以下に、本発明に係わる高周波バイポーラト
ランジスタの具体例を図面を参照しながら詳細に説明す
る。 （第１の具体例）図１（ａ），（ｂ）は、本発明に係わ
る高周波バイポーラトランジスタの第１の具体例の構造
を示す図であって、これらの図には、半導体チップ１
と、この半導体チップ１のベース、コレクタ、エミッタ
電極３、４、２と、前記半導体チップ１のボンディング
パッドと前記各電極３、４、２とを接続するボンディン
グワイヤ６、７、５と、これらを封止する封止樹脂８と
で構成した高周波バイポーラトランジスタにおいて、前
記半導体チップ１をエミッタ電極２上に配置し、前記エ
ミッタ電極２を挟んで、ベース電極３、コレクタ電極４
を設けたことを特徴とする高周波バイポーラトランジス
タが示されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a high-frequency bipolar transistor according to the present invention will be described below in detail with reference to the drawings. (First Specific Example) FIGS. 1A and 1B are diagrams showing the structure of a first specific example of a high-frequency bipolar transistor according to the present invention.
A base, a collector, and an emitter electrode 3, 4, and 2 of the semiconductor chip 1, bonding wires 6, 7, 5 for connecting a bonding pad of the semiconductor chip 1 to each of the electrodes 3, 4, 2; The semiconductor chip 1 is arranged on the emitter electrode 2, and the base electrode 3 and the collector electrode 4 are sandwiched between the emitter electrode 2.
Are provided, and a high-frequency bipolar transistor is provided.

【０００８】また、前記夫々の電極の一部を封止樹脂８
より露出せしめたリードレスパッケージであることを特
徴とする高周波バイポーラトランジスタが示され、更
に、前記電極２、３、４は、封止樹脂８の一方の面８ａ
にのみ露出せしめた高周波バイポーラトランジスタが示
されている。以下に、第１の具体例を図１を用いて、更
に詳細に説明する。Further, a part of each of the electrodes is sealed with a sealing resin 8.
A high-frequency bipolar transistor characterized by being a more exposed leadless package is shown. Further, the electrodes 2, 3, and 4 are provided on one surface 8a of a sealing resin 8.
1 shows a high-frequency bipolar transistor which is exposed only to the high-frequency bipolar transistor. Hereinafter, the first specific example will be described in more detail with reference to FIG.

【０００９】エミッタ電極２は、ベース電極３とコレク
タ電極４の間にあり、エミッタ電極２、ベース電極３、
コレクタ電極４の一端は、封止樹脂８より一部が露出し
ており、本発明の本半導体装置を基板（図示していな
い）に実装する際、基板の配線パターンと接触するよう
に構成している。エミッタ電極２上に半導体チップ１が
搭載され、チップ１上のエミッタボンディングパッドと
エミッタ電極２とがエミッタボンディングワイヤ５を介
し接続され、チップ１上のベースボンディングパッドと
ベース電極３とがベースボンディングワイヤ６を介し接
続され、同様に、チップ１上に形成されたコレクタボン
ディングパッドとコレクタ電極４とはコレクタボンディ
ングワイヤ７を介し接続されている。The emitter electrode 2 is located between the base electrode 3 and the collector electrode 4, and the emitter electrode 2, the base electrode 3,
One end of the collector electrode 4 is partially exposed from the sealing resin 8, and is configured to come into contact with a wiring pattern of the substrate when the semiconductor device of the present invention is mounted on a substrate (not shown). ing. The semiconductor chip 1 is mounted on the emitter electrode 2, the emitter bonding pad on the chip 1 is connected to the emitter electrode 2 via the emitter bonding wire 5, and the base bonding pad on the chip 1 and the base electrode 3 are connected to the base bonding wire. 6, and similarly, a collector bonding pad formed on the chip 1 and the collector electrode 4 are connected via a collector bonding wire 7.

【００１０】エミッタ電極２、ベース電極３、コレクタ
電極４の一端は、封止樹脂８より下方に露出しており、
基板に実装される際、基板の引き出し電極と接触する。
また、エミッタ電極２、ベース電極３、コレクタ電極４
を、半導体装置上面から見た場合、樹脂７の内側に存在
し、樹脂７の外側には存在しない（図１）。次に、本発
明の半導体装置の製造方法について説明する。One end of each of the emitter electrode 2, the base electrode 3, and the collector electrode 4 is exposed below the sealing resin 8,
When mounted on a substrate, it comes into contact with a lead electrode of the substrate.
Further, an emitter electrode 2, a base electrode 3, a collector electrode 4
Are located inside the resin 7 and not outside the resin 7 when viewed from the top of the semiconductor device (FIG. 1). Next, a method for manufacturing a semiconductor device of the present invention will be described.

【００１１】初めに、銅製のリードフレームのエミッタ
電極となる部分を写真食刻法を用いて０．０５ｍｍエッ
チングし、凹部を形成する。続いて、銀をリードフレー
ムにめっきし、金型を用いたプレス法でベース電極３、
エミッタ電極２、コレクタ電極４に分離する。続いて、
チップ１を銀ペースト等の接続材を用いて、エミッタ電
極２上に搭載する。接続材はこの他、金アンチモンや金
すずや、金シリコン共晶などを用いてもよい。次に、金
線からなるベースボンディングワイヤ６、コレクタボン
ディング７、エミッタボンディングワイヤ５を用いて、
チップ１上に設けたベースボンディングパット、エミッ
タボンディングパット、コレクタボンディングパットと
ベース電極３、エミッタ電極２、コレクタ電極４とを夫
々接続する。First, a portion serving as an emitter electrode of a copper lead frame is etched by 0.05 mm using a photolithography method to form a concave portion. Subsequently, silver is plated on the lead frame, and the base electrode 3 is pressed by a pressing method using a mold.
It is separated into an emitter electrode 2 and a collector electrode 4. continue,
The chip 1 is mounted on the emitter electrode 2 using a connecting material such as a silver paste. In addition, as the connection material, gold antimony, gold tin, gold silicon eutectic, or the like may be used. Next, using a base bonding wire 6, a collector bonding 7, and an emitter bonding wire 5 made of a gold wire,
The base bonding pad, emitter bonding pad, and collector bonding pad provided on the chip 1 are connected to the base electrode 3, the emitter electrode 2, and the collector electrode 4, respectively.

【００１２】次に、縦１ｍｍ、横０．５ｍｍ、高さ０．
３ｍｍとなるように封入金型を用いて、エポキシ系樹脂
を金型に封入し、整形する。この際、樹脂の外に余分に
はみ出していたベース電極３、エミッタ電極２、コレク
タ電極４は切り取られる。この整形はダイシング法を用
いる。最後に、露出しているベース電極３、エミッタ電
極２、コレクタ電極４上を半田めっきし、ベース電極
３、エミッタ電極２、コレクタ電極４に半田層を形成す
る。Next, the height is 1 mm, the width is 0.5 mm, and the height is 0.
An epoxy resin is sealed in a mold so as to have a thickness of 3 mm, and is shaped. At this time, the base electrode 3, the emitter electrode 2, and the collector electrode 4 that have protruded out of the resin are cut off. This shaping uses a dicing method. Finally, the exposed base electrode 3, emitter electrode 2, and collector electrode 4 are plated with solder to form a solder layer on the base electrode 3, emitter electrode 2, and collector electrode 4.

【００１３】図４の従来例の場合、１．０ｍｍ×０．５
ｍｍサイズのパッケージでは、０．１ｐＦのパッケージ
寄生容量が存在したが、この具体例では、０．０１ｐＦ
であり、従来の１／１０にすることが出来た。また、上
記トランジスタをエミッタ接地で用いる場合、従来のト
ランジスタのＣｃｂが０．０５ｐＦの場合、ｆTが２０
ＧＨｚであるのに対し、本具体例の半導体装置では、２
５ＧＨｚと良好な値を得ることが出来た。 （第２の具体例）図２（ａ），（ｂ）は、本発明に係わ
る高周波バイポーラトランジスタの第２の具体例の構造
を示す図であって、これらの図には、前記半導体チップ
１をコレクタ電極４上に配置し、前記エミッタ電極２を
挟んで、ベース電極３、コレクタ電極４を設けたことを
特徴とする高周波バイポーラトランジスタが示されてい
る。In the case of the conventional example shown in FIG.
The package parasitic capacitance of 0.1 pF was present in the package of the mm size.
, Which was reduced to 1/10 of the conventional value. In the case of using the transistor in grounded emitter, if Ccb conventional transistor is 0.05 pF, f T 20
GHz, whereas the semiconductor device of this specific example has a frequency of 2 GHz.
A good value of 5 GHz was obtained. (Second Specific Example) FIGS. 2A and 2B are diagrams showing the structure of a second specific example of the high-frequency bipolar transistor according to the present invention. Is disposed on a collector electrode 4, and a base electrode 3 and a collector electrode 4 are provided with the emitter electrode 2 interposed therebetween.

【００１４】この場合、各ボンディグワイヤはインダク
タンスを小さくするため、複数本形成できるから、利得
も更に向上できる等の効果を有する。 （第３の具体例）図３は、本発明に係わる高周波バイポ
ーラトランジスタの第３の具体例の構造を示す図であ
る。In this case, since a plurality of bonding wires can be formed in order to reduce the inductance, there is an effect that the gain can be further improved. (Third Specific Example) FIG. 3 is a diagram showing the structure of a third specific example of the high-frequency bipolar transistor according to the present invention.

【００１５】第１、第２の具体例では、前記各電極２、
３、４を略一直線に配置したが、第３の具体例では、前
記各電極２、３、４が、一直線上に乗らないように配置
したことを特徴とするものである。In the first and second specific examples, each of the electrodes 2,
Although the electrodes 3 and 4 are arranged substantially in a straight line, the third specific example is characterized in that the electrodes 2, 3 and 4 are arranged so as not to be on a straight line.

【００１６】[0016]

【発明の効果】本発明に係わる高周波バイポーラトラン
ジスタは、上述のように構成したので、特に、エミッタ
接地回路で用いた場合、コレクタ容量が小さくなり、従
って、遮断周波数が上昇し、高周波特性を改善すること
が出来る。Since the high-frequency bipolar transistor according to the present invention is constructed as described above, especially when used in a common-emitter circuit, the collector capacitance is reduced, so that the cutoff frequency is increased and the high-frequency characteristics are improved. You can do it.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係わる高周波バイポーラトランジスタ
の第１の具体例を示す図である。FIG. 1 is a diagram showing a first specific example of a high-frequency bipolar transistor according to the present invention.

【図２】本発明の第２の具体例を示す図である。FIG. 2 is a diagram showing a second specific example of the present invention.

【図３】本発明の第３の具体例を示す図である。FIG. 3 is a diagram showing a third specific example of the present invention.

【図４】従来例を示す図である。FIG. 4 is a diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ エミッタ電極 ３ ベース電極 ４ コレクタ電極 ５ エミッタボンディングワイヤ ６ ベースボンディングワイヤ ７ コレクタボンディングワイヤ ８ 封止樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Emitter electrode 3 Base electrode 4 Collector electrode 5 Emitter bonding wire 6 Base bonding wire 7 Collector bonding wire 8 Sealing resin

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップと、この半導体チップのベ
ース、コレクタ、エミッタ電極と、前記半導体チップの
ボンディングパッドと前記各電極とを接続するボンディ
ングワイヤと、これらを封止する封止樹脂とで構成した
高周波バイポーラトランジスタにおいて、前記半導体チ
ップをエミッタ電極上に配置し、前記エミッタ電極を挟
んで、ベース電極、コレクタ電極を設けたことを特徴と
する高周波バイポーラトランジスタ。1. A semiconductor chip comprising: a semiconductor chip; a base, a collector, and an emitter electrode of the semiconductor chip; a bonding wire for connecting a bonding pad of the semiconductor chip to each of the electrodes; and a sealing resin for sealing these. A high-frequency bipolar transistor according to claim 1, wherein said semiconductor chip is arranged on an emitter electrode, and a base electrode and a collector electrode are provided with said emitter electrode interposed therebetween. 【請求項２】 半導体チップと、この半導体チップのベ
ース、コレクタ、エミッタ電極と、前記半導体チップの
ボンディングパッドと前記各電極とを接続するボンディ
ングワイヤと、これらを封止する封止樹脂とで構成した
高周波バイポーラトランジスタにおいて、前記半導体チ
ップをコレクタ電極上に配置し、前記エミッタ電極を挟
んで、ベース電極、コレクタ電極を設けたことを特徴と
する高周波バイポーラトランジスタ。2. A semiconductor chip comprising: a semiconductor chip; a base, a collector, and an emitter electrode of the semiconductor chip; a bonding wire for connecting a bonding pad of the semiconductor chip to each of the electrodes; and a sealing resin for sealing these. A high-frequency bipolar transistor according to claim 1, wherein said semiconductor chip is arranged on a collector electrode, and a base electrode and a collector electrode are provided with said emitter electrode interposed therebetween. 【請求項３】 前記トランジスタをエッミタ接地回路で
用いることを特徴とする請求項１又は２記載の高周波バ
イポーラトランジスタ。3. The high-frequency bipolar transistor according to claim 1, wherein the transistor is used in an emitter grounding circuit. 【請求項４】 前記夫々の電極の一部を前記封止樹脂よ
り露出せしめたリードレスパッケージであることを特徴
とする請求項１乃至３の何れかに記載の高周波バイポー
ラトランジスタ。4. The high-frequency bipolar transistor according to claim 1, wherein said high-frequency bipolar transistor is a leadless package in which a part of each of said electrodes is exposed from said sealing resin. 【請求項５】 前記各電極は、封止樹脂の一方の面にの
み露出せしめたことを特徴とする請求項１乃至４の何れ
かに記載の高周波バイポーラトランジスタ。5. The high-frequency bipolar transistor according to claim 1, wherein each of the electrodes is exposed only on one surface of a sealing resin. 【請求項６】 前記各電極を略一直線に配置したことを
特徴とする請求項１乃至５の何れかに記載の高周波バイ
ポーラトランジスタ。6. The high-frequency bipolar transistor according to claim 1, wherein said electrodes are arranged substantially in a straight line.
JP12009099A 1999-04-27 1999-04-27 High frequency bipolar transistor Expired - Fee Related JP3307361B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP12009099A JP3307361B2 (en) 1999-04-27 1999-04-27 High frequency bipolar transistor
DE10019250A DE10019250A1 (en) 1999-04-27 2000-04-18 High frequency bipolar transistor
KR10-2000-0022372A KR100447460B1 (en) 1999-04-27 2000-04-27 High-frequency bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12009099A JP3307361B2 (en) 1999-04-27 1999-04-27 High frequency bipolar transistor

Publications (2)

Publication Number Publication Date
JP2000311976A true JP2000311976A (en) 2000-11-07
JP3307361B2 JP3307361B2 (en) 2002-07-24

Family

ID=14777669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12009099A Expired - Fee Related JP3307361B2 (en) 1999-04-27 1999-04-27 High frequency bipolar transistor

Country Status (3)

Country Link
JP (1) JP3307361B2 (en)
KR (1) KR100447460B1 (en)
DE (1) DE10019250A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011101065A (en) * 2011-02-24 2011-05-19 Rohm Co Ltd Semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260563A (en) * 1993-03-03 1994-09-16 Mitsubishi Electric Corp Package for transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011101065A (en) * 2011-02-24 2011-05-19 Rohm Co Ltd Semiconductor device

Also Published As

Publication number Publication date
JP3307361B2 (en) 2002-07-24
KR20000077094A (en) 2000-12-26
KR100447460B1 (en) 2004-09-07
DE10019250A1 (en) 2001-03-15

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