JP2000304822A - Test method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To modify a test pattern so as to be in accord with input-output switching timing of an input-output terminal of an integrated circuit measured by an input-output switch timer. SOLUTION: A simulation is executed (step 1), an input/output switch timing of an integrated circuit is calculated to create a test program and a test pattern (step 2, step 3). At first the speed of the integrated circuit is measured for grasping the speed characteristics of the integrated circuit at a factory (step 4), using the results, a conversion factor of the test pattern is calculated (step 5) to convert the test pattern so as to have a switch timing suitable for the integrated circuit (step 6), and a test is executed using the changed test pattern (step 7) to sort good or defective products (steps 8, 9).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor device, and more particularly, to a method for testing a semiconductor device in which a good product and a defective product are distinguished by using a test pattern.

[0002]

2. Description of the Related Art In the prior art of semiconductor test patterns,
Since the test program and the test pattern are created based on the simulation result under the worst condition, a difference occurs between the input / output switching timing of the input / output terminals of the actual integrated circuit and the input / output switching timing of the tester. In addition, a short circuit and a floating state occur between the input / output terminal of the integrated circuit and the tester for a long time, and a non-defective product becomes NG in the FUNCTION test.

FIG. 7 is a graph showing a correlation between a delay time of an inverter and a test pattern in the conventional semiconductor test pattern described above. As shown in FIG. 7A, when the switching timing of the input / output terminal of the integrated circuit from the input to the output is faster than the switching timing of the tester as shown in FIG. 7A, a short circuit occurs between the input / output terminal of the integrated circuit and the tester. 7B, and conversely, as shown in FIG. Further, as shown in FIG. 7C, when the switching timing from the output to the input of the input / output terminal of the integrated circuit is faster than the switching timing of the tester,
The tester becomes a floating state between the input / output terminal of the integrated circuit and the tester, and as shown in FIG.

A cause of the above-mentioned state is that manufacturing variations occur in the manufacturing process of the integrated circuit, so that integrated circuits having different speeds are produced. In such a case, since the test program and the test pattern are created under the worst condition, the difference between the input / output switching timing of the input / output terminals of the actual integrated circuit and the input / output switching timing of the tester increases.

Next, a malfunction in the conventional example will be described with reference to FIGS. FIG. 8 is a circuit diagram showing a configuration when the integrated circuit malfunctions, and FIG. 9 is a timing chart when the integrated circuit malfunctions. FIG.
As shown in FIG. 9, when the input / output terminals are in a floating state, erroneous data is latched in the integrated circuit as shown in FIG. Becomes N in the FUNCTION test
It will be G. Further, when the input / output terminal is in a short-circuit state, a large current may flow into the buffer of the output unit, and the integrated circuit may be destroyed.

[0006]

As described above, in the conventional method for testing a semiconductor device, when the manufacturing variation fluctuates to the condition of operating the earliest, the test program and the test pattern operate under the condition of operating the slowest. Because of this, there is a problem that the difference between the input / output switching timing of the input / output terminals of the actual integrated circuit and the input / output switching timing of the tester increases.

If the input / output terminals are in a floating state, erroneous data may be latched in the integrated circuit, or a through current may flow into the buffer of the input section, causing the integrated circuit to become unstable, and the FUNGCTION test may indicate NG. There was a problem that would be.

Further, when the input / output terminals are short-circuited, there is a problem that a large current may flow into the buffer of the output unit and destroy the integrated circuit.

Therefore, an object of the present invention is to correct the test pattern so that the input / output switching timing matches the input / output switching timing of the input / output terminal of the integrated circuit to be measured in order to solve the above-mentioned problem.

[0010]

In order to achieve the above object, a method of testing a semiconductor device according to the present invention is directed to a method of testing a semiconductor device by executing a simulation to create a test program and a test pattern to test the semiconductor device. In the test method, the speed of the semiconductor device is measured by an inverter to understand the speed characteristics of the semiconductor device, and the internal speed is measured from the speed measurement result using the correlation between the speed measurement result and the delay time of the internal circuit. An input / output switching timing produced by a circuit is obtained, and a test is performed by modifying a test pattern so that the input / output switching timing matches the input / output switching timing of an input / output terminal of a semiconductor device to be measured.

It is preferable that the simulation is performed under one of a condition where the speed of the semiconductor device is the slowest, a condition where the speed is fastest, and a normal condition.

Further, the speed measurement is preferably performed by measuring the frequency of a speed measurement circuit in which an odd number of inverters are connected in a ring.

Further, it is preferable that the input / output switching timing is obtained by calculating a conversion coefficient obtained by utilizing the correlation between the result of the speed measurement and the delay time of the internal circuit.

Preferably, the conversion coefficient is obtained by dividing the delay time of the inverter by the delay time of the inverter based on the speed measurement.

Further, the input / output switching timing is preferably obtained by multiplying the conversion coefficient by the input / output switching timing value of the input / output terminal of the test pattern.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings.

When a test of an integrated circuit is performed, a simulation is executed as preprocessing (step 1), the input / output switching timing of the integrated circuit is calculated, and a test program and a test pattern are created (steps 2 and 3). ). First, the factory measures the speed of the integrated circuit in order to grasp the speed characteristics of the integrated circuit (step 4), and calculates the test pattern conversion coefficient using the result (step 5). The test pattern is converted at the switching timing (step 6), a test is performed using the changed test pattern (step 7), and non-defective products and defective products are selected (steps 8 and 9).

[0018]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

First, a first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a flowchart showing the steps of the embodiment of the present invention. FIG. 1 (a)
1 shows a pretreatment step, and FIG. 1B is a flow showing a step in a factory. FIG. 2 is a circuit diagram showing a speed measuring circuit of an integrated circuit in which inverters are connected in a ring. FIG. 3 is a graph used to calculate the delay time of the inverter from the speed measurement result. FIG. 4 is a correlation diagram showing the delay time of the inverter and the input / output switching timing.

First, the pre-processing step of FIG. 1A will be described. In step 1, the integrated circuit performs a simulation under the worst condition (the condition at which the speed is the slowest) to change the input / output switching timing of the integrated circuit. calculate. Next, a test program is created in step 2.
Next, in step 3, a test pattern is created in accordance with the input / output switching timing of the integrated circuit obtained in step 1.

Next, the process in the factory shown in FIG. 1B will be described. In order to grasp the speed characteristic of the integrated circuit in step 4, an odd number of inverters as shown in FIG. The frequency of the speed measurement circuit of the integrated circuit is measured. Next, in step 5, the conversion coefficient K for calculating the input / output switching timing generated in the internal circuit is calculated from the speed measurement result using the correlation between the speed measurement result and the delay time of the internal circuit. For example, when the measurement result of the speed measurement circuit arranged in the integrated circuit is aHz, as shown in FIG. 3, the delay time TPDa of the inverter is obtained from the speed measurement result obtained in advance.
Ask for. TPDa is TPDworst to TPDbe
It is within the manufacturing control range during st. Next, as shown in FIG. 4, the variation in the delay time of the inverter is proportional to the variation in the input / output switching timing generated by the internal circuit. Therefore, the input / output switching timing IO_TPDa is determined by calculating the inverter delay time TPDa. You can ask. Therefore, the conversion coefficient K = TPDa / TPDworst obtained from the delay time of the inverter can be used as the conversion coefficient K for the input / output switching timing. next,
In step 6, the input / output switching timing value of the input / output terminal of the test pattern created based on the simulation result under the worst condition is changed to the input / output switching timing value * K.
To minimize the difference between the input / output switching timing of the actual integrated circuit and the input / output switching timing of the tester (test pattern correction). Next, step 7
The test is performed using a test pattern modified so that the input / output switching timing matches the input / output switching timing of the input / output terminal of the integrated circuit to be measured. If the result is NG, the test result is defective in step 8 and OK. If step 9
It becomes a good product. Thus, a stable test can be performed by performing the test method of the semiconductor device of the present invention.

Next, another embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a flowchart showing a second embodiment of the present invention. In this description, only parts different from the first embodiment of the present invention shown in FIG. 1 will be described. In the present embodiment, a test pattern having an input / output switching timing that can uniformly cover the range in which the speed of the integrated circuit fluctuates due to manufacturing variations in step 3 'is used.
Create more than one (test patterns 2 to N). For example,
The test pattern in which the input / output switching timing is set according to the fastest condition within the manufacturing control range is set as test pattern 1, and the input / output switching timing is set according to the slowest condition within the manufacturing control range. The set test pattern is referred to as test pattern N, and N
A test pattern suitable for each input / output switching timing is prepared by dividing by -1 and allocating from 2 to N-1 in ascending order. Next, in Step 4, the test pattern whose input / output switching timing is closest to the input / output switching timing of the input / output terminal of the integrated circuit is measured in Step 5 ′ in accordance with the characteristics of the integrated circuit obtained by measuring the speed of the integrated circuit. Select For example, as shown in FIG. 6, the measurement result of the speed measurement circuit arranged in the integrated circuit is A
In the case of Hz, the test pattern K is selected from the correlation between the speed measurement result and the test pattern, and the difference between the input / output switching timing of the input / output terminals of the actual integrated circuit and the input / output switching timing of the tester can be minimized.

[0024]

Since the difference between the input / output switching timing of the input / output terminals of the actual integrated circuit and the input / output switching timing of the tester can be minimized, the difference between the input / output terminals of the integrated circuit and the tester during the test can be reduced. The short circuit or floating period can be shortened, and the integrated circuit can be stably tested.

When the input / output switching timing of the input / output terminal takes 30 ns under the worst condition,
Since the time is 12 ns under the st condition, the difference between the actual input / output switching timing of the input / output terminal of the integrated circuit and the input / output switching timing of the tester is 18 ns. On the other hand, in the present invention, it can be reduced to several ns.

[Brief description of the drawings]

FIG. 1 is a flowchart showing steps of an embodiment of the present invention. FIG. 1A shows a pretreatment step, and FIG.
Is a flow showing a process in the factory.

FIG. 2 is a circuit diagram showing a speed measurement circuit of an integrated circuit in which inverters are connected in a ring shape.

FIG. 3 is a graph used to calculate a delay time of an inverter from a speed measurement result.

FIG. 4 is a correlation diagram showing a delay time of an inverter and an input / output switching timing.

FIG. 5 is a flowchart showing a second embodiment of the present invention. FIG. 5A shows a pretreatment step, and FIG.
Is a flow showing a process in the factory.

FIG. 6 is a correlation diagram between a delay time of an inverter and a test pattern.

FIG. 7 is a timing chart showing the correlation between the input / output switching timing of the integrated circuit and the tester. (A) shows a case where the input of the integrated circuit is fast, (b) shows a case where the input is slow, (c) shows a case where the output is fast, and (d) shows a case where the output is slow.

FIG. 8 is a circuit diagram showing a configuration when an integrated circuit malfunctions.

FIG. 9 is a timing chart when an integrated circuit malfunctions.

[Explanation of symbols]

 1 Simulation 2 Test program creation 3 Test pattern creation 3 'Test pattern 2 to N creation 4 Speed measurement 5 Conversion coefficient calculation 6 Test pattern correction 6' Test pattern selection 7 Test 8 Defective 9 Non-defective

Continued on the front page F-term (reference) 2G032 AB02 AC08 AD06 AE12 AK15 AL00 4M106 AA20 AB20 AC01 AC02 CA09 CA57 DJ11 DJ18

Claims (6)

[Claims] 1. A method of testing a semiconductor device by executing a simulation to generate a test program and a test pattern to test the semiconductor device, wherein an inverter is used to determine the speed characteristics of the semiconductor device. A speed measurement is performed, and an input / output switching timing made in the internal circuit is obtained from a result of the speed measurement using a correlation between the result of the speed measurement and a delay time of an internal circuit, and the input / output switching is performed. A test method for a semiconductor device, wherein a test is performed by correcting a test pattern so that a timing matches an input / output switching timing of an input / output terminal of a semiconductor device to be measured. 2. The simulation according to claim 1, wherein the speed of the semiconductor device is the slowest condition, the fastest condition,
2. The method for testing a semiconductor device according to claim 1, wherein the method is performed under one of normal conditions. 3. The method according to claim 1, wherein the speed measurement is performed by measuring a frequency of a speed measurement circuit having an odd number of inverters connected in a ring. . 4. The input / output switching timing is obtained by calculating a conversion coefficient obtained by using a correlation between a result of the speed measurement and a delay time of an internal circuit. 4. The method for testing a semiconductor device according to any one of claims 1 to 3. 5. The method according to claim 4, wherein the conversion coefficient is obtained by dividing a delay time of the inverter by a delay time of the inverter based on the speed measurement. 6. The semiconductor device according to claim 5, wherein said input / output switching timing is obtained by multiplying said conversion coefficient by an input / output switching timing value of an input / output terminal of said test pattern. Test method.