JP2000286552A - Multilayer circuit board - Google Patents

Multilayer circuit board

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Publication number
JP2000286552A
JP2000286552A JP9317799A JP9317799A JP2000286552A JP 2000286552 A JP2000286552 A JP 2000286552A JP 9317799 A JP9317799 A JP 9317799A JP 9317799 A JP9317799 A JP 9317799A JP 2000286552 A JP2000286552 A JP 2000286552A
Authority
JP
Japan
Prior art keywords
thermal expansion
coefficient
circuit board
double
multilayer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9317799A
Other languages
Japanese (ja)
Inventor
Yasushi Inoue
泰史 井上
Toku Nagasawa
徳 長沢
Masakazu Sugimoto
正和 杉本
Kei Nakamura
圭 中村
Takuji Okeyui
卓司 桶結
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP9317799A priority Critical patent/JP2000286552A/en
Publication of JP2000286552A publication Critical patent/JP2000286552A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To ensure high connection reliability for both primary mounting and secondary mounting by laminating and integrating a plurality of both side copper clad substrates having different coefficient of thermal expansion containing a metal foil in an insulation layer through adhesive layers in the order of coefficient of thermal expansion. SOLUTION: First through third both side copper clad substrates 13 are laminated collectively in the order of coefficient of thermal expansion using adhesive layers 10 to produce a multilayer circuit board. In order to electrically connect the both side copper clad substrates 1-3 of the multilayer circuit board thus produced, through holes are drilled after collective lamination and subjected to through hole plating. A multilayer circuit board thus produced can be provided with a gradient in the coefficient of thermal expansion in the thickness direction thereof. Consequently, the coefficient of thermal expansion can be set low for the silicon chip mounting face having a low coefficient of thermal expansion and can be set high for the secondary mounting face to a glass epoxy substrate having a high coefficient of thermal expansion. According to the arrangement, highly reliable primary mounting and secondary mounting can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップを搭
載するのに適した多層回路基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board suitable for mounting a semiconductor chip.

【0002】[0002]

【従来の技術】近年の電子機器の小型化,高性能化に伴
い、電子機器を構成する半導体装置およびこれを実装す
る多層プリント配線基板には、小型薄型化,高性能化,
高信頼性が要求されている。これらの要求を受けて、実
装方法はピン挿入型パッケージから表面実装型パッケー
ジへと移行してきており、最近では半導体チップを直接
基板に実装するフリップチップ実装と呼ばれる実装方法
が研究されている。
2. Description of the Related Art With the recent miniaturization and high performance of electronic devices, semiconductor devices constituting electronic devices and multilayer printed wiring boards on which the electronic devices are mounted have been reduced in size and thickness and improved in performance.
High reliability is required. In response to these demands, the mounting method has shifted from a pin insertion type package to a surface mounting type package, and recently, a mounting method called flip chip mounting, in which a semiconductor chip is directly mounted on a substrate, has been studied.

【0003】ところが、従来のガラスエポキシ基板の熱
膨張率は15〜18ppm/℃と大きく、熱膨張率が3
〜4ppm/℃のシリコンチップを直接フリップチップ
実装すると、両者の熱膨張率の差により接続部に応力が
かかる。このようなチップと基板の熱膨張率の差により
発生する応力で、例えば、半田バンプ接続の場合には半
田にクラックが発生したり、完全に切断する等の問題が
ある。
However, the thermal expansion coefficient of the conventional glass epoxy substrate is as large as 15 to 18 ppm / ° C., and the thermal expansion coefficient is 3
When a silicon chip of 44 ppm / ° C. is directly flip-chip mounted, stress is applied to the connection due to the difference in the coefficient of thermal expansion between the two. The stress generated due to the difference in the coefficient of thermal expansion between the chip and the substrate causes problems such as cracks in the solder or complete cutting in the case of solder bump connection.

【0004】そこで、このような応力を緩和するため
に、チップと基板の間にアンダーフィル材と呼ばれる接
着剤を注入し、応力が接続部に集中しないようにする方
法等が実施されているが、これらの方法によっても、今
後のチップの大型化,パッドの狭ピッチ化が進むことを
考慮すると、信頼性は充分ではなく、さらに高い信頼性
を確保するには、基板自体の熱膨張率を下げることが不
可欠である。このような背景の中、本出願人は、熱膨張
率の低い金属箔を絶縁層中に含んだ低熱膨張基板をすで
に提案している(特願平9−260201号)。
In order to alleviate such stress, a method of injecting an adhesive called an underfill material between the chip and the substrate to prevent the stress from concentrating on the connection portion has been implemented. However, even with these methods, the reliability is not sufficient in consideration of the future increase in the size of the chip and the narrowing of the pitch of the pads. To ensure higher reliability, the thermal expansion coefficient of the substrate itself must be reduced. It is essential to lower. Against this background, the present applicant has already proposed a low thermal expansion substrate including a metal foil having a low thermal expansion coefficient in an insulating layer (Japanese Patent Application No. 9-260201).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、例え
ば、基板の熱膨張率をシリコンチップの熱膨張率(3.
5ppm/℃)にまで低くすると、チップと基板の間の
接続信頼性(1次実装)は向上するが、さらに別の基板
(ガラスエポキシ基板)への2次実装が必要な用途にお
いては、低熱膨張基板とガラスエポキシ基板の間の熱膨
張率差によって接続信頼性が低下するという問題があっ
た。
However, for example, the coefficient of thermal expansion of the substrate is determined by the coefficient of thermal expansion of the silicon chip (3.
When the temperature is lowered to 5 ppm / ° C.), the connection reliability between the chip and the substrate (primary mounting) is improved, but in applications requiring secondary mounting on another substrate (glass epoxy substrate), low heat is required. There is a problem that connection reliability is reduced due to a difference in thermal expansion coefficient between the expansion substrate and the glass epoxy substrate.

【0006】本発明は、このような事情に鑑みなされた
もので、1次実装,2次実装ともに高い接続信頼性を確
保できる多層回路基板の提供をその目的とする。
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a multilayer circuit board that can ensure high connection reliability in both primary mounting and secondary mounting.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
め、本発明の多層回路基板は、金属箔を絶縁層中に含ん
だ熱膨脹率の異なる複数の両面銅張基板が、熱膨脹率の
大きい順に接着剤層を介して積層され、一体化されてい
るという構成をとる。
In order to achieve the above object, in the multilayer circuit board of the present invention, a plurality of double-sided copper-clad substrates having different thermal expansion coefficients each containing a metal foil in an insulating layer have a large thermal expansion coefficient. The configuration is such that they are sequentially laminated via an adhesive layer and integrated.

【0008】すなわち、本発明者らは、1次実装,2次
実装ともに高い接続信頼性を確保できる多層回路基板を
得るため、鋭意研究した結果、金属箔を絶縁層中に含ん
だ熱膨脹率の異なる複数の両面銅張基板が、熱膨脹率の
大きい順に接着剤層を介して積層され、一体化されてい
ると、1次実装,2次実装ともに高い接続信頼性を確保
できることを見出し、本発明に到達した。すなわち、本
発明の多層回路基板では、そのチップ搭載面の熱膨張率
を小さくし、ガラスエポキシ基板に接続する面の熱膨張
率を大きくすることにより、1次実装,2次実装ともに
高い接続信頼性を確保することができる。
That is, the present inventors have conducted intensive studies to obtain a multilayer circuit board capable of ensuring high connection reliability in both primary and secondary mountings. The present invention has found that when a plurality of different double-sided copper-clad substrates are laminated via an adhesive layer in order of increasing thermal expansion coefficient and integrated, high connection reliability can be ensured in both primary mounting and secondary mounting. Reached. That is, in the multilayer circuit board of the present invention, the coefficient of thermal expansion of the chip mounting surface is reduced, and the coefficient of thermal expansion of the surface connected to the glass epoxy substrate is increased, so that the primary mounting and the secondary mounting have high connection reliability. Nature can be secured.

【0009】つぎに、本発明を詳しく説明する。Next, the present invention will be described in detail.

【0010】本発明の多層回路基板は、図1に示すよう
に、熱膨脹率の異なる複数の両面銅張基板からなってお
り、各両面銅張基板には、両面に銅箔の回路を有する絶
縁層中に金属箔が設けられている(図1では、多層回路
基板は、第1〜第3の両面銅張基板からなっている)。
As shown in FIG. 1, the multilayer circuit board of the present invention comprises a plurality of double-sided copper-clad boards having different coefficients of thermal expansion. A metal foil is provided in the layer (in FIG. 1, the multilayer circuit board is composed of first to third double-sided copper-clad boards).

【0011】上記金属箔は、両面銅張基板の全体の熱膨
張率を制御するものであり、金属種や金属箔の厚みを変
えることにより、両面銅張基板の全体の熱膨張率を変化
させることができる。すなわち、金属種により両面銅張
基板の全体の熱膨張率を制御する場合には、第1の両面
銅張基板に使用する第1の金属箔は熱膨張率が小さいも
のが選択され、第2の両面銅張基板に使用する第2の金
属箔は上記第1の金属箔より大きい熱膨張率を有するも
のが選択される。また、第3の両面銅張基板に使用する
第3の金属箔は第2の金属箔より大きい熱膨張率を有す
るものが選択される。一方、金属箔の厚みにより両面銅
張基板の全体の熱膨張率を制御する場合には、同一の金
属種からなる金属箔を用い、その厚みの関係は、第1の
金属箔>第2の金属箔>第3の金属箔に設定される。も
ちろん、金属種を変える方法と金属箔の厚みを変える方
法の両者を併用してもよい。
The above-mentioned metal foil controls the coefficient of thermal expansion of the entire double-sided copper-clad board, and changes the coefficient of thermal expansion of the entire double-sided copper-clad board by changing the type of metal and the thickness of the metal foil. be able to. That is, when controlling the entire coefficient of thermal expansion of the double-sided copper-clad board according to the type of metal, the first metal foil used for the first double-sided copper-clad board is selected to have a small coefficient of thermal expansion, The second metal foil used for the double-sided copper-clad substrate is selected to have a higher coefficient of thermal expansion than the first metal foil. The third metal foil used for the third double-sided copper-clad substrate is selected to have a higher coefficient of thermal expansion than the second metal foil. On the other hand, when controlling the entire thermal expansion coefficient of the double-sided copper-clad board by the thickness of the metal foil, a metal foil made of the same metal type is used, and the relationship of the thickness is as follows: the first metal foil> the second metal foil. Metal foil> third metal foil is set. Of course, both the method of changing the metal type and the method of changing the thickness of the metal foil may be used in combination.

【0012】上記金属箔の種類としては、あらゆるもの
が使用されるが、経済性,加工性の面よりチタン,SU
S,銅,ニッケル,アルミニウム,鉄−ニッケル系合
金,鉄−ニッケル−コバルト系合金が推奨される。特
に、鉄−ニッケル(−コバルト)系合金は、鉄とニッケ
ルの含有率の割合により熱膨張率の異なるものが得られ
ることから好適に使用される。このような金属箔は、そ
の厚みが10〜300μmのものが好適に用いられる。
この範囲以下であると、両面銅張基板の全体の熱膨張率
が安定せず、この範囲以上であると、両面回路の接続信
頼性が低下する。
As the type of the metal foil, any type can be used.
S, copper, nickel, aluminum, an iron-nickel alloy, and an iron-nickel-cobalt alloy are recommended. In particular, an iron-nickel (-cobalt) -based alloy is preferably used because different alloys having different coefficients of thermal expansion are obtained depending on the content ratio of iron and nickel. Such a metal foil having a thickness of 10 to 300 μm is suitably used.
Below this range, the coefficient of thermal expansion of the entire double-sided copper-clad board will not be stable, and above this range, the connection reliability of the double-sided circuit will decrease.

【0013】上記各両面銅張基板を互いに積層一体化さ
せる時に使用される接着剤の室温でのヤング率は1.0
GPa以下に設定するのがよい。これは、熱膨張率の異
なる両面銅張基板を一体化すると、多層化した基板が熱
膨張率の低い側(第1の両面銅張基板)を凸にして反る
ことがあるからである。この反りは、上記各両面銅張基
板の熱膨張率の差が大きいほど発生しやすい。このた
め、接着剤の室温でのヤング率を低く設定すると、上記
熱膨張率差によって生じる歪みを吸収することができ、
基板の反りを最小限に抑えることができる。
The Young's modulus at room temperature of the adhesive used for laminating and integrating each of the above double-sided copper-clad substrates is 1.0.
It is better to set it to GPa or less. This is because, when a double-sided copper-clad substrate having a different coefficient of thermal expansion is integrated, the multilayered substrate may warp with the side with the lower coefficient of thermal expansion (first double-sided copper-clad substrate). This warpage is more likely to occur as the difference between the coefficients of thermal expansion of the double-sided copper-clad substrates increases. For this reason, if the Young's modulus at room temperature of the adhesive is set low, it is possible to absorb the distortion caused by the difference in the coefficient of thermal expansion,
The warpage of the substrate can be minimized.

【0014】上記接着剤としては、特に限定しないが、
例えば、エポキシ系,ポリイミド系,ポリイミド−エポ
キシ混合系,ポリエーテルイミド等が使用される。
The adhesive is not particularly limited,
For example, epoxy type, polyimide type, polyimide-epoxy mixed type, polyetherimide, etc. are used.

【0015】本発明の多層回路基板の製造方法の1例を
説明する。すなわち、まず、スルーホール接続用孔11
aを開けた第1の金属箔11の両面に、絶縁層の片面に
導体層(銅箔)が形成された積層体21を接着剤22を
用いて貼り合わせ(図3参照)、両面に導体層7aを有
する基材23を作製する(図4参照)。ついで、スルー
ホール接続用孔11aの位置にそれよりも小さい孔24
を開け、銅めっきを行い、両導体層7aをスルーホール
めっき部14で繋ぐ(図5参照)。つぎに、通常のエッ
チング法により、両導体層7aに回路形成を行い、第1
の両面銅張基板1を作製する(図6参照)。
An example of a method for manufacturing a multilayer circuit board according to the present invention will be described. That is, first, the through-hole connecting holes 11 are formed.
The laminated body 21 in which the conductor layer (copper foil) is formed on one side of the insulating layer is bonded to both sides of the first metal foil 11 having the opening a with an adhesive 22 (see FIG. 3), and the conductors are formed on both sides. A substrate 23 having the layer 7a is produced (see FIG. 4). Then, a hole 24 smaller than the through hole connection hole 11a is formed.
Is opened, copper plating is performed, and both conductor layers 7a are connected by through-hole plating portions 14 (see FIG. 5). Next, a circuit is formed on both conductor layers 7a by a normal etching method,
(See FIG. 6).

【0016】つぎに、上記の方法と同様にして、第2、
第3の両面銅張基板2,3(図7参照)を作製する。こ
こで、第2の両面銅張基板2の熱膨張率は、第1の両面
銅張基板1の熱膨張率より大きく、かつ、第3の両面銅
張基板3の熱膨張率は第2の両面銅張基板2の熱膨張率
より大きく設定される。
Next, in the same manner as in the above method, the second,
Third double-sided copper-clad substrates 2 and 3 (see FIG. 7) are manufactured. Here, the coefficient of thermal expansion of the second double-sided copper-clad board 2 is larger than the coefficient of thermal expansion of the first double-sided copper-clad board 1, and the coefficient of thermal expansion of the third double-sided copper-clad board 3 is the second. It is set to be larger than the coefficient of thermal expansion of the double-sided copper-clad board 2.

【0017】このような各両面銅張基板1〜3の熱膨張
率の制御は、これに用いる金属箔11〜13(図7参
照)の種類,厚みを選択することにより行うことができ
る。例えば、第1の両面銅張基板1に用いる第1の金属
箔11を50μm厚みの鉄(64重量%)−Ni(36
重量%)合金(熱膨張率=1.5ppm/℃)、第2の
両面銅張基板2に用いる第2の金属箔12を50μm厚
みの鉄(58重量%)−Ni(42重量%)合金(熱膨
張率=4.5ppm/℃)、第3の両面銅張基板3に用
いる第3の金属箔13を50μm厚みのSUS430
(熱膨張率=10.4ppm/℃)とする。
The control of the coefficient of thermal expansion of each of the double-sided copper-clad substrates 1 to 3 can be performed by selecting the type and thickness of the metal foils 11 to 13 (see FIG. 7) used for this. For example, the first metal foil 11 used for the first double-sided copper-clad substrate 1 is made of iron (64% by weight) -Ni (36 wt.
%) Alloy (thermal expansion coefficient = 1.5 ppm / ° C.), a 50 μm thick iron (58% by weight) -Ni (42% by weight) alloy having a second metal foil 12 used for the second double-sided copper-clad substrate 2 (Coefficient of thermal expansion = 4.5 ppm / ° C.) The third metal foil 13 used for the third double-sided copper-clad substrate 3 is made of SUS430 having a thickness of 50 μm.
(Coefficient of thermal expansion = 10.4 ppm / ° C.).

【0018】これら第1〜第3の両面銅張基板1〜3を
接着剤層10(図7参照)を用い、熱膨張率の大きい順
に一括して積層し、多層回路基板を作製する。このよう
にして作製された多層回路基板の各両面銅張基板1〜3
を電気的に接続するために、一括積層後に貫通孔をドリ
ル等を用いて開けたあと、スルーホールめっきを行うよ
うにする。また、第1と第2の両面銅張基板1,2およ
び第2と第3の両面銅張基板2,3を接着する接着フィ
ルム等の接着剤層にドリル,パンチ,レーザー等で孔を
形成し、この孔に導電性物質を充填したのち、一括積層
してもよい。
The first to third double-sided copper-clad substrates 1 to 3 are collectively laminated in ascending order of thermal expansion coefficient using an adhesive layer 10 (see FIG. 7) to produce a multilayer circuit board. Each double-sided copper-clad board 1 to 3 of the multilayer circuit board thus manufactured
In order to electrically connect the through holes, a through hole is opened using a drill or the like after batch lamination, and then through hole plating is performed. Also, holes are formed in an adhesive layer such as an adhesive film for bonding the first and second double-sided copper-clad substrates 1 and 2 and the second and third double-sided copper-clad substrates 2 and 3 with a drill, a punch, a laser, or the like. After the holes are filled with a conductive material, the holes may be laminated at once.

【0019】このようにして得られた本発明の多層回路
基板は、基板の厚み方向に熱膨張率の勾配を持たせるこ
とができ、熱膨張率の小さいシリコンチップ実装面の熱
膨張率を低く、熱膨張率の大きいガラスエポキシ基板等
への2次実装面の熱膨張率を高く設定することが可能に
なる。したがって、ベアチップをフリップチップ実装す
るMCM(マルチチップモジュール)基板や、CPS
(チップサイズパッケージ)用インターポーザー等のド
ーターポードとして好適に使用され、1次実装,2次実
装ともに高信頼の実装が行える。
The multilayer circuit board of the present invention thus obtained can have a gradient of the coefficient of thermal expansion in the thickness direction of the board, and the coefficient of thermal expansion of the silicon chip mounting surface having a small coefficient of thermal expansion can be reduced. In addition, it is possible to set a high coefficient of thermal expansion of the secondary mounting surface on a glass epoxy substrate or the like having a large coefficient of thermal expansion. Therefore, an MCM (multi-chip module) substrate on which a bare chip is flip-chip mounted or a CPS
(Chip size package) It is suitably used as a daughter port of an interposer or the like, and can perform highly reliable mounting in both primary mounting and secondary mounting.

【0020】[0020]

【発明の実施の形態】つぎに、本発明の実施の形態を図
面にもとづいて説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0021】図2は本発明の多層回路基板の一実施の形
態を示している。図において、1〜3は第1〜第3の両
面銅張基板であり、ポリイミド系接着剤からなる接着剤
層10により積層一体化されている。上記各両面銅張基
板1〜3は、ポリイミド樹脂からなる絶縁層4〜6の表
裏両面に銅箔からなる回路7〜9が形成されたもので構
成されており、各絶縁層4〜6中に第1〜第3の金属箔
11〜13が設けられている。14〜16はスルーホー
ルめっき部であり、表裏両面の回路7〜9を電気的に接
続している。17,18は上下に隣り合う2つの両面銅
張基板(第1と第2の両面銅張基板1,2および第2と
第3の両面銅張基板2,3)の回路(回路7,8および
回路8,9)を電気的に接続する半田(導電性物質)で
ある。
FIG. 2 shows an embodiment of the multilayer circuit board of the present invention. In the figure, reference numerals 1 to 3 denote first to third double-sided copper-clad substrates, which are laminated and integrated by an adhesive layer 10 made of a polyimide-based adhesive. Each of the double-sided copper-clad substrates 1 to 3 is configured by forming circuits 7 to 9 made of copper foil on both front and back surfaces of insulating layers 4 to 6 made of a polyimide resin. Are provided with first to third metal foils 11 to 13. Reference numerals 14 to 16 denote through-hole plated portions, which electrically connect the circuits 7 to 9 on both the front and back surfaces. Reference numerals 17 and 18 denote circuits (circuits 7 and 8) of two double-sided copper-clad substrates (first and second double-sided copper-clad substrates 1 and 2 and second and third double-sided copper-clad substrates 2 and 3) vertically adjacent to each other. And solder (conductive material) for electrically connecting the circuits 8 and 9).

【0022】この実施の形態では、第2の金属箔12の
熱膨張率は第1の金属箔11の熱膨張率より大きく、第
3の金属箔13の熱膨張率は第2の金属箔12の熱膨張
率より大きく設定されており、これにより、第2の両面
銅張基板2の熱膨張率は第1の両面銅張基板1の熱膨張
率より大きく、第3の両面銅張基板3の熱膨張率は第2
の両面銅張基板2の熱膨張率より大きく設定されてい
る。
In this embodiment, the coefficient of thermal expansion of the second metal foil 12 is greater than the coefficient of thermal expansion of the first metal foil 11, and the coefficient of thermal expansion of the third metal foil 13 is Is larger than the coefficient of thermal expansion of the second double-sided copper-clad board 2, the coefficient of thermal expansion of the second double-sided copper-clad board 1 is larger than that of the first double-sided copper-clad board 1. Has a coefficient of thermal expansion of 2
Is set to be larger than the coefficient of thermal expansion of the double-sided copper-clad substrate 2.

【0023】上記多層回路基板を、つぎのようにして製
造することができる。すなわち、まず、スルーホール接
続用孔11aを開けた第1の金属箔11の両面に、2枚
の片面銅張ポリイミド積層体21をポリイミド系接着剤
からなる2枚の接着シート22を用いて貼り合わせる
(図3参照)。これにより、ポリイミド樹脂からなる絶
縁層4の表裏両面に銅箔からなる導体層7aが形成され
てなる基材23を作製する(図4参照)。ついで、図5
に示すように、スルーホール接続用孔11aの位置に小
孔24を穿設し、この小孔24に銅めっきを行い、両面
の導体層7aをスルーホールめっき部14で繋ぐ。つぎ
に、通常のエッチング法により、上記両導体層7aに回
路形成を行い、第1の両面銅張基板1を作製する(図6
参照)。
The above-mentioned multilayer circuit board can be manufactured as follows. That is, first, two single-sided copper-clad polyimide laminates 21 are attached to both surfaces of the first metal foil 11 in which the through-hole connection holes 11a are opened using two adhesive sheets 22 made of a polyimide-based adhesive. Match (see FIG. 3). In this way, a base material 23 in which the conductor layer 7a made of copper foil is formed on both front and back surfaces of the insulating layer 4 made of polyimide resin is produced (see FIG. 4). Then, FIG.
As shown in (1), a small hole 24 is formed at the position of the through-hole connecting hole 11a, copper plating is performed on the small hole 24, and the conductor layers 7a on both surfaces are connected by a through-hole plated portion 14. Next, a circuit is formed on both the conductor layers 7a by a normal etching method, and the first double-sided copper-clad substrate 1 is manufactured (FIG. 6).
reference).

【0024】つぎに、上記方法と同様にして、第2,第
3の両面銅張基板2,3を作製する(図7参照)。その
のち、第2,第3の両面銅張基板2,3の上面にポリイ
ミド系接着剤からなる接着剤層10を設け、この接着剤
層10に孔26を形成し、この孔26に半田27を充填
したのち、第1,第2,第3の両面銅張基板1,2,3
の順に一括して積層し、図2に示す多層回路基板を作製
する。
Next, second and third double-sided copper-clad substrates 2 and 3 are manufactured in the same manner as described above (see FIG. 7). Thereafter, an adhesive layer 10 made of a polyimide-based adhesive is provided on the upper surfaces of the second and third double-sided copper-clad substrates 2 and 3, holes 26 are formed in the adhesive layer 10, and solder holes 27 are formed in the holes 26. After filling, the first, second and third double-sided copper-clad substrates 1, 2, 3
Are collectively laminated in this order to produce the multilayer circuit board shown in FIG.

【0025】このように、上記実施の形態では、多層回
路基板の厚み方向に熱膨張率の勾配を持たせることがで
き、1次実装,2次実装ともに高信頼の実装が行える。
このため、シリコンチップ実装面の熱膨張率を低く、ガ
ラスエポキシ基板等への2次実装面の熱膨張率を高く設
定することができる。
As described above, in the above-described embodiment, a gradient of the coefficient of thermal expansion can be provided in the thickness direction of the multilayer circuit board, and highly reliable mounting can be performed for both the primary mounting and the secondary mounting.
Therefore, the coefficient of thermal expansion of the silicon chip mounting surface can be set low, and the coefficient of thermal expansion of the secondary mounting surface on the glass epoxy substrate or the like can be set high.

【0026】[0026]

【実施例1】厚み100μmのニッケル36重量%、鉄
64重量%合金からなる金属箔(熱膨張率1.5ppm
/℃)の両面に、厚み18μmの銅箔と厚み13μmの
ポリイミドからなる2層基材(三井化学社製:NEOF
LEX NEX−131R)をポリイミド系接着シート
(新日鐡化学社製:SPB−035A、ヤング率1.7
GPa)を用いて、加熱加圧接着(40Kg/cm2
200℃,1時間)を行い、第1の両面銅張基板を作製
した。
Embodiment 1 A metal foil made of an alloy of 36% by weight of nickel and 64% by weight of iron (thickness of thermal expansion: 1.5 ppm) having a thickness of 100 μm
/ ° C) on both sides of a two-layer base material made of 18 μm thick copper foil and 13 μm thick polyimide (manufactured by Mitsui Chemicals: NEOF)
LEX NEX-131R) is a polyimide-based adhesive sheet (manufactured by Nippon Steel Chemical Co., Ltd .: SPB-035A, Young's modulus 1.7).
GPa) and heat and pressure bonding (40 Kg / cm 2 ,
(200 ° C., 1 hour) to produce a first double-sided copper-clad substrate.

【0027】つぎに、厚み100μmのチタン箔(熱膨
張率8.6ppm/℃)を用いた以外は、上記と同じ方
法で、第2の両面銅張基板を作製した。さらに、厚み1
00μmのSUS−631(熱膨張率11.8ppm/
℃)を用いた以外は、上記と同じ方法で、第3の両面銅
張基板を作製した。これら第1〜第3の両面銅張基板を
熱膨張率を測定したところ、それぞれ3.5ppm/
℃、9.5ppm/℃、12.5ppm/℃であった。
Next, a second double-sided copper-clad substrate was produced in the same manner as described above, except that a titanium foil having a thickness of 100 μm (coefficient of thermal expansion: 8.6 ppm / ° C.) was used. Furthermore, thickness 1
SUS-631 having a thermal expansion coefficient of 11.8 ppm /
C)), except that a third double-sided copper-clad substrate was produced in the same manner as described above. When the thermal expansion coefficients of these first to third double-sided copper-clad substrates were measured, each was 3.5 ppm /
° C, 9.5 ppm / ° C, and 12.5 ppm / ° C.

【0028】これら熱膨張率の異なる第1〜第3の両面
銅張基板を、ポリイミド系接着剤(宇部興産社製:UP
A−83、ヤング率0.6GPa)を用いて、熱膨張率
の順に加熱加圧接着(40Kg/cm2 ,150℃,1
時間)し、6層の導体層を有する多層回路基板を作製し
た。
The first to third double-sided copper-clad substrates having different coefficients of thermal expansion are bonded to a polyimide-based adhesive (UPE Kosan: UP
A-83, Young's modulus 0.6 GPa), heat and pressure bonding (40 kg / cm 2 , 150 ° C., 1
Then, a multilayer circuit board having six conductor layers was manufactured.

【0029】[0029]

【実施例2】厚み100μmのニッケル42重量%、鉄
58重量%合金からなる金属箔(熱膨張率4.5ppm
/℃)の両面に、厚み18μmの銅箔と厚み13μmの
ポリイミドからなる2層基材(三井化学社製:NEOF
LEX NEX−131R)をポリイミド系接着シート
(新日鐡化学社製:SPB−035A、ヤング率1.7
GPa)を用いて、加熱加圧接着(40Kg/cm2
200℃,1時間)を行い、第1の両面銅張基板を作製
した。
Embodiment 2 A metal foil made of an alloy of 42% by weight of nickel and 58% by weight of iron having a thickness of 100 μm (coefficient of thermal expansion: 4.5 ppm)
/ ° C) on both sides of a two-layer base material made of 18 μm thick copper foil and 13 μm thick polyimide (manufactured by Mitsui Chemicals: NEOF)
LEX NEX-131R) is a polyimide-based adhesive sheet (manufactured by Nippon Steel Chemical Co., Ltd .: SPB-035A, Young's modulus 1.7).
GPa) and heat and pressure bonding (40 Kg / cm 2 ,
(200 ° C., 1 hour) to produce a first double-sided copper-clad substrate.

【0030】つぎに、厚み40μmのニッケル42重量
%、鉄58重量%合金からなる金属箔(熱膨張率4.5
ppm/℃)を用いた以外は、上記と同じ方法で、第2
の両面銅張基板を作製した。さらに、厚み20μmのニ
ッケル42重量%、鉄58重量%合金からなる金属箔
(熱膨張率4.5ppm/℃)を用いた以外は、上記と
同じ方法で、第3の両面銅張基板を作製した。これら第
1〜第3の両面銅張基板を熱膨張率を測定したところ、
それぞれ6.3ppm/℃、9.5ppm/℃、12.
0ppm/℃であった。
Next, a metal foil made of an alloy having a thickness of 40 μm and comprising 42% by weight of nickel and 58% by weight of iron (coefficient of thermal expansion: 4.5)
ppm / ° C.) in the same manner as described above, except that
Was produced. Further, a third double-sided copper-clad substrate is produced in the same manner as described above, except that a metal foil (coefficient of thermal expansion: 4.5 ppm / ° C.) made of an alloy of 42% by weight of nickel and 58% by weight of iron having a thickness of 20 μm is used. did. When the thermal expansion coefficients of these first to third double-sided copper-clad substrates were measured,
6.3 ppm / ° C, 9.5 ppm / ° C, and 12.
It was 0 ppm / ° C.

【0031】これら熱膨張率の異なる第1〜第3の両面
銅張基板を、ポリイミド系接着剤(宇部興産社製:UP
A−83、ヤング率0.6GPa)を用いて、熱膨張率
の順に加熱加圧接着(40Kg/cm2 ,150℃,1
時間)し、6層の導体層を有する多層回路基板を作製し
た。
The first to third double-sided copper-clad substrates having different coefficients of thermal expansion are bonded to a polyimide adhesive (UPE Kosan: UP
A-83, Young's modulus 0.6 GPa), heat and pressure bonding (40 kg / cm 2 , 150 ° C., 1
Then, a multilayer circuit board having six conductor layers was manufactured.

【0032】[0032]

【実施例3】実施例1で使用したポリイミド系接着剤
(宇部興産社製:UPA−83、ヤング率0.6GP
a)の代わりに、ポリイミド系接着材(新日鐡化学社
製:SPB−035A、ヤング率1.7GPa)を用い
て、熱膨張率の異なる第1〜第3の両面銅張基板を熱膨
張率の順に加熱加圧接着(40Kg/cm2 ,150
℃,1時間)した以外は、上記実施例1と同様にして、
6層の導体層を有する多層回路基板を作製した。
Example 3 The polyimide adhesive used in Example 1 (UPA-83, manufactured by Ube Industries, Ltd., Young's modulus 0.6 GP)
Instead of a), the first to third double-sided copper-clad substrates having different coefficients of thermal expansion are thermally expanded using a polyimide adhesive (SPB-035A, manufactured by Nippon Steel Chemical Co., Ltd., Young's modulus: 1.7 GPa). Heat and pressure bonding (40 kg / cm 2 , 150
C., 1 hour) in the same manner as in Example 1 above.
A multilayer circuit board having six conductor layers was manufactured.

【0033】実施例1〜実施例3の多層回路基板の表裏
の熱膨張率および基板の反りを測定したところ、以下の
結果となった。その結果を、下記の表1に示す。この表
1から明らかなように、実施例1品〜実施例3品とも
に、その熱膨張率が基板の表裏で異なることが判る。し
かも、基板の反りは殆どない。ただし、実施例3品は、
基板の反りが実施例1品,実施例2品よりもやや大き
い。このように表裏で熱膨張率の異なる基板を使用すれ
ば、ベアチップ実装(1次実装)の信頼性と、マザーボ
ードへの2次実装の両方の信頼性を向上させることがで
き、CPS用シンターポーザー,MCM基板等に非常に
有効である。
The thermal expansion coefficients of the front and back surfaces of the multilayer circuit boards of Examples 1 to 3 and the warpage of the boards were measured, and the following results were obtained. The results are shown in Table 1 below. As is clear from Table 1, all of the products of Examples 1 to 3 have different thermal expansion coefficients on the front and back of the substrate. Moreover, there is almost no warpage of the substrate. However, the product of Example 3
The warpage of the substrate is slightly larger than the products of the first and second embodiments. By using substrates having different coefficients of thermal expansion on the front and back in this way, it is possible to improve the reliability of bare chip mounting (primary mounting) and the reliability of secondary mounting on a motherboard. , MCM substrate, etc.

【0034】[0034]

【表1】 [Table 1]

【0035】[0035]

【発明の効果】以上のように、本発明の多層回路基板に
よれば、そのチップ搭載面の熱膨張率を小さくし、ガラ
スエポキシ基板に接続する面の熱膨張率を大きくするこ
とにより、1次実装,2次実装ともに高い接続信頼性を
確保することができる。
As described above, according to the multilayer circuit board of the present invention, the coefficient of thermal expansion of the chip mounting surface is reduced and the coefficient of thermal expansion of the surface connected to the glass epoxy substrate is increased. High connection reliability can be ensured in both the secondary mounting and the secondary mounting.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層回路基板の構成説明図である。FIG. 1 is a diagram illustrating the configuration of a multilayer circuit board according to the present invention.

【図2】本発明の多層回路基板の一実施の形態を示す断
面図である。
FIG. 2 is a sectional view showing an embodiment of the multilayer circuit board of the present invention.

【図3】上記多層回路基板の製造工程を示す断面図であ
る。
FIG. 3 is a cross-sectional view showing a manufacturing process of the multilayer circuit board.

【図4】上記多層回路基板の製造工程を示す断面図であ
る。
FIG. 4 is a sectional view showing a manufacturing process of the multilayer circuit board.

【図5】上記多層回路基板の製造工程を示す断面図であ
る。
FIG. 5 is a cross-sectional view showing a manufacturing process of the multilayer circuit board.

【図6】上記多層回路基板の製造工程を示す断面図であ
る。
FIG. 6 is a cross-sectional view illustrating a step of manufacturing the multilayer circuit board.

【図7】上記多層回路基板の製造工程を示す断面図であ
る。
FIG. 7 is a cross-sectional view showing a step of manufacturing the multilayer circuit board.

【符号の説明】[Explanation of symbols]

1〜3 両面銅張基板 4〜6 絶縁層 10 接着剤層 11〜13 金属箔 1-3 double-sided copper-clad board 4-6 insulating layer 10 adhesive layer 11-13 metal foil

───────────────────────────────────────────────────── フロントページの続き (72)発明者 杉本 正和 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 (72)発明者 中村 圭 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 (72)発明者 桶結 卓司 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 Fターム(参考) 5E346 AA06 AA12 AA15 AA16 AA22 AA25 BB01 BB15 CC10 CC31 CC32 CC34 CC37 CC41 EE01 EE05 EE12 GG28 HH07 HH11 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Masakazu Sugimoto 1-1-2 Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation (72) Inventor Kei Nakamura 1-1-2 Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation (72) Inventor Takuji Okei 1-1-2 Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko Corporation F Term (Reference) 5E346 AA06 AA12 AA15 AA16 AA22 AA25 BB01 BB15 CC10 CC31 CC32 CC34 CC37 CC41 EE01 EE05 EE12 GG28 HH07 HH11

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 金属箔を絶縁層中に含んだ熱膨脹率の異
なる複数の両面銅張基板が、熱膨脹率の大きい順に接着
剤層を介して積層され、一体化されていること特徴とす
る多層回路基板。
1. A multilayer structure in which a plurality of double-sided copper-clad substrates each having a different coefficient of thermal expansion containing a metal foil in an insulating layer are laminated via an adhesive layer in the order of increasing coefficient of thermal expansion and integrated. Circuit board.
【請求項2】 上記両面銅張基板の熱膨張率が、絶縁層
中に含まれる金属箔の熱膨張率を変えることにより制御
されている請求項1記載の多層回路基板。
2. The multilayer circuit board according to claim 1, wherein the coefficient of thermal expansion of the double-sided copper-clad board is controlled by changing the coefficient of thermal expansion of a metal foil contained in an insulating layer.
【請求項3】 上記両面銅張基板の熱膨張率が、絶縁層
中に含まれる金属箔の厚みを変えることにより制御され
ている請求項1記載の多層回路基板。
3. The multilayer circuit board according to claim 1, wherein a coefficient of thermal expansion of the double-sided copper-clad board is controlled by changing a thickness of a metal foil included in an insulating layer.
【請求項4】 積層一体化に使用する接着剤の室温での
ヤング率が1.0GPa以下である請求項1〜3のいず
れか一項に記載の多層回路基板。
4. The multilayer circuit board according to claim 1, wherein a Young's modulus at room temperature of an adhesive used for lamination integration is 1.0 GPa or less.
【請求項5】 上記金属箔が、チタン,SUS,銅,ニ
ッケル,アルミニウム,鉄−ニッケル系合金,鉄−ニッ
ケル−コバルト系合金から選ばれた1種または2種以上
の金属で構成されている請求項1〜4のいずれか一項に
記載の多層回路基板。
5. The metal foil is made of one or more metals selected from titanium, SUS, copper, nickel, aluminum, iron-nickel alloy, and iron-nickel-cobalt alloy. The multilayer circuit board according to claim 1.
JP9317799A 1999-03-31 1999-03-31 Multilayer circuit board Pending JP2000286552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9317799A JP2000286552A (en) 1999-03-31 1999-03-31 Multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9317799A JP2000286552A (en) 1999-03-31 1999-03-31 Multilayer circuit board

Publications (1)

Publication Number Publication Date
JP2000286552A true JP2000286552A (en) 2000-10-13

Family

ID=14075305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9317799A Pending JP2000286552A (en) 1999-03-31 1999-03-31 Multilayer circuit board

Country Status (1)

Country Link
JP (1) JP2000286552A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100954488B1 (en) 2003-06-26 2010-04-22 엘지디스플레이 주식회사 A multi-layer pcb and the fabricating method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100954488B1 (en) 2003-06-26 2010-04-22 엘지디스플레이 주식회사 A multi-layer pcb and the fabricating method

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