JP2000277918A - Manufacture of printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a printed wiring board to form a filled via relatively easily on a build-up layer without increasing the cost. SOLUTION: A small diameter via-forming hole 10 is formed on the insulation layers 5, 6 of a prescribed thickness T1 in a build-up layer 4. Next, using an electroless plating bath solution, a lower plated layer is formed on the insulation layers 5, 6. Then using the electrolyte plating bath with addition of an additive having leveling effect, the lower plated layer is subjected to electrolyte panel plating. As a result, the via-forming hole 10 is filled, and the field via 9 is formed on the insulation layers 5, 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board.

[0002]

2. Description of the Related Art In recent years, many attempts have been made to produce a wiring board capable of high-density mounting by increasing the number of layers and thinning a conductor pattern. As an example thereof, a multilayer printed wiring board having a build-up layer formed through an additive process on a base substrate is known.

A build-up layer in such a multilayer printed wiring board is formed by the following procedure.
1) First, an additive adhesive for forming an insulating layer is applied on a base substrate so as to have a thickness of about several tens μm. 2) By performing exposure and development on the formed insulating layer,
A via forming hole having an inner diameter of about 100 μm to 200 μm is formed at a predetermined location. 3) After performing the roughening treatment, the catalyst nucleus provision and the activation treatment, and then performing the electroless plating,
A base plating layer is formed on the entire surface of the insulating layer. 4) Thereafter, electrolytic panel plating is performed on the base plating layer. At the same time, a via-hole formed by depositing a plating layer in the via-forming hole is formed. 5) A conductive pattern having a predetermined shape is formed by etching the plating layer deposited on the insulating layer. 6) Repeat steps 1 to 5 as necessary.

[0004] As a result, a build-up layer formed by alternately laminating insulating layers and conductor layers is formed, and a desired build-up multilayer printed wiring board is completed.

[0005]

In this type of build-up multilayer printed wiring board, there is a demand that the surface of the build-up layer be as flat as possible. This is because if the surface of the build-up layer has irregularities, the occurrence of solder voids will hinder the surface mounting of electronic components such as LSI chips and various packages. The largest cause of such unevenness is that the filling of the hole with the plating layer is incomplete and the center of the via is depressed. Therefore, it is considered that it is better to completely fill the via forming hole with the plating layer as much as possible, in other words, to form a filled via-hole.

However, conventionally, in order to form such a filled via, it is necessary to devise a method of periodically changing a voltage value of a current passed during electrolytic plating.
The setting of the conditions was extremely troublesome. Also, since a control device for periodically changing the voltage value is required,
As a result, there is also a problem that the equipment cost is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a method of manufacturing a printed wiring board in which a filled via can be relatively easily formed in a build-up layer without increasing cost. Is to provide.

[0008]

According to the first aspect of the present invention, a filled via is formed by plating on an insulating layer constituting a build-up layer provided on a base substrate. In the method for manufacturing a printed wiring board, a via hole having a small diameter is formed in the insulating layer having a predetermined thickness, and then a base plating layer is formed on the entire insulating layer using an electroless plating bath. A method for manufacturing a printed wiring board, characterized in that the via-forming holes are filled by performing electrolytic panel plating on the base plating layer using an electrolytic plating bath containing an additive having Is the gist.

According to a second aspect of the present invention, there is provided a method for manufacturing a printed wiring board in which a filled via is formed by plating on an insulating layer constituting a build-up layer provided on a base substrate. After forming a via-forming hole having an opening diameter of 50 μm or less in the insulating layer,
Forming a base plating layer on the entire insulating layer using an electroless plating bath, and then performing electrolytic panel plating on the base plating layer using an electrolytic plating bath obtained by adding an additive having a leveling action. The gist of the present invention is a method for manufacturing a printed wiring board, characterized in that the via forming holes are filled.

According to a third aspect of the present invention, in the first or second aspect, the electroless plating bath is an electroless copper plating bath, and the electrolytic plating bath is an electrolytic copper sulfate plating bath.

Hereinafter, the "action" of the present invention will be described. According to the first and second aspects of the present invention, it is presumed that as a result of reducing the diameter of the via forming hole, the via forming hole is likely to be filled by deposition of plating from the bottom surface or side surface.

[0012] In this case, it is presumed that the additive having a leveling action added to the electrolytic plating bath also functions favorably to achieve complete filling. That is, it is considered that the additive is easily adsorbed around the opening of the via forming hole. For this reason, plating deposition on the portion concerned is considerably hindered, and the deposition rate of plating becomes relatively slow. On the other hand, it is considered that the additive is unlikely to be adsorbed at the bottom of the small-diameter via forming hole, which is a recessed portion. Therefore, the deposition of the plating on the portion is not so hindered, and the deposition rate of the plating is relatively high.
As described above, as a result of the difference in plating deposition rate between the periphery of the opening of the via forming hole and the bottom, so-called leveling is achieved, and a thicker plating layer is formed at the center. Therefore, a depression is less likely to occur in the center of the plating layer, and the via obtained by this becomes a filled via.

According to the method of the present invention, it is not necessary to employ a special energizing method when performing electroplating.
Filled vias can be formed in the buildup layer relatively easily. In addition, as a result that it is not necessary to adopt a special energizing method, a control device and the like for that purpose are not required, and an increase in equipment cost can be prevented.

According to the third aspect of the present invention, since both the base plating layer and the plating layer deposited on the base plating layer are both made of copper, further increase in cost is prevented. Further, since the metals are of the same kind, they are easily compatible with each other, and a high adhesiveness is given to the interface between them, so that a highly reliable filled via can be obtained. Further, since copper has excellent conductivity, a low-resistance filled via can be obtained.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a build-up multilayer printed wiring board 1 according to an embodiment of the present invention and a method of manufacturing the same will be described in detail with reference to FIGS.

As shown in FIG. 1, a base substrate 3 constituting the build-up multilayer printed wiring board 1 has an inner conductor pattern 2 on both surfaces of a rigid insulating base material.
It is a so-called double-sided board. The inner conductor pattern 2 is formed by etching a copper foil.

On both surfaces of the base substrate 3, there are formed build-up layers 4 in which insulating layers 5, 6 and conductor layers 7, 8 are alternately laminated. Here, each of the build-up layers 4 has a two-layer structure. The first insulating layer 5 is formed on the base substrate 3, and a first conductor layer (conductor pattern) 7 is formed on an upper surface thereof. Further, the second insulating layer 6
Is formed on the first insulating layer 5, and the second
A conductor layer (component connection pad) 8 is formed. Here, the insulating layers 5 and 6 are made of epoxy resin or the like. The conductor layers 7 and 8 are made of copper, which is a metal having suitable conductivity.
In the case of the present embodiment, the thickness of the conductor patterns 7 and 8 is 1 μm.
The thickness is set to about 20 μm, preferably about 5 μm to 10 μm. The thickness of the insulating layers 5 and 6 is 20 μm to 100 μm
About 30 μm, preferably about 30 μm to 60 μm.

As shown in FIG. 1, the multilayer printed wiring board 1 has a small diameter filled via 9. The small-diameter filled via 9 is formed in the buildup layer 4, more specifically, in the insulating layers 5 and 6 constituting the buildup layer 4. These filled vias 9 form insulating layers 5,
6 is formed by filling the via forming hole 10 formed in 6 mainly with the electrolytic plating layer 11. At the interface between the electrolytic plating layer 11 and the via forming hole 10, a base plating layer (not shown) is interposed. Since this base plating layer is extremely thin as compared with the electrolytic plating layer 11, it is omitted in FIG. 1 for convenience. Via forming hole 10 provided in first insulating layer 5
Are located at positions corresponding to the interlayer connection portions 2a in the inner layer conductor pattern 2. The via-forming hole 10 provided in the second insulating layer 6 is connected to the interlayer connection portion 7a in the conductor pattern 7.
In the position corresponding to. In the case of the present embodiment, the opening diameter D1 of the via forming hole 10 is less than 100 μm, preferably less than 75 μm, and more preferably 25 μm or less.
It is set to about 50 μm.

The filled via 9 of the first insulating layer 5 connects the inner conductor pattern 2 and the conductor pattern 7 between layers.
The filled via 9 of the second insulating layer 6 connects the conductor pattern 7 and the component connection pad 8 between layers. An electronic component (not shown) is surface-mounted on the component connection pad 8 by soldering.

Next, an example of a method of manufacturing such a build-up multilayer printed wiring board 1 will be described step by step with reference to FIGS. 1) First, the base substrate 3 is manufactured by a conventional method. Here, the copper-clad laminate is used as a starting material, and the conductor patterns 2 are formed on both surfaces of the glass epoxy insulating base material by etching according to a subtractive process (see FIG. 2).

2) Next, the second layer constituting the build-up layer 4
(1) In order to form the insulating layer 5, an adhesive for forming an insulating layer is uniformly applied to both surfaces of the base substrate 3 and then dried. This adhesive is a so-called additive adhesive in which a readily soluble resin filler is dispersed in a hardly soluble epoxy resin matrix. As a result, the first insulating layer 5 having a predetermined thickness is formed.
Is formed.

3) Conductor pattern 2 in first insulating layer 5
After exposing a portion corresponding to the interlayer connection portion 2a of the base substrate 3 using an exposing machine (not shown), the base substrate 3 is charged into a developing machine to perform the development. As a result, a small-diameter via-forming hole 10 is formed at a predetermined position, and the interlayer connection portion 2a is exposed from that portion (see FIG. 3). Instead of such a photo-punching, of course, a laser-punching may be performed. When the photo method is used as described above, it is necessary to impart photosensitivity to the additive adhesive. This is not particularly necessary when the laser method is used.

4) The entire surface of the first insulating layer 5 and the entire inner wall surface of the via hole 10 are roughened by treating the base substrate 3 having undergone the drilling step with a roughening agent. By performing this treatment, a suitable roughened surface having fine anchor recesses can be obtained. In the present embodiment, the roughening agent is a chemical that dissolves easily soluble components in the additive adhesive, and refers to, for example, a solution of chromic acid, chromate, sulfuric acid, hydrochloric acid, permanganic acid, or the like. A defoaming treatment may be performed after the roughening treatment.

5) Next, a catalyst nucleus 12 such as Pd serving as a core at the time of deposition of electroless plating is applied to the entire surface of the first insulating layer 5, and then a process for activating the catalyst nucleus 12 is performed. At this time, the catalyst nuclei 12 are also applied to the side surfaces of the via-forming holes 10 and the surface of the interlayer connection portion 2a exposed at the bottom surface of the via-forming holes 10 (see FIG. 4).

6) Next, a base plating layer (base copper plating layer) is formed on the entire surface of the first insulating layer 5 by performing electroless plating. The plating at this time is so-called thin plating, and the thickness is 0.1 μm to 3.0 μm.
It is extremely thin. As the electroless plating bath, an electroless copper plating bath is preferably selected. Hereinafter, various conditions of the electroless plating set in the present embodiment will be described.

Electroless copper plating bath: Trade name (KC-50)
0, manufactured by Japan Energy Co., Ltd.) Processing temperature: 68 ° C. to 70 ° C. Processing time: 10 minutes to 40 minutes 7) After performing the above-described electroless thin plating, an additive having a leveling action is further added. Panel plating is performed using an electrolytic plating bath. As a result, the electrolytic plating layer 11 is deposited on the base plating layer. In the present embodiment, thick plating is performed using an electrolytic copper sulfate plating bath as the electrolytic plating bath. Then, through such an electrolytic plating step, an electrolytic plated layer 11 having a predetermined thickness is formed on the entire surface of the first insulating layer 5. At the same time, the electrolytic plated layer 11 is formed also in the via forming hole 10, so that the filled via 9 is formed (see FIG. 5).

Hereinafter, various conditions of the electrolytic plating set in this embodiment will be described. The bath may be agitated as needed. The bath: CuSO ₄ 60 to 100 / l, H ₂ SO ₄ 170~220g / l, NaCl
40-80 mg / liter. Additive: "Capparaside HL (trade name)" manufactured by Atotech (a mixed solution of an azo dye and a thiourea derivative, the amount in a plating bath is 20 g / liter) Processing temperature: 20 ° C to 30 ° C Processing time: 60 minutes to 120 minutes Energizing conditions: current density 1 A / dm ² , 20 μm to 30 μ
m, constant voltage 8) Next, an etching resist (not shown) is formed on the surface of the electrolytic plating layer 11 on the first insulating layer 5, and in this state, etching is performed using an etchant that can dissolve copper. As a result, the electrolytic plating layer 11 is partially dissolved and removed, and the conductor pattern 7 having a predetermined shape is formed on the first insulating layer 5 (see FIG. 6).

9) By repeating the above steps 2 to 8, the second insulating layer 6 having the filled via 9 and the pad 8 are formed, and the desired build-up multilayer printed wiring board 1 shown in FIG. 1 is completed. Let it.

[0029]

EXAMPLE Next, three types of insulating layers 5 and 6 (40
(μm, 30 μm, 60 μm), and a test for investigating the degree of filling of the via hole 10 was performed by changing the via diameter for each.

The graph of FIG. 7A shows that the insulating layers 5 and 6 are 4
It shows the degree of filling of the via-forming hole 10 when it is set to 0 μm. Similarly, the graph of FIG. 7B shows the degree of filling of the via forming hole 10 when the insulating layers 5 and 6 are set to 30 μm, and the graph of FIG. 7C shows the degree when the insulating layers 5 and 6 are set to 60 μm. Is shown. In each graph, the horizontal axis indicates the via diameter D1 (specifically, the opening diameter D1 (μm) of the via forming hole 10), and the vertical axis indicates the via plating height T (μm). In the schematic diagrams on the right side of each graph, the thickness of the insulating layers 5 and 6 is indicated by T1 (μm), and the thickness of the plating layer 11 deposited on the insulating layers 5 and 6 is indicated by T2 (μm). I have. In addition, the via diameter D1 has six steps (25 μm, 50 μm, 75 μm, 100 μm, 12 μm).
5 μm and 150 μm).

As can be seen from each graph, in the test section in which the via diameter D1 was set to 100 μm or more, the value of the plating height T of the via was only about 10 μm. That is, the via-forming hole 10 was hardly filled with the electrolytic plating layer 11, and the filled via 9 could not be obtained.

On the other hand, in the test section in which the via diameter D1 was set to 75 μm or less, the value of the plating height T of the via was 10 μm.
It was found that it was definitely larger than m. Therefore, in these test sections, the via-forming holes 10 are
1 made it easier to fill in. In particular, when the thickness T1 of the insulating layers 5 and 6 is set to 40 μm or less, by setting the via diameter D1 to 50 μm or less,
It has been found that almost complete filling is achieved.
In this case, no depression was formed in the center of the electrolytic plating layer 11, and the result was that the filled via 9 having extremely favorable properties could be reliably obtained.

Therefore, according to the present embodiment, the following effects can be obtained. (1) In the manufacturing method of the present embodiment, the diameter of the via-forming hole 10 is reduced, and electrolytic panel plating is performed thereon using an electrolytic plating bath to which an additive having a leveling action is added. Therefore, a thicker electrolytic plating layer 11 is formed at the center of the via-forming hole 10 due to the leveling action provided by the additive. Therefore, a depression is less likely to occur in the center of the electrolytic plating layer 11, and FIG.
Can be obtained.

(2) According to the manufacturing method of the present embodiment, it is not necessary to employ a special energizing method for performing the electroplating, so that the filled via 9 can be formed in the buildup layer 4 relatively easily. . In addition, as a result that it is not necessary to adopt a special energizing method, a control device and the like for that purpose are not required, and an increase in equipment cost can be prevented.

(3) According to the manufacturing method of this embodiment, the base plating layer and the electrolytic plating layer 11 deposited on the base plating layer
Since both are made of copper, the cost can be further prevented from increasing. Further, since the metals are of the same kind, they are easily compatible with each other, and a high adhesiveness is given to the interface between them, so that a highly reliable filled via 9 can be obtained. Further, since copper has excellent conductivity, a filled via 9 having low resistance can be obtained.

The embodiment of the present invention may be modified as follows. The build-up layer 4 does not have to be formed on both sides of the base substrate 3 and may be formed only on one side.
Further, it is of course possible to adopt a configuration in which the number of the build-up layers 4 is one or three or more.

The base substrate 3 is not limited to one having the conductor pattern 2 on both sides, but may be one having only one side (single-sided plate). Of course, the base substrate 3 may be a multilayer board. Further, a mere base material without the conductor pattern 2 may be used as the base substrate 3. That is, the printed wiring board embodying the present invention is not necessarily a multilayer printed wiring board.

The electrolytic plating bath used for forming the electrolytic plating layer 11 is not limited to the electrolytic plating bath containing copper as metal ions as described in the embodiment. Instead, an electrolytic plating bath containing a metal ion such as nickel, chromium, palladium, aluminum or gold can be used. Similarly, an electroless plating bath containing metal ions other than copper (nickel, chromium, palladium, aluminum, gold, etc.) can be selected for the electroless plating bath used when forming the base plating layer. It is.

Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the above-described embodiments will be listed below together with their effects. (1) A method for manufacturing a printed wiring board in which a filled via is formed by plating on an insulating layer constituting a build-up layer provided on a base substrate has a thickness of 40 μm.
After forming a via forming hole having an opening diameter of 50 μm or less in the insulating layer having a thickness of 〜60 μm, a base plating layer is formed on the entire insulating layer using an electroless plating bath, and then an additive having a leveling action is added. Using an electrolytic plating bath
A method for manufacturing a printed wiring board, wherein the via-forming holes are filled by performing electrolytic panel plating on the base plating layer. Therefore, according to the invention described in the technical idea 1, there is provided a method of manufacturing a printed wiring board that can relatively easily form a filled via having a property extremely suitable for a build-up layer without increasing cost. can do.

(2) In any one of the first to third aspects and the technical idea 1, the electrolytic panel plating is performed by applying a current having a substantially constant voltage value.
Therefore, according to the invention described in the technical idea 2, since a simple energizing method is used, a device for performing a complicated energizing method is not required.

(3) In claim 3, the electroless plating bath is for thin plating, and the electrolytic plating bath is for thick plating. (4) In any one of claims 1 to 3 and technical ideas 1 to 3, the thickness of the base plating layer is 0.1 μm.
〜3.0 μm.

(5) In the method of filling a via-forming hole formed in an insulating layer constituting a build-up layer with a plating layer, a method of forming a small-diameter via-forming hole in the insulating layer having a predetermined thickness, Forming a base plating layer on the entire insulating layer using an electroless plating bath, and then performing electrolytic panel plating on the base plating layer using an electrolytic plating bath obtained by adding an additive having a leveling action. A method for filling a via-forming hole in a build-up layer, the method comprising: Therefore, according to the invention described in the technical idea 5, it is possible to completely fill the via forming hole relatively easily without increasing the cost, and to surely obtain a filled via having no depression at the center. be able to.

[0043]

As described in detail above, according to the first aspect of the present invention, it is possible to manufacture a printed wiring board in which a filled via can be formed in a build-up layer relatively easily without increasing cost. A method can be provided.

According to the second aspect of the present invention, there is provided a method for manufacturing a printed wiring board which can relatively easily form a filled via having a property extremely suitable for a build-up layer without increasing cost. It is in.

According to the third aspect of the present invention, it is possible to prevent the cost from being further increased, and to obtain a highly reliable and low-resistance filled via.

[Brief description of the drawings]

FIG. 1 is a partial schematic cross-sectional view showing a build-up multilayer printed wiring board according to an embodiment of the present invention.

FIG. 2 is a partial schematic cross-sectional view illustrating a method for manufacturing the wiring board.

FIG. 3 is a partial schematic cross-sectional view for explaining a method of manufacturing the wiring board.

FIG. 4 is a partial schematic cross-sectional view for explaining a method of manufacturing the wiring board.

FIG. 5 is a partial schematic cross-sectional view for explaining a method of manufacturing the wiring board.

FIG. 6 is a partial schematic cross-sectional view for explaining the method of manufacturing the wiring board.

FIG. 7A is a graph showing a degree of filling of a via-forming hole when the insulating layer is set to 40 μm and a schematic diagram of a via; FIG. 7B is a diagram showing a via-forming hole when the insulating layer is set to 30 μm; And FIG. 4C is a graph showing the degree of filling of via holes and a schematic view of vias when the insulating layer is set to 60 μm.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1: Build-up multilayer printed wiring board as a printed wiring board, 3: Base board, 4: Build-up layer, 5, 6
... Insulating layer, 9 ... Filled via, 10 ... Small diameter via forming hole, 11 ... Plating layer, T1 ... Thickness (of insulating layer), D1 ... Opening diameter.

Claims (3)

[Claims] 1. A method of manufacturing a printed wiring board, wherein a filled via is formed by plating on an insulating layer constituting a build-up layer provided on a base substrate, wherein a small-diameter via is formed on the insulating layer having a predetermined thickness. After forming the holes, an underplating layer is formed on the entire insulating layer using an electroless plating bath, and then an electrolytic plating bath formed by adding an additive having a leveling action is used to perform electrolysis on the underplating layer. A method for manufacturing a printed wiring board, wherein the via-forming holes are filled by performing panel plating. 2. A method for manufacturing a printed wiring board, wherein a filled via is formed by plating on an insulating layer constituting a build-up layer provided on a base substrate, wherein the insulating layer having a thickness of 20 μm to 60 μm has an opening diameter of 50 μm.
After forming the following via forming holes, a base plating layer is formed on the entire insulating layer using an electroless plating bath, and then, using an electrolytic plating bath obtained by adding an additive having a leveling action, A method for manufacturing a printed wiring board, characterized in that the via-forming holes are filled by performing electrolytic panel plating on a base plating layer. 3. The method for manufacturing a printed wiring board according to claim 1, wherein said electroless plating bath is an electroless copper plating bath, and said electrolytic plating bath is an electrolytic copper sulfate plating bath. .