JP2000277909A - Semiconductor device and electronic device using the same - Google Patents
Semiconductor device and electronic device using the sameInfo
- Publication number
- JP2000277909A JP2000277909A JP7915199A JP7915199A JP2000277909A JP 2000277909 A JP2000277909 A JP 2000277909A JP 7915199 A JP7915199 A JP 7915199A JP 7915199 A JP7915199 A JP 7915199A JP 2000277909 A JP2000277909 A JP 2000277909A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- conductor layer
- substrate
- brazing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップ部品を載置
部材にろう材で固着する構造を有する半導体装置及びこ
れを用いた電子装置に関する。The present invention relates to a semiconductor device having a structure in which a chip component is fixed to a mounting member with a brazing material, and an electronic device using the same.
【０００２】[0002]
【従来の技術】ハイブリッドＩＣを構成する抵抗，コン
デンサ，封止型半導体素子，フリップフロップチップ等
のチップ部品は、例えば厚膜配線を設けたアルミナ基板
のような載置部材上に、融点の比較的低いろう材により
接着される。例えば、第１先行技術例としての特開昭61
−269998号公報には、Ａｇ：１〜３０ｗｔ％及びＳｂ：
０.５〜２５ｗｔ％ の１種又は２種を含有し、残部がＳ
ｎであるＳｎ合金はんだが開示されている。この場合、
酸素含有量を５ppm 以下、そして平均結晶粒径を３μｍ
に調整することによりはんだの熱疲労性を向上させてい
る。2. Description of the Related Art Chip components such as resistors, capacitors, encapsulated semiconductor elements, and flip-flop chips that constitute a hybrid IC are compared with each other on a mounting member such as an alumina substrate provided with a thick film wiring. Adhered by low brazing material. For example, as a first prior art example,
No. 269998 discloses that Ag: 1 to 30 wt% and Sb:
0.5 to 25 wt% of one or two kinds, the balance being S
An Sn alloy solder that is n is disclosed. in this case,
Oxygen content is less than 5ppm and average grain size is 3μm
The thermal fatigue resistance of the solder is improved by adjusting the temperature.
【０００３】第２先行技術例としての特開昭61−92797
号公報には、Ｓｂ：５〜１０ｗｔ％，Ｎｉ：０.５５〜
５ｗｔ％ を含み、残部がＳｎからなるＳｎ−Ｓｂ系合
金はんだが開示されている。このはんだ材では、Ｃｕ−
Ｓｎ金属間化合物の生成が抑えられるため、はんだ接続
部の接合強度や信頼性が高められる。Japanese Patent Application Laid-Open No. 61-92797 as a second prior art example
In the publication, Sb: 5 to 10 wt%, Ni: 0.55 to
A Sn—Sb alloy solder containing 5 wt% and the balance of Sn is disclosed. In this solder material, Cu-
Since the formation of the Sn intermetallic compound is suppressed, the bonding strength and reliability of the solder connection portion are improved.
【０００４】第３先行技術例としての特開昭59−189096
号公報には、Ｚｎ：５〜１５ｗｔ％，Ｂｉ：３〜２０ｗ
ｔ％を含み、残部がＳｎからなる半田合金が開示されて
いる。ここで、Ｚｎの添加により接着強度や溶融温度を
制御するとともに、Ｂｉの添加により半田の流動性や濡
れ性を改善している。Japanese Patent Laid-Open No. 59-189096 as a third prior art example
In the publication, Zn: 5 to 15 wt%, Bi: 3 to 20 w
A solder alloy containing t% and the balance Sn is disclosed. Here, the addition of Zn controls the adhesive strength and the melting temperature, and the addition of Bi improves the fluidity and wettability of the solder.
【０００５】第４先行技術例としてのK.Yamamoto らに
よる“High Reliability HybrideCircuits for Automo
tive Applications”の題する論文(ISHM'90 Proceeding
s,pp.６１０〜６１７，１９９０)には、９６％アルミナ
基板にＡｇ−Ｐｄ原膜導体を形成し、これに表面実装用
回路素子をはんだ付け搭載した自動車用ハイブリッドＩ
Ｃ装置が開示されている。本技術例のハイブリッドＩＣ
装置では、第１〜３先行技術例で開示されたＳｎを主成
分とするろう材によりチップ部品を搭載して回路形成す
ることが可能である。As a fourth prior art example, “High Reliability Hybride Circuits for Automo
tive Applications ”(ISHM'90 Proceeding
pp. 610-617, 1990) discloses a hybrid I for automobiles in which an Ag-Pd primary film conductor is formed on a 96% alumina substrate, and a surface-mounting circuit element is soldered and mounted thereon.
A C device is disclosed. Hybrid IC of this technology example
In the apparatus, it is possible to mount a chip component using a brazing material containing Sn as a main component disclosed in the first to third prior art examples to form a circuit.
【０００６】[0006]
【発明が解決しようとする課題】従来から、Ｐｂを含む
はんだ材は多くの半導体装置に用いられてきた。しか
し、環境保全の観点から、最近ではその使用を避けるア
プローチがなされている。第１〜３先行技術例で開示さ
れたＳｎを主成分とするろう材はＰｂを含有しておら
ず、上記の観点に沿った材料になり得る。第１〜３先行
技術例で開示されたＳｎを主成分とするろう材が第４先
行技術例で開示されたハイブリッドＩＣ装置に適用され
た場合は、解決しなければならない次の課題を有してい
た。その第１は、Ａｇ−Ｐｄ厚膜導体層の成分がＳｎを
主成分とする溶融ろう材中に溶解して消失し、この導体
層は本来の電気的役割やチップ部品の固定用担体として
の役割を果たし得なくなることである。これは、Ａｇと
Ｐｄの合金はＳｎを主成分とするろう材に対する溶解度
が高いことになる。Conventionally, solder materials containing Pb have been used in many semiconductor devices. However, from the viewpoint of environmental protection, approaches to avoid its use have recently been taken. The brazing material containing Sn as a main component disclosed in the first to third prior art examples does not contain Pb, and can be a material according to the above viewpoint. When the brazing material containing Sn as a main component disclosed in the first to third prior art examples is applied to the hybrid IC device disclosed in the fourth prior art example, the following problems must be solved. I was The first is that the components of the Ag-Pd thick film conductor layer dissolve and disappear in the molten brazing material containing Sn as a main component, and this conductor layer serves as its original electric role and as a carrier for fixing chip components. It will not be able to play a role. This means that the alloy of Ag and Pd has a high solubility in the brazing material containing Sn as a main component.
【０００７】また、Ａｇ−Ｐｄ膜厚導体層が完全に消失
しない場合でも、高温の稼働条件のもとにさらされた場
合は、Ｓｎを主成分とするろう材とＡｇ−Ｐｄ厚膜導体
との固相拡散が促進され、Ａｇ−Ｐｄ厚膜導体層はＡ
ｇ，Ｐｄ及びＳｎを主成分とする合金ないし金属間化合
物に変化する。このような合金ないし金属間化合物は、
それ自体脆く、アルミナ等のセラミックス基板との接合
力も弱い。この結果、固着されていたチップ部品が基板
から剥離して、所期の回路機能を維持できなくなる。こ
れが第２の問題がある。[0007] Even when the Ag-Pd thick conductor layer does not completely disappear, when exposed under high-temperature operating conditions, the brazing material containing Sn as a main component and the Ag-Pd thick-film conductor are removed. Is promoted, and the Ag-Pd thick conductor layer
It changes to an alloy or intermetallic compound containing g, Pd and Sn as main components. Such alloys or intermetallic compounds are
The material itself is brittle and has low bonding strength with ceramic substrates such as alumina. As a result, the fixed chip components are separated from the substrate, and the desired circuit function cannot be maintained. This has a second problem.
【０００８】本発明の目的は上述の問題点を解決し、チ
ップ部品を載置部材にろう付けして固着する際の過剰な
界面反応を抑制し、制造時あるいは運転時の熱的及び機
械的変化によるろう付け部の破損を防止し、製造歩留り
や信頼性の高い半導体装置とこれを用いた電子装置を提
供することである。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to suppress an excessive interfacial reaction when a chip component is brazed to a mounting member, and to reduce thermal and mechanical problems during fabrication or operation. An object of the present invention is to provide a semiconductor device which prevents breakage of a brazed portion due to a change and has a high production yield and high reliability, and an electronic device using the same.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成する本発
明の半導体装置は、チップ部品がセラミックスからなる
載置部材上に、Ｓｎからなるろう材又はＳｎ，Ｓｂ，Ａ
ｇ，Ｃｕ，Ｎｉ，Ｐ，Ｂｉ，Ｚｎ，ＡｕそしてＩｎの群
から選択された２種以上の物質からなるろう材により固
着され、該載置部材の該固着部にＰｔを含む厚膜導体層
が設けられていることを特徴とする。In order to achieve the above object, a semiconductor device according to the present invention has a soldering member made of Sn or Sn, Sb, A on a mounting member whose chip component is made of ceramics.
g, Cu, Ni, P, Bi, Zn, Au, and a thick film conductor layer fixed by a brazing material made of at least two kinds of substances selected from the group of In and including Pt in the fixing portion of the mounting member. Is provided.
【００１０】本発明半導体装置を用いた電子装置は、チ
ップ部品がセラミックスからなる載置部材上に、Ｓｎか
らなるろう材又はＳｎ，Ｓｂ，Ａｇ，Ｃｕ，Ｎｉ，Ｐ，
Ｂｉ，Ｚｎ，ＡｕそしてＩｎの群から選択された２種以
上の物質からなるろう材により固着され、該載置部材の
該固着部にＰｔを含む厚膜導体層が設けられている半導
体装置が、負荷に給電する回路に組み込まれたことを特
徴とする。In an electronic device using the semiconductor device of the present invention, a brazing material made of Sn or Sn, Sb, Ag, Cu, Ni, P,
A semiconductor device is fixed by a brazing material made of two or more kinds of substances selected from the group consisting of Bi, Zn, Au and In, and a thick film conductor layer containing Pt is provided at the fixing portion of the mounting member. , Incorporated in a circuit for supplying power to the load.
【００１１】[0011]
【発明の実施の形態】本発明半導体装置３０は、図１に
示す鳥瞰図及び断面図のような形態を有している。先
ず、（ａ）の鳥瞰図に注目する。Ｓｉからなるパワー半
導体基体としてのＩＧＢＴ（Insulated Gate Bipolar T
ransistor)チップ１は、厚さ：１mmのＣｕベース板２上
にろう材３（図示を省略）により固着されている。この
際、ろう付けは還元雰囲気中で２７０℃程度に加熱して
なされる。Ｃｕベース板２の表面には、Ｎｉめっき（図
示を省略、厚さ：３〜７μｍ）が施されている。また、
Ｃｕベース板２上には、配線層としての厚膜Ａｇ−Ｐｔ
導体（図示を省略）４を施した載置部材としてのアルミ
ナセラミックス基板５がシリコーン樹脂接着剤（図示を
省略）６により取り付けられている。アルミナ基板５の
厚膜Ａｇ−Ｐｔ導体４間には、厚膜抵抗１１，ＩＣチッ
プ基板１２，コンデンサチップ１３、そしてガラススリ
ーブ型ツェナーダイオードチップ１４等のチップ部品が
ろう材３′（図示を省略）により固着されており、ＩＧ
ＢＴチップ１を制御する回路１０が形成されている。Ｉ
ＧＢＴチップ１のエミッタ電極及びゲート電極は直径３
００μｍのＡｌワイヤ６により制御回路１０と電気的に
連絡されている。IGBTチップ１のコレクタ電極は、Ｃｕ
ベース板２とＡｌワイヤ６′を経由して端子７と電気的
に接続されている。制御回路１０もＡｌワイヤ６′によ
り端子７と電気的に連絡されている。端子７はＣｕベー
ス板２と同質の材料からなり、その表面にはＮｉめっき
（図示を省略、厚さ：３〜７μｍ）が施されている。載
置部材の母材がＣｕ材である場合は母材が表面に露出し
た状態であっても良いが、より高い品質を保持する上で
Ｎｉ，Ａｕ，Ａｇ等のめっきを施すことが望ましい。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device 30 of the present invention has a form as shown in a bird's-eye view and a sectional view shown in FIG. First, look at the bird's-eye view of (a). IGBT (Insulated Gate Bipolar T) as a power semiconductor substrate made of Si
A ransistor chip 1 is fixed on a Cu base plate 2 having a thickness of 1 mm with a brazing material 3 (not shown). At this time, brazing is performed by heating to about 270 ° C. in a reducing atmosphere. The surface of the Cu base plate 2 is plated with Ni (not shown, thickness: 3 to 7 μm). Also,
On the Cu base plate 2, a thick film Ag-Pt as a wiring layer
An alumina ceramics substrate 5 as a mounting member provided with a conductor (not shown) 4 is attached by a silicone resin adhesive (not shown) 6. Chip components such as a thick film resistor 11, an IC chip substrate 12, a capacitor chip 13, and a glass sleeve type Zener diode chip 14 are provided between the thick film Ag-Pt conductor 4 of the alumina substrate 5 by a brazing material 3 '(not shown). ) And IG
A circuit 10 for controlling the BT chip 1 is formed. I
The emitter electrode and the gate electrode of the GBT chip 1 have a diameter of 3
It is electrically connected to the control circuit 10 by the Al wire 6 of 00 μm. The collector electrode of the IGBT chip 1 is Cu
It is electrically connected to the terminal 7 via the base plate 2 and the Al wire 6 '. The control circuit 10 is also electrically connected to the terminal 7 by the Al wire 6 '. The terminal 7 is made of the same material as the Cu base plate 2, and its surface is plated with Ni (not shown, thickness: 3 to 7 μm). When the base material of the mounting member is a Cu material, the base material may be exposed on the surface, but it is preferable to perform plating of Ni, Au, Ag, or the like to maintain higher quality.
【００１２】以上の概略構造を有するアッセンブリは、
（ｂ）に示す断面図の破線で示すように、ＩＧＢＴチッ
プ１の搭載部，チップ部品が取り付けられたアルミナ基
板５の搭載部、Ａｌワイヤ６及び６′が完全に封止され
る如くに、Ｃｕベース板２及び端子７の一部を含めてエ
ポキシ樹脂８によるモールドが施されている。An assembly having the above general structure is as follows.
As shown by the broken line in the cross-sectional view shown in (b), the mounting portion of the IGBT chip 1, the mounting portion of the alumina substrate 5 to which the chip components are attached, and the Al wires 6 and 6 'are completely sealed. The mold including the Cu base plate 2 and a part of the terminal 7 is molded with the epoxy resin 8.
【００１３】図２はチップ部品搭載部の断面構造模式図
である。載置部材としてのアルミナ基板５の一方の主面
に厚膜Ａｇ−Ｐｔ導体４が設けられている。導体層４
は、アルミナ基板５上に最終的に組成がＡｇ−１ｗｔ％
Ｐｔとなる金属成分を含有するペースト組成物を印刷
し、これらを９００℃で空気中焼成することにより得ら
れる。次いで、厚膜抵抗１１は抵抗ペースト組成物を印
刷した後、９００℃で空気中焼成することにより得られ
る。更に、必要ならば、導体層４や厚膜抵抗１１を保護
するためのオーバコートガラス層（図示省略）を設けて
もよい。導体層４の所望部に組成Ｓｎ−３ｗｔ％Ａｇ−
０.８ｗｔ％Ｃｕ なる合金粉末を含有するはんだペース
ト組成物を印刷した後、その印刷部にＩＣチップ基体１
２，コンデンサチップ１３、そしてガラススリーブ型ツ
ェナーダイオードチップ１４等のチップ部品をセット
し、２５０±１０℃に加熱してチップ部品を固着する。
ここで、上記はんだペースト組成物は、最終的にはろう
材３′となる。また、厚膜抵抗１１には必要に応じてレ
ーザトリミングによる抵抗値調整が施される。ＩＧＢＴ
チップ１の制御回路１０は、以上のようにして形成され
る。FIG. 2 is a schematic sectional view of a chip component mounting portion. Thick film Ag-Pt conductor 4 is provided on one main surface of alumina substrate 5 as a mounting member. Conductor layer 4
Means that the composition is finally Ag-1 wt% on the alumina substrate 5
It is obtained by printing a paste composition containing a metal component to be Pt, and firing these at 900 ° C. in the air. Next, the thick film resistor 11 is obtained by printing the resistor paste composition and firing at 900 ° C. in the air. Further, if necessary, an overcoat glass layer (not shown) for protecting the conductor layer 4 and the thick film resistor 11 may be provided. A desired portion of the conductor layer 4 has a composition of Sn-3 wt% Ag-
After printing a solder paste composition containing an alloy powder of 0.8 wt% Cu, the IC chip substrate 1 is printed on the printed portion.
2. A chip component such as a capacitor chip 13 and a glass sleeve type Zener diode chip 14 is set, and heated to 250 ± 10 ° C. to fix the chip component.
Here, the solder paste composition finally becomes the brazing material 3 '. The resistance of the thick film resistor 11 is adjusted by laser trimming as necessary. IGBT
The control circuit 10 of the chip 1 is formed as described above.
【００１４】図３は溶融したろう材槽中にディップした
場合の厚膜Ａｇ−Ｐｔ導体層の残留厚さを示すグラフで
ある。検討に用いた厚膜Ａｇ−Ｐｔ導体層４の初期厚さ
は１２±１μｍ、ろう材はＳｎ−３.５ｗｔ％Ｓｂ ，Ｓ
ｎ及びＳｎ−５ｗｔ％Ｓｂの３種類、そしてディップ条
件は２６０℃×２min である。Ｐｔを含有しない厚膜Ａ
ｇ導体層の場合は、２分間のディップで厚さ１〜２μｍ
の導体層しか残らず、約１０μｍ分の導体層はろう材中
に溶解して消失する。Ｐｔ濃度を増すとろう材中に溶
解，消失する量が少なくなり、残留部は厚くなる。この
傾向は、Ｐｔ濃度約１ｗｔ％までの範囲で顕著である。
Ｐｔ濃度約１ｗｔ％以上では、溶解及び消失する量は極
めて少なくなり、初期厚さ（１２±１μｍ）と極めて近
似した厚さが確保される。FIG. 3 is a graph showing the residual thickness of the thick Ag-Pt conductor layer when dipped in a molten brazing material bath. The initial thickness of the thick Ag—Pt conductor layer 4 used for the study was 12 ± 1 μm, and the brazing material was Sn-3.5 wt% Sb, S
n and Sn-5 wt% Sb, and the dipping conditions are 260 ° C. × 2 min. Thick film A containing no Pt
g In the case of a conductor layer, the thickness is 1-2 μm by dipping for 2 minutes.
Only the conductor layer of about 10 μm dissolves in the brazing material and disappears. When the Pt concentration is increased, the amount of dissolution and disappearance in the brazing filler metal decreases, and the remaining portion becomes thick. This tendency is remarkable up to a Pt concentration of about 1 wt%.
At a Pt concentration of about 1 wt% or more, the amount of dissolution and disappearance is extremely small, and a thickness very similar to the initial thickness (12 ± 1 μm) is secured.
【００１５】ろう材としてＳｎ−３.５ｗｔ％Ａｇ，Ｓ
ｎ−３ｗｔ％Ａｇ−０.８ｗｔ％Ｃｕで代表されるよう
な他のＳｎ−Ａｇ系，Ｓｎ−５ｗｔ％Ｓｂ−０.６ｗｔ
％Ｎｉ−０.０５ｗｔ％Ｐ で代表されるような他のＳｎ
−Ｓｂ系，Ｓｎ−５８ｗｔ％Ｂｉで代表されるようなＳ
ｎ−Ｂｉ系，Ｓｎ−０.７ｗｔ％Ｃｕ で代表されるよう
なＳｎ−Ｃｕ系，Ｓｎ−５２ｗｔ％Ｉｎで代表されるよ
うなＳｎ−Ｉｎ系，Ｓｎ−９ｗｔ％Ｚｎで代表されるよ
うなＳｎ−Ｚｎ系，Ｉｎ−１０ｗｔ％Ａｇで代表される
ようなＩｎ−Ａｇ系、そして、Ａｕ−２０ｗｔ％Ｓｎで
代表されるようなＡｕ−Ｓｎ系に置き換えても、残留厚
さは図３と同様の傾向を示す。ここで、初期厚さの１２
±１μｍは、チップ部品をろう付け搭載した後の導体層
４の厚さを１０μｍ以上に確保することを目的に設定さ
れたものである。As a brazing material, Sn-3.5 wt% Ag, S
Other Sn-Ag series represented by n-3 wt% Ag-0.8 wt% Cu, Sn-5 wt% Sb-0.6 wt
% Ni-0.05 wt% P.
-Sb, S-type represented by Sn-58wt% Bi
n-Bi type, Sn-Cu type typified by Sn-0.7 wt% Cu, Sn-In type typified by Sn-52 wt% In, and typified by Sn-9 wt% Zn Even if it is replaced with an Sn-Zn system, an In-Ag system represented by In-10wt% Ag, and an Au-Sn system represented by Au-20wt% Sn, the residual thickness is as shown in FIG. It shows a similar tendency. Here, the initial thickness of 12
The value of ± 1 μm is set for the purpose of securing the thickness of the conductor layer 4 after soldering and mounting the chip component to 10 μm or more.
【００１６】図３の結果から、残留厚さ１０μｍ以上が
確保されるのはＰｔ濃度０.８wt％以上の範囲であり、
この観点で選択される好ましい組成は０.８ｗｔ％Ｐｔ
以上であることが確認される。From the results shown in FIG. 3, the Pt concentration of 0.8 wt% or more ensures that the residual thickness is 10 μm or more.
A preferred composition selected from this viewpoint is 0.8 wt% Pt.
This is confirmed.
【００１７】図４は厚膜Ａｇ−Ｐｔ導体層のシート抵抗
を示すグラフである。厚膜Ａｇ−Ｐｔ導体層４の初期厚
さは１２±１μｍに調整されている。シート抵抗はＰｔ
濃度が０ｗｔ％（Ａｇ導体）の場合約１.５ｍΩ／□ で
あり、Ｐｔ濃度を増すにつれて増加する。Ｐｔ濃度が極
端に高い領域では、シート抵抗も急峻に増大する。厚膜
Ａｇ−Ｐｔ配線層４はできるだけ抵抗の低いこと、そし
てＰｂ濃度の多少の変動があっても安定的に低い抵抗値
が得られることが望ましい。このような観点で選択され
るＰｂ濃度は、図４から５ｗｔ％以下の範囲であること
が認められる。FIG. 4 is a graph showing the sheet resistance of the thick Ag-Pt conductor layer. The initial thickness of the thick film Ag-Pt conductor layer 4 is adjusted to 12 ± 1 μm. Sheet resistance is Pt
When the concentration is 0 wt% (Ag conductor), it is about 1.5 mΩ / □, and increases as the Pt concentration increases. In the region where the Pt concentration is extremely high, the sheet resistance also increases sharply. It is desirable that the thick film Ag-Pt wiring layer 4 has a resistance as low as possible and that a stable low resistance value is obtained even if the Pb concentration slightly varies. It is recognized from FIG. 4 that the Pb concentration selected from such a viewpoint is in a range of 5 wt% or less.
【００１８】図５はチップ部品を搭載したろう付け部の
金属のデプスプロファイルを示すグラフである。この分
析はＳＩＭＳ（Secondary Ion Mass Spectroscopy)によ
るものである。図中のＡｌはアルミナ基板、Ａｇ，Ｐ
ｔ，Ｐｄは導体層、そしてＳｎはろう材をそれぞれ代表
した成分である。また、試料はチップ部品を２４０℃で
ろう付けした後、１７５℃で１０００ｈの高温放置試験
したものである。ろう付け直後の導体層厚さは、Ａｇ−
１ｗｔ％Ｐｔ導体の場合は１２μｍ、そして比較例とし
てのＡｇ−２０ｗｔ％Ｐｄ導体の場合は６.５μｍ であ
った。FIG. 5 is a graph showing a metal depth profile of a brazing portion on which chip components are mounted. This analysis is based on SIMS (Secondary Ion Mass Spectroscopy). Al in the figure is an alumina substrate, Ag, P
t and Pd are components representative of the conductor layer, and Sn is a component representative of the brazing material. The sample was obtained by brazing the chip component at 240 ° C. and then performing a high-temperature storage test at 175 ° C. for 1000 hours. The thickness of the conductor layer immediately after brazing is Ag-
In the case of a 1 wt% Pt conductor, it was 12 μm, and in the case of an Ag-20 wt% Pd conductor as a comparative example, it was 6.5 μm.
【００１９】先ず、Ａｇ−１ｗｔ％Ｐｔ導体の場合に注
目する。導体層４としてのＡｇやＰｔのプロファイルに
は、高温放置試験によってＳｎと相互作用を生じた形跡
は認められない。また、ＳｎはＡｇやＰｔの領域に深く
侵入してもいない。これは、Ａｇ−Ｐｔ合金はＳｎの侵
入あるいはＳｎとの相互反応に対する耐力に優れ、Ｓｎ
との合金化を抑えることを示唆する。これに対しＡｇ−
２０ｗｔ％Ｐｄ導体の場合は、ＡｇやＰｄはイオン強度
が小さく、基板５上に層状をなして存在していない。Ｓ
ｎもＡｇやＰｄの領域に深く侵入し、基板５の近くまで
到達している。これは、Ａｇ−２０ｗｔ％Ｐｄ導体の場
合はろう付け後に導体層が残っていても、高温放置試験
によってＳｎとＡｇ−Ｐｄ合金との相互反応が進行し、
導体層としての形態を失ってしまうことを示唆する。First, attention is paid to the case of an Ag-1 wt% Pt conductor. In the profile of Ag or Pt as the conductor layer 4, there is no evidence of interaction with Sn in the high-temperature storage test. Also, Sn does not penetrate deep into Ag or Pt regions. This is because the Ag—Pt alloy has excellent resistance to penetration of Sn or mutual reaction with Sn.
It suggests that alloying with is suppressed. Ag-
In the case of a 20 wt% Pd conductor, Ag and Pd have low ionic strength and do not exist in a layer on the substrate 5. S
n also penetrates deeply into the Ag or Pd region and reaches near the substrate 5. This is because in the case of an Ag-20 wt% Pd conductor, even if the conductor layer remains after brazing, the interaction between Sn and the Ag-Pd alloy proceeds by a high-temperature storage test,
It suggests that the form as a conductor layer is lost.
【００２０】以上より、Ａｇ−１ｗｔ％Ｐｔ導体４はＳ
ｎを多量に含むろう材３′と接した状態で高温にさらさ
れても、相互の反応を僅少に抑えることができる。以上
に述べた高温放置試験における傾向は、ろう材３′が上
記した種々のろう材に置き換えられても変わらない。As described above, the Ag-1 wt% Pt conductor 4 is made of S
Even when exposed to a high temperature in contact with the brazing filler metal 3 'containing a large amount of n, mutual reaction can be suppressed to a small extent. The tendency in the high-temperature storage test described above does not change even if the brazing material 3 'is replaced with the various brazing materials described above.
【００２１】ＩＧＢＴチップ１や制御回路１０等を封止
するモールド用エポキシ樹脂８は、フィラーとしてＳｉ
Ｏ2(溶融シリカ，結晶シリカ）やＺｎＯ粉末を添加した
フェノール硬化型エポキシ樹脂が用いられる。この場
合、フィラーの添加量は所望の熱膨張率及びモールド処
理温度に応じて５０〜９０％の範囲の任意の組成を選ぶ
ことが可能である。また、ゴム変性エポキシ樹脂を用い
てもよい。これらの樹脂は、生産性，経済性の観点から
トランスファモールド法によることが望ましい。しか
し、所望の耐水性，電気性能，信頼性等を満たす範囲で
は、ポッティング法により封止することも可能である。The molding epoxy resin 8 for sealing the IGBT chip 1 and the control circuit 10 is made of Si as a filler.
A phenol-curable epoxy resin to which O 2 (fused silica, crystalline silica) or ZnO powder is added is used. In this case, it is possible to select an arbitrary composition of the filler in the range of 50 to 90% depending on the desired coefficient of thermal expansion and the mold processing temperature. Further, a rubber-modified epoxy resin may be used. These resins are desirably formed by a transfer molding method from the viewpoint of productivity and economy. However, as long as desired water resistance, electrical performance, reliability, and the like are satisfied, sealing can be performed by a potting method.
【００２２】以上の構成を、図面を用いて説明する。The above configuration will be described with reference to the drawings.
【００２３】〔実施例１〕本実施例では、パワー半導体
素子基体とその電気的動作を制御する制御回路を搭載し
た半導体装置及びこの半導体装置を用いた自動車用点火
装置について説明する。[Embodiment 1] In this embodiment, a semiconductor device equipped with a power semiconductor element base and a control circuit for controlling the electrical operation thereof, and an automobile ignition device using this semiconductor device will be described.
【００２４】パワー半導体素子基体１とその電気的動作
を制御する制御回路１０を搭載した半導体装置３０は、
図１に示す鳥瞰図構造及び断面構造を有している。Ｓｉ
からなるＩＧＢＴチップ基体１(チップサイズ：５×５
×０.２５mm）は、厚さ１mm，面積約２５×２０mmのＣ
ｕベース板２上に組成Ｓｎ−５ｗｔ％Ｓｂ−０.６wt％
Ｎｉ−０.０５ｗｔ％Ｐ のろう材３（図示を省略）によ
り固着されている。Ｃｕベース板２の表面には厚さ３〜
７μｍのＮｉめっき（図示を省略）が施されている。こ
の際、ろう付けは厚さ２００μｍ，サイズ５×５mmのシ
ート状上記ろう材３をチップ基体１とベース板２の間に
積層し、この積層体を水素添加の窒素雰囲気中で２７０
±１０℃に加熱することにより実施した。The semiconductor device 30 on which the power semiconductor element substrate 1 and the control circuit 10 for controlling its electric operation are mounted
It has the bird's-eye view structure and the cross-sectional structure shown in FIG. Si
IGBT chip base 1 (chip size: 5 × 5
× 0.25mm) is a C with a thickness of 1mm and an area of about 25 × 20mm.
Composition Sn-5 wt% Sb-0.6 wt% on u base plate 2
It is fixed with a brazing material 3 (not shown) of Ni-0.05 wt% P. The thickness of the Cu base plate 2 is 3 to
7 μm Ni plating (not shown) is applied. At this time, the brazing material 3 having a thickness of 200 μm and a size of 5 × 5 mm is laminated between the chip base 1 and the base plate 2, and the laminated body is subjected to 270 μm in a hydrogen-added nitrogen atmosphere.
Performed by heating to ± 10 ° C.
【００２５】一方、厚さ約１２μｍの厚膜Ａｇ−１ｗｔ
％Ｐｔ導体層（図示を省略、シート抵抗：１５ｍΩ／
□）４，厚膜抵抗１１及びオーバコートガラス層(図示
を省略)を設けた、サイズ：１９×１０×０.８mm の載
置部材としてのアルミナセラミックス基板５を用意し
た。次いで、アルミナ基板５の所望領域に、最終的にろ
う材３′となる組成Ｓｎ−３ｗｔ％Ａｇ−０.８ｗｔ％
Ｃｕ のろう材粉末を含有したペーストを印刷し、この
印刷部にＩＣチップ基体１２，コンデンサチップ１３、
そしてガラススリーブ型ツェナーダイオードチップ１４
等のチップ部品を搭載し、空気中で２５０±１０℃に加
熱した。これにより、各チップ部品１２，１３，１４や
厚膜抵抗１１はろう材３′により厚膜Ａｇ−１ｗｔ％Ｐ
ｔ導体層４と電気的に接続され、アルミナ基板５上には
ＩＧＢＴチップ基体１の動作を制御するための制御回路
１０が形成された。On the other hand, a thick film Ag-1wt having a thickness of about 12 μm
% Pt conductor layer (not shown, sheet resistance: 15 mΩ /
□) An alumina ceramic substrate 5 as a mounting member having a size of 19 × 10 × 0.8 mm provided with 4, a thick film resistor 11 and an overcoat glass layer (not shown) was prepared. Next, in a desired region of the alumina substrate 5, a composition Sn-3wt% Ag-0.8wt% which finally becomes the brazing material 3 'is formed.
A paste containing a brazing filler metal powder of Cu is printed, and an IC chip substrate 12, a capacitor chip 13,
And the glass sleeve type Zener diode chip 14
And the like, and heated to 250 ± 10 ° C. in air. As a result, each of the chip components 12, 13, and 14 and the thick film resistor 11 are made of a thick film Ag-1 wt% P by the brazing material 3 '.
A control circuit 10 for electrically controlling the operation of the IGBT chip base 1 was formed on the alumina substrate 5 and electrically connected to the t conductor layer 4.
【００２６】ろう付け後のＡｇ−１ｗｔ％Ｐｔ導体層４
は、１１.５μｍ の厚さが確保されている。このアルミ
ナ基板５はシリコーン樹脂接着剤（図示を省略）９によ
り、Ｃｕベース板２上に取り付けられている。ＩＧＢＴ
チップ１のエミッタ電極及びゲート電極は直径３００μ
ｍのＡｌワイヤ６により制御回路１０と電気的に連絡さ
れている。ＩＧＢＴチップ１のコレクタ電極は、Ｃｕベ
ース板２とＡｌワイヤ６′を経由して端子７と電気的に
連絡されている。制御回路１０もＡｌワイヤ６′により
端子７と電気的に連絡されている。端子７はＣｕベース
板２と同質の材料からなり、その表面にはＮｉめっき
（図示を省略，厚さ：３〜７μｍ）が施されている。Ag-1 wt% Pt conductor layer 4 after brazing
Has a thickness of 11.5 μm. The alumina substrate 5 is mounted on the Cu base plate 2 with a silicone resin adhesive (not shown) 9. IGBT
The emitter electrode and gate electrode of chip 1 have a diameter of 300 μm.
It is electrically connected to the control circuit 10 by m Al wires 6. The collector electrode of the IGBT chip 1 is electrically connected to the terminal 7 via the Cu base plate 2 and the Al wire 6 '. The control circuit 10 is also electrically connected to the terminal 7 by the Al wire 6 '. The terminal 7 is made of the same material as the Cu base plate 2, and its surface is plated with Ni (not shown, thickness: 3 to 7 μm).
【００２７】以上の概略構造を有するアッセンブリは、
（ｂ）に示す断面図の破線で示すように、ＩＧＢＴチッ
プ１の搭載部、チップ部品が取り付けられたアルミナ基
板５の搭載部、Ａｌワイヤ６及び６′が完全に封止され
る如くに、Ｃｕベース板２及び端子７の一部を含めてエ
ポキシ樹脂８によるトランスファモールドが施されてい
る。エポキシ樹脂８は熱膨張率：１６ppm／℃ ，ガラス
転移点：１５５℃，体積抵抗率：９×１０15Ω・ｍ（Ｒ
Ｔ），曲げ強度：３×１０15kgｆ／mm2 ，曲げ弾性率：
１６００kgｆ／mm2 なる特性を有している。トランスフ
ァモールドは１８０℃のもとで実施し、次いで１５０℃
のもとで２ｈの熱処理を施して樹脂の硬化を促進させ
た。The assembly having the above general structure is as follows.
As shown by the broken line in the cross-sectional view shown in (b), the mounting portion of the IGBT chip 1, the mounting portion of the alumina substrate 5 to which the chip components are attached, and the Al wires 6 and 6 'are completely sealed. The transfer molding using the epoxy resin 8 including the Cu base plate 2 and a part of the terminal 7 is performed. The epoxy resin 8 has a thermal expansion coefficient of 16 ppm / ° C., a glass transition point of 155 ° C., and a volume resistivity of 9 × 10 15 Ω · m (R
T), flexural strength: 3 × 10 15 kgf / mm 2 , flexural modulus:
It has a characteristic of 1600 kgf / mm 2 . Transfer mold is performed at 180 ° C, then at 150 ° C
Under a heat treatment for 2 hours to accelerate the curing of the resin.
【００２８】以上のようにして製作された本実施例半導
体装置３０は、不良発生率が0.001％以下であった。こ
のように低い不良率が得られたのには、ろう付けによる
導体層４の溶解及び消失が抑制され、チップ部品搭載部
の電気的接続が確実になされたことが寄与している。一
方、Ａｇ−２０ｗｔ％Ｐｄ導体を形成した載置部材とし
ての基板にチップ部品を搭載した比較例半導体装置で
は、不良発生率は約１％であった。この主要な原因は、
ろう付けによる導体層の溶解及び消失が促進されたた
め、チップ部品搭載部の電気的接続が不十分であったこ
とによる。The semiconductor device 30 of the present embodiment manufactured as described above had a failure rate of 0.001% or less. The reason why such a low defect rate is obtained is that melting and disappearance of the conductor layer 4 due to brazing are suppressed, and the electrical connection of the chip component mounting portion is reliably performed. On the other hand, in the comparative example semiconductor device in which the chip component was mounted on the substrate as the mounting member on which the Ag-20 wt% Pd conductor was formed, the defect occurrence rate was about 1%. The main cause of this is
This is because melting and disappearance of the conductor layer due to brazing were promoted, and the electrical connection of the chip component mounting portion was insufficient.
【００２９】図６は温度サイクル試験によるコンデンサ
チップろう付け部のインピーダンスの推移を示すグラフ
である。図中の曲線Ａは本実施例半導体装置３０、そし
て、曲線Ｂは比較用半導体装置（Ａｇ−２０ｗｔ％Ｐｄ
導体を形成した基板５にチップ部品を搭載）に関するも
のである。ここで、インピーダンスはコンデンサチップ
１３のろう付け部３′を含む配線４間での値である。し
たがって、ろう付け部にクラック等の破壊を生ずると、
見かけのインピーダンスは増大する。本実施例半導体装
置３０の場合は、インピーダンスは温度サイクル数：５
０００回までの試験で初期値と等価な値に維持されてい
る。５０００回終了後のろう付け部の断面を調べたが、
導体層４の厚さは１１.５μｍ とろう付け直後の値と同
等であった。また、ろう付け部３′及び導体層４のいず
れにもクラック等の破壊は見られなかった。FIG. 6 is a graph showing the transition of the impedance of the capacitor chip brazing part by the temperature cycle test. A curve A in the figure is a semiconductor device 30 of the present example, and a curve B is a semiconductor device for comparison (Ag-20 wt% Pd).
(A chip component is mounted on a substrate 5 on which a conductor is formed). Here, the impedance is a value between the wires 4 including the brazing portion 3 ′ of the capacitor chip 13. Therefore, if breakage such as cracks occurs in the brazed part,
The apparent impedance increases. In the case of the semiconductor device 30 of the present embodiment, the impedance is the number of temperature cycles: 5
It is maintained at a value equivalent to the initial value in up to 000 tests. After examining the cross section of the brazed part after 5,000 times,
The thickness of the conductor layer 4 was 11.5 μm, which was equivalent to the value immediately after brazing. In addition, no breakage such as a crack was found in any of the brazed portion 3 'and the conductor layer 4.
【００３０】以上のように、本実施例半導体装置３０は
優れた信頼性が確保されていることが確認される。一
方、比較用半導体装置の場合には、温度サイクル数：３
０回を過ぎるとインピーダンスの上昇を生じている。こ
のことは、導電性を阻害する破壊がろう付け部あるいは
導体層のいずれかに生じたことを意味する。温度サイク
ル数：５００回終了後の比較用導体装置を分解し、ろう
付け部の断面を調べた。この結果、基板５上にわずかに
残っていた導体層とろう材層とが基板５から剥離してい
いた。この状況から、インピーダンスの上昇は導体層の
クラックによるものと推定される。As described above, it is confirmed that the semiconductor device 30 of this embodiment has excellent reliability. On the other hand, in the case of the comparative semiconductor device, the number of temperature cycles: 3
After 0 times, the impedance rises. This means that the destruction that hindered the conductivity occurred in either the brazed portion or the conductor layer. Number of temperature cycles: The comparative conductor device after 500 cycles was disassembled, and the cross section of the brazed portion was examined. As a result, the conductor layer and the brazing material layer slightly remaining on the substrate 5 were peeled off from the substrate 5. From this situation, it is assumed that the increase in impedance is due to cracks in the conductor layer.
【００３１】また、上述した本実施例半導体装置３０及
び比較用半導体装置におけるコンデンサチップ１３のろ
う付け部のせん断強度を比較した。せん断強度は本実施
例半導体装置３０の場合３.５kg であるのに対し、比較
用半導体装置の場合は１.３と、大きな相違が観測され
た。この試験による破壊は、本実施例半導体装置３０の
場合はろう材３′の領域で生じていたのに対し、比較用
半導体装置の場合はアルミナ基板とろう材の界面で生じ
ていた。The shear strength of the brazed portion of the capacitor chip 13 in the semiconductor device 30 of the present embodiment and the comparative semiconductor device was compared. The shear strength was 3.5 kg in the case of the semiconductor device 30 of the present example, whereas it was 1.3 in the case of the semiconductor device for comparison, a large difference was observed. Destruction by this test occurred in the region of the brazing material 3 'in the case of the semiconductor device 30 of the present example, whereas it occurred at the interface between the alumina substrate and the brazing material in the case of the comparative semiconductor device.
【００３２】図７は本実施例半導体装置３０の回転を説
明する図である。ＩＧＢＴ素子１のエミッタ及びゲート
は制御回路１０と電気的に接続され、素子１の動作はこ
の回路１０により制御される。制御回路１０には抵抗１
１，ＩＣ１２，コンデンサ１３が搭載され、これらの素
子は厚膜Ａｇ−１ｗｔ％Ｐｔ導体層４により接続されて
いる。ＩＧＢＴ素子１と制御回路１０からはそれぞれ端
子７が引き出されている。半導体装置３０はＩＧＢＴ素
子１とそれを制御する回路１０とから構成され、自動車
用エンジン点火装置のコイルへ給電するのに用いられ
る。また、図８は、図７の回路と同様に自動車用エンジ
ン点火装置のコイルへ給電するのに用いられる、他の半
導体装置の例である。この場合の制御回路には、サージ
保護素子１３Ａやダイオード１４も搭載されている。こ
れらの回路から構成された半導体装置３０は、最高周囲
温度１２０℃の環境のもとで自動車用エンジンを点火す
るのに使用された。自動車の走行距離１０万キロメート
ルに相当する稼働においても、本実施例半導体装置３０
はその回路機能を維持することが確認された。FIG. 7 is a view for explaining the rotation of the semiconductor device 30 of this embodiment. The emitter and gate of the IGBT element 1 are electrically connected to a control circuit 10, and the operation of the element 1 is controlled by the circuit 10. The control circuit 10 has a resistor 1
1, an IC 12, and a capacitor 13 are mounted, and these elements are connected by a thick film Ag-1 wt% Pt conductor layer 4. Terminals 7 are drawn from the IGBT element 1 and the control circuit 10, respectively. The semiconductor device 30 includes the IGBT element 1 and a circuit 10 for controlling the IGBT element 1, and is used to supply power to a coil of an automobile engine ignition device. FIG. 8 is an example of another semiconductor device used to supply power to a coil of an automobile engine ignition device as in the circuit of FIG. In this case, the control circuit also includes a surge protection element 13A and a diode 14. The semiconductor device 30 composed of these circuits was used to ignite an automobile engine under an environment having a maximum ambient temperature of 120 ° C. The semiconductor device 30 of the present embodiment can be operated even when the vehicle travels for 100,000 kilometers.
Was confirmed to maintain its circuit function.
【００３３】〔実施例２〕本実施例では、パワー半導体
基体と制御回路を同一基板上に搭載した高周波電圧増幅
回路を有する半導体装置とこれを用いた電子装置につい
て説明する。[Embodiment 2] In this embodiment, a semiconductor device having a high-frequency voltage amplifier circuit in which a power semiconductor substrate and a control circuit are mounted on the same substrate and an electronic device using the same will be described.
【００３４】パワー半導体素子基体１とその周辺回路素
子を搭載した半導体装置３０は、図９に示す断面構造を
有している。載置部材としてのアルミナ基板（３７×１
２×０.８mm)５の一方の主面側に厚さ約１２μｍの厚膜
Ａｇ−１ｗｔ％Ｐｔ導体層（シート抵抗：１.５ｍΩ／
□)４と厚膜抵抗体１１を形成し、これら導体層４と厚
膜抵抗体１１の所定部にオーバコートガラス層（図示を
省略）を設け、他方の主面側に厚さ約１２μｍの厚膜Ａ
ｇ−１ｗｔ％Ｐｔ導体層（シート抵抗：１.５ｍΩ／
□）４′を形成し、そして導体層４及び４′を接続する
スルーホール厚膜Ａｇ−１ｗｔ％Ｐｔ導体（シート抵
抗：１.５ｍΩ／□）４Ａを形成している。導体層４上
には最終的にろう材３となる組成Ｓｎ−３ｗｔ％Ａｇ−
０.８wt％Ｃｕのろう材粉末を含有したペーストを印刷
し、この印刷部にＳｉからなるＭＯＳＦＥＴチップ基体
１，コンデンサチップ１３、そしてガラススリーブ型ダ
イオードチップ１４等のチップ部品を搭載して空気中で
２５０±１０℃に加熱した。引き続き、Ｎｉめっき（厚
さ：３〜７μｍ、図示を省略）を設けたＣｕ板２上に組
成Ｓｎ−５２ｗｔ％Ｉｎなるろう材３′により基板５を
固着し、パワー半導体素子基体１と導体層４間に直径３
５μｍのＡｕ細線６、そして、導体層４と端子７間に直
径３５μｍのＡｕ細線６′を熱圧着ボンディングして、
所定の高周波電圧増幅回路を構成した。The semiconductor device 30 on which the power semiconductor element substrate 1 and its peripheral circuit elements are mounted has a sectional structure shown in FIG. Alumina substrate as mounting member (37 × 1
2 × 0.8 mm) 5 A thick Ag-1wt% Pt conductor layer (sheet resistance: 1.5 mΩ /
□) 4 and a thick film resistor 11 are formed, an overcoat glass layer (not shown) is provided on a predetermined portion of the conductor layer 4 and the thick film resistor 11, and a thickness of about 12 μm is formed on the other main surface side. Thick film A
g-1 wt% Pt conductor layer (sheet resistance: 1.5 mΩ /
□) 4 ′ is formed, and a through-hole thick film Ag-1 wt% Pt conductor (sheet resistance: 1.5 mΩ / □) 4A connecting the conductor layers 4 and 4 ′ is formed. On the conductor layer 4, the composition Sn-3wt% Ag-
A paste containing a brazing filler metal powder of 0.8 wt% Cu is printed, and chip parts such as a MOSFET chip base body 1 made of Si, a capacitor chip 13, and a glass sleeve type diode chip 14 are mounted on the printed portion, and the printed circuit board is mounted in the air. To 250 ± 10 ° C. Subsequently, the substrate 5 is fixed on the Cu plate 2 provided with Ni plating (thickness: 3 to 7 μm, not shown) by a brazing material 3 ′ having a composition of Sn-52 wt% In, and the power semiconductor element substrate 1 and the conductor layer Diameter 3 between 4
A 5 μm Au thin wire 6 and a 35 μm diameter Au thin wire 6 ′ between the conductor layer 4 and the terminal 7 are thermocompression bonded.
A predetermined high-frequency voltage amplifier circuit was constructed.
【００３５】この増幅回路は最終的に断面図の破線で示
すように、エポキシ樹脂８によるトランスファモールド
が施されている。エポキシ樹脂８は熱膨張率：１６ppm
／℃,ガラス転移点：１５５℃，体積抵抗率：９×１０
15Ω・ｍ（ＲＴ），曲げ強度：３×１０15kgｆ／mm2 ，
曲げ弾性率：１６００kgｆ／mm2 なる特性を有してい
る。トランスファモールドは１８０℃のもとで実施し、
次いで１５０℃のもとで２ｈの熱処理を施して樹脂の硬
化を促進させた。This amplifier circuit is finally subjected to transfer molding using an epoxy resin 8, as shown by the broken line in the sectional view. Epoxy resin 8 has a coefficient of thermal expansion of 16 ppm
/ ° C, glass transition point: 155 ° C, volume resistivity: 9 × 10
15 Ω · m (RT), bending strength: 3 × 10 15 kgf / mm 2 ,
Flexural modulus: 1600 kgf / mm 2 . Transfer mold is performed at 180 ° C,
Then, heat treatment was performed at 150 ° C. for 2 hours to accelerate the curing of the resin.
【００３６】本実施例半導体装置３０に−４０〜１２５
℃の温度サイクルを２０００回与えたが、ＭＯＳＦＥＴ
チップ基体１の搭載部の厚膜Ａｇ−１ｗｔ％Ｐｔ導体層
４やろう材３には何らの異常もみられかった。In the present embodiment, the semiconductor device 30 has -40 to 125
Temperature cycle of 2000 ° C.
No abnormality was found in the thick film Ag-1 wt% Pt conductor layer 4 and the brazing material 3 in the mounting portion of the chip base 1.
【００３７】図１０は半導体装置の入力電圧波形及び出
力電圧波形を示すグラフである。出力電圧は３５Ｖと入
力電圧の０.７Ｖ に対して５０倍の値が得られ、そして
出力電圧波形も立上がり及び立下がりとも０.２ｎｓ 以
下の時定数を示している。この結果は、半導体装置３０
は２５０ＭＨｚ帯の高周波電圧制御用として実用可能な
ことを示唆している。上記装置３０は最終的に画素３０
００×３０００のテレビジョン装置に組み込まれた。そ
の結果、テレビジョン装置は高精細な画像を表示した。FIG. 10 is a graph showing an input voltage waveform and an output voltage waveform of the semiconductor device. The output voltage is 35 V, which is 50 times the value of 0.7 V of the input voltage, and the output voltage waveform also shows a time constant of 0.2 ns or less for both rising and falling. This result indicates that the semiconductor device 30
Suggests that it can be used for high-frequency voltage control in the 250 MHz band. The device 30 is finally
It was incorporated into a 00 × 3000 television device. As a result, the television device displayed a high-definition image.
【００３８】〔実施例３〕本実施例では、窒化アルミニ
ウムセラミックスからなる基板上にパワー半導体基体と
制御回路を搭載した高周波電圧増幅回路を有する半導体
装置とこれを用いた電子装置について説明する。[Embodiment 3] In this embodiment, a semiconductor device having a high-frequency voltage amplifier circuit in which a power semiconductor substrate and a control circuit are mounted on a substrate made of aluminum nitride ceramics, and an electronic device using the same will be described.
【００３９】窒化アルミニウムセラミックス基板５上に
パワー半導体素子基体１とその周辺回路素子を搭載した
半導体装置３０は、図９と同様の断面構造を有してい
る。載置部材としての窒化アルミニウム基板（３７×１
２×０.８mm)５の一方の主面側に厚さ約１２μｍの厚膜
Ａｇ−１ｗｔ％Ｐｔ導体層（シート抵抗：１.５ｍΩ／
□) ４と厚膜抵抗体１１を形成し、これら導体層４と厚
膜抵抗体１１の所定部にオーバコートガラス層（図示を
省略）を設け、他方の主面側に厚さ約１２μｍの厚膜Ａ
ｇ−１ｗｔ％Ｐｔ導体層(シート抵抗：１.５ｍΩ／□）
４′を形成し、そして導体層４及び４′を接続するスル
ーホール厚膜Ａｇ−１ｗｔ％Ｐｔ導体（シート抵抗：
１.５ｍΩ／□）４Ａを形成している。The semiconductor device 30 in which the power semiconductor element substrate 1 and its peripheral circuit elements are mounted on the aluminum nitride ceramics substrate 5 has the same sectional structure as that of FIG. Aluminum nitride substrate (37 × 1) as mounting member
2 × 0.8 mm) 5 A thick Ag-1wt% Pt conductor layer (sheet resistance: 1.5 mΩ /
□) 4 and a thick film resistor 11 are formed, an overcoat glass layer (not shown) is provided on predetermined portions of the conductor layer 4 and the thick film resistor 11, and a thickness of about 12 μm is formed on the other main surface side. Thick film A
g-1wt% Pt conductor layer (sheet resistance: 1.5mΩ / □)
4 ′, and a through-hole thick film Ag-1 wt% Pt conductor connecting the conductor layers 4 and 4 ′ (sheet resistance:
(1.5 mΩ / □) 4A is formed.
【００４０】導体層４上には最終的にろう材３となる組
成Ｓｎ−３ｗｔ％Ａｇ−０.８ｗｔ％Ｃｕのろう材粉末
を含有したペーストを印刷し、この印刷部にＳｉからな
るＭＯＳＦＥＴチップ基体１，コンデンサチップ１３、
そしてガラススリーブ型ダイオードチップ１４等のチッ
プ部品を搭載して空気中で２５０±１０℃に加熱した。
引き続き、Ｎｉめっき（厚さ：３〜７μｍ、図示を省
略）を設けたＣｕ板２上に組成Ｓｎ−５２ｗｔ％Ｉｎな
るろう材３′により基板５を固着し、パワー半導体素子
基体１と導体層４間に直径３５μｍのＡｕ細線６、そし
て、導体層４と端子７間に直径３５μｍのＡｕ細線６′
を熱圧着ボンディングして、所定の高周波電圧増幅回路
を構成した。A paste containing a brazing material powder having a composition of Sn-3 wt% Ag-0.8 wt% Cu, which finally becomes the brazing material 3, is printed on the conductor layer 4, and a MOSFET chip made of Si is printed on the printed portion. Base 1, capacitor chip 13,
Then, chip components such as the glass sleeve type diode chip 14 were mounted and heated to 250 ± 10 ° C. in the air.
Subsequently, the substrate 5 is fixed on the Cu plate 2 provided with Ni plating (thickness: 3 to 7 μm, not shown) by a brazing material 3 ′ having a composition of Sn-52 wt% In, and the power semiconductor element substrate 1 and the conductor layer 4, an Au thin wire 6 having a diameter of 35 μm, and an Au thin wire 6 ′ having a diameter of 35 μm between the conductor layer 4 and the terminal 7.
Was bonded by thermocompression bonding to form a predetermined high-frequency voltage amplifier circuit.
【００４１】この増幅回路は最終的に断面図の破線で示
すように、エポキシ樹脂８によるトランスファモールド
が施されている。エポキシ樹脂８は熱膨張率：１６ppm
／℃,ガラス転移点：１５５℃，体積抵抗率：９×１０
15Ω・ｍ（ＲＴ），曲げ強度：３×１０15kgｆ／mm2 ，
曲げ弾性率：１６００kgｆ／mm2 なる特性を有してい
る。トランスファモールドは１８０℃のもとで実施し、
次いで１５０℃のもとで２ｈの熱処理を施して樹脂の硬
化を促進させた。This amplifier circuit is finally subjected to transfer molding using an epoxy resin 8, as shown by the broken line in the sectional view. Epoxy resin 8 has a coefficient of thermal expansion of 16 ppm
/ ° C, glass transition point: 155 ° C, volume resistivity: 9 × 10
15 Ω · m (RT), bending strength: 3 × 10 15 kgf / mm 2 ,
Flexural modulus: 1600 kgf / mm 2 . Transfer mold is performed at 180 ° C,
Then, heat treatment was performed at 150 ° C. for 2 hours to accelerate the curing of the resin.
【００４２】本実施例半導体装置３０に−４０〜１２５
℃の温度サイクルを２０００回与えたが、ＭＯＳＦＥＴ
チップ基体１の搭載部の厚膜Ａｇ−１ｗｔ％Ｐｔ導体層
４やろう材３には何らの異常もみられなかった。The semiconductor device 30 of the present embodiment has -40 to 125
Temperature cycle of 2000 ° C.
No abnormality was observed in the thick film Ag-1 wt% Pt conductor layer 4 and the brazing material 3 in the mounting portion of the chip base 1.
【００４３】また、半導体装置３０の入力電圧波形及び
出力電圧波形を調べた。この結果、出力電圧は３５Ｖと
入力電圧の０.７Ｖ に対して５０倍の値が得られ、そし
て出力電圧波形も立上がり及び立下がりとも０.２ｎｓ
以下の時定数を示していることが確認された。この結
果、実施例２と同様に、半導体装置３０は２５０ＭＨｚ
帯の高周波電圧制御用として実用可能なことを示唆して
いる。上記装置３０は最終的に画素３０００×３０００
のテレビジョン装置に組み込まれた。この結果、テレビ
ジョン装置は高精細な画像を表示した。The input voltage waveform and the output voltage waveform of the semiconductor device 30 were examined. As a result, the output voltage is 35 V, which is 50 times higher than the input voltage of 0.7 V, and the output voltage waveform is 0.2 ns for both rising and falling.
It was confirmed that the following time constant was exhibited. As a result, similarly to the second embodiment, the semiconductor device 30
It suggests that it can be used for high-frequency voltage control of the band. The device 30 finally has a pixel of 3000 × 3000.
Television device. As a result, the television device displayed a high-definition image.
【００４４】〔実施例４〕本実施例では、ガラスセラミ
ックス（アルミナ＋ほう珪酸ガラス，熱膨張率：５.５p
pm／℃）からなる基板上にパワー半導体基板と制御回路
を搭載した高周波電圧増幅回路を有する半導体装置とこ
れを用いた電子装置について説明する。Embodiment 4 In this embodiment, a glass ceramic (alumina + borosilicate glass, coefficient of thermal expansion: 5.5 p
The following describes a semiconductor device having a high-frequency voltage amplifier circuit in which a power semiconductor substrate and a control circuit are mounted on a substrate made of pm / ° C.) and an electronic device using the same.
【００４５】ガラスセラミックス基板５上にパワー半導
体素子基体１とその周辺回路素子を搭載した半導体装置
３０は、図９と同様の断面構造を有している。載置部材
としてのガラスセラミックス基板（３７×１２×０.８m
m)５の一方の主面側に厚さ約１２μｍの厚膜Ａｇ−１ｗ
ｔ％Ｐｔ導体層(シート抵抗：１.５ｍΩ／□）４と厚膜
抵抗体１１を形成し、これら導体層４と厚膜抵抗体１１
の所定部にオーバコートガラス層（図示を省略）を設
け、他方の主面側に厚さ約１２μｍの厚膜Ａｇ−１ｗｔ
％Ｐｔ導体層(シート抵抗：１.５ｍΩ／□）４′を形成
し、そして導体層４及び４′を接続するスルーホール厚
膜Ａｇ−１ｗｔ％Ｐｔ導体（シート抵抗：１.５ｍΩ／
□）４Ａを形成している。The semiconductor device 30 having the power semiconductor element substrate 1 and its peripheral circuit elements mounted on the glass ceramic substrate 5 has the same cross-sectional structure as that of FIG. Glass ceramic substrate (37 × 12 × 0.8 m) as mounting member
m) A thick film Ag-1w having a thickness of about 12 μm on one main surface side of 5)
The t% Pt conductor layer (sheet resistance: 1.5 mΩ / □) 4 and the thick film resistor 11 are formed, and the conductor layer 4 and the thick film resistor 11 are formed.
Is provided with an overcoat glass layer (not shown) at a predetermined portion, and a thick film Ag-1wt having a thickness of about 12 μm is provided on the other main surface side.
% Pt conductor layer (sheet resistance: 1.5 mΩ / □) 4 ′, and a through-hole thick film Ag-1 wt% Pt conductor (sheet resistance: 1.5 mΩ / sheet) connecting conductor layers 4 and 4 ′
□) 4A is formed.
【００４６】導体層４上には最終的にろう材３となる組
成Ｓｎ−３ｗｔ％Ａｇ−０.８wt％Ｃｕのろう材粉末を
含有したペーストを印刷し、この印刷部にＳｉからなる
ＭＯＳＦＥＴチップ基体１，コンデンサチップ１３、そ
してガラススリーブ型ダイオードチップ１４等のチップ
部品を搭載して空気中で２５０±１０℃に加熱した。引
き続き、Ｎｉめっき（厚さ：３〜７μｍ、図示を省略）
を設けたＣｕ板２上に組成Ｓｎ−５２ｗｔ％Ｉｎなるろ
う材３′により基板５を固着し、パワー半導体素子基体
１と導体層４間に直径３５μｍのＡｕ細線６、そして、
導体層４と端子７間に直径３５μｍのＡｕ細線６′を熱
圧酢ボンディングして、所定の高周波電圧増幅回路を構
成した。A paste containing a brazing material powder having a composition of Sn-3 wt% Ag-0.8 wt% Cu, which finally becomes the brazing material 3, is printed on the conductor layer 4, and a MOSFET chip made of Si is printed on the printed portion. The chip components such as the base 1, the capacitor chip 13, and the glass sleeve type diode chip 14 were mounted and heated to 250 ± 10 ° C. in air. Subsequently, Ni plating (thickness: 3 to 7 μm, not shown)
The substrate 5 is fixed on the Cu plate 2 provided with the above by a brazing material 3 ′ having a composition of Sn-52 wt% In, an Au fine wire 6 having a diameter of 35 μm between the power semiconductor element substrate 1 and the conductor layer 4, and
An Au fine wire 6 ′ having a diameter of 35 μm was bonded between the conductor layer 4 and the terminal 7 by hot and pressure vinegar bonding to form a predetermined high-frequency voltage amplifier circuit.
【００４７】この増幅回路は最終的に断面図の破線で示
すように、エポキシ樹脂８によるトランスファモールド
が施されている。エポキシ樹脂８は熱膨張率：１６ppm
／℃,ガラス転移点：１５５℃，体積抵抗率：９×１０
15Ω・ｍ（ＲＴ），曲げ強度：３×１０15kgｆ／mm2 ，
曲げ弾性率：１６００kgｆ／mm2 なる特性を有してい
る。トランスファモールドは１８０℃のもとで実施し、
次いで１５０℃のもとで２ｈの熱処理を施して樹脂の硬
化を促進させた。This amplifier circuit is finally subjected to transfer molding using an epoxy resin 8 as shown by the broken line in the sectional view. Epoxy resin 8 has a coefficient of thermal expansion of 16 ppm
/ ° C, glass transition point: 155 ° C, volume resistivity: 9 × 10
15 Ω · m (RT), bending strength: 3 × 10 15 kgf / mm 2 ,
Flexural modulus: 1600 kgf / mm 2 . Transfer mold is performed at 180 ° C,
Then, heat treatment was performed at 150 ° C. for 2 hours to accelerate the curing of the resin.
【００４８】本実施例半導体装置３０に−４０〜１２５
℃の温度サイクルを２０００回与えたが、ＭＯＳＦＥＴ
チップ基体１の搭載部の厚膜Ａｇ−１ｗｔ％Ｐｔ導体層
４やろう材３には何らの異常もみられかった。In the present embodiment, the semiconductor device 30 has -40 to 125
Temperature cycle of 2000 ° C.
No abnormality was found in the thick film Ag-1 wt% Pt conductor layer 4 and the brazing material 3 in the mounting portion of the chip base 1.
【００４９】また、半導体装置３０の入力電圧波形及び
出力電圧波形を調べた。この結果、出力電圧は３５Ｖと
入力電圧の０.７Ｖ に対して５０倍の値が得られ、そし
て出力電圧波形も立上がり及び立下がりとも０.２ｎｓ
以下の時定数を示していることが確認された。この結
果、実施例２と同様に、半導体装置３０は２５０ＭＨｚ
帯の高周波電圧制御用として実用可能なことを示唆して
いる。上記装置３０は最終的に画素３０００×３０００
のテレビジョン装置に組み込まれた。この結果、テレビ
ジョン装置は高精細な画像を表示した。The input voltage waveform and the output voltage waveform of the semiconductor device 30 were examined. As a result, the output voltage is 35 V, which is 50 times higher than the input voltage of 0.7 V, and the output voltage waveform is 0.2 ns for both rising and falling.
It was confirmed that the following time constant was exhibited. As a result, similarly to the second embodiment, the semiconductor device 30
It suggests that it can be used for high-frequency voltage control of the band. The device 30 finally has a pixel of 3000 × 3000.
Television device. As a result, the television device displayed a high-definition image.
【００５０】以上までに、実施例を用いて本発明を説明
した。しかし、本発明は実施例に記載の事項のみに限定
されるものではない。The present invention has been described with reference to the embodiments. However, the present invention is not limited only to the matters described in the examples.
【００５１】本発明において、半導体装置３０は負荷に
給電する電気回路に組み込まれて使用される。このよう
にして使用される装置は、本発明で言う電子装置であ
る。この際、（１）半導体装置が、回転装置に給電する
電気回路に組み込まれて、上記回転装置の回転速度を制
御するが、もしくは、それ自体が移動するシステム（例
えば、電車，エレベータ，エスカレータ，ベルトコンベ
ア）に回転装置とともに組み込まれて上記移動システム
の移動速度を制御する場合、（２）前記回転装置に給電
する電気回路がインバータ回路である場合、（３）半導
体装置が流体を撹拌又は流動させる装置に組み込まれ
て、被撹拌物又は被流動物の移動速度を制御する場合、
（４）半導体装置が物体を加工する装置に組み込まれ
て、被加工物の研削速度を制御する場合、（５）半導体
装置が発光体に組み込まれて、上記発光体の放出光量を
制御する場合、そして、（６）半導体装置が出力周波数
５０Ｈｚないし３０ｋＨｚで作動する場合にも、上記実
施例の場合と同様の効果，利点を享受できる。In the present invention, the semiconductor device 30 is used by being incorporated in an electric circuit for supplying power to a load. The device used in this way is the electronic device referred to in the present invention. At this time, (1) the semiconductor device is incorporated in an electric circuit for supplying power to the rotating device to control the rotation speed of the rotating device, or a system that moves itself (for example, a train, an elevator, an escalator, (2) When the electric circuit that feeds the rotating device is an inverter circuit, (3) the semiconductor device agitates or flows the fluid. In the case of controlling the moving speed of the object to be stirred or the object to be fluidized,
(4) A case where the semiconductor device is incorporated in a device for processing an object to control a grinding speed of a workpiece, and (5) A case where the semiconductor device is incorporated in a light emitter and the amount of emitted light of the light emitter is controlled. (6) Even when the semiconductor device operates at an output frequency of 50 Hz to 30 kHz, the same effects and advantages as those of the above embodiment can be obtained.
【００５２】本発明において、半導体基板１になり得る
素材は、Ｓｉ（４.２ppm／℃），Ｇｅ（５.８ppm／
℃），ＧａＡｓ（６.５ppm／℃），ＧａＰ（５.３ppm／
℃），ＳｉＣ（３.５ppm／℃）等である。これらの素材
からなる半導体素子を搭載することに何らの制約もな
い。この際、半導体基体はサイリスタ，トランジスタ等
実施例に記載されていない電気的機能を有していてもよ
い。また、基板５上に形成された厚膜抵抗１１はチップ
抵抗に置き換えられてもよい。In the present invention, the materials that can be the semiconductor substrate 1 are Si (4.2 ppm / ° C.) and Ge (5.8 ppm /
° C), GaAs (6.5 ppm / ° C), GaP (5.3 ppm /
° C), SiC (3.5 ppm / ° C) and the like. There are no restrictions on mounting semiconductor elements made of these materials. At this time, the semiconductor substrate may have an electrical function, such as a thyristor or a transistor, which is not described in the embodiments. Further, the thick film resistor 11 formed on the substrate 5 may be replaced with a chip resistor.
【００５３】[0053]
【発明の効果】本発明によれば、チップ部品を載置部材
にろう付けして固着する際の過剰な界面反応を抑制し、
製造時あるいは運転時の熱的及び機械的変化によるろう
付け部の破損を防止し、製造歩留りや信頼性の高い半導
体装置とこれを用いた電子装置を提供することができ
る。According to the present invention, an excessive interfacial reaction when a chip component is brazed and fixed to a mounting member is suppressed,
It is possible to provide a semiconductor device having high manufacturing yield and high reliability and an electronic device using the same, by preventing breakage of a brazed portion due to thermal and mechanical changes during manufacturing or operation.
【図１】本発明の半導体装置を説明する鳥瞰図及び断面
図である。FIG. 1 is a bird's-eye view and a cross-sectional view illustrating a semiconductor device of the present invention.
【図２】チップ部品搭載部の断面構造模式図である。FIG. 2 is a schematic sectional view of a chip component mounting section.
【図３】溶融したろう材槽中にディップした場合の厚膜
Ａｇ−Ｐｔ導体層の残留厚さを示すグラフである。FIG. 3 is a graph showing the residual thickness of a thick Ag-Pt conductor layer when dipped in a molten brazing material bath.
【図４】厚膜Ａｇ−Ｐｔ導体層のシート抵抗を示すグラ
フである。FIG. 4 is a graph showing sheet resistance of a thick Ag-Pt conductor layer.
【図５】チップ部品を搭載したろう付け部の金属のデプ
スプロファイルを示すグラフである。FIG. 5 is a graph showing a metal depth profile of a brazing portion on which a chip component is mounted.
【図６】温度サイクル試験によるコンデンサチップろう
付け部のインピーダンスの推移を示すグラフである。FIG. 6 is a graph showing a change in impedance of a capacitor chip brazing part by a temperature cycle test.
【図７】一実施例の半導体装置の回路を説明する図であ
る。FIG. 7 is a diagram illustrating a circuit of a semiconductor device according to one embodiment.
【図８】他の半導体装置の回路を説明する図である。FIG. 8 is a diagram illustrating a circuit of another semiconductor device.
【図９】他の実施例の半導体装置を説明する断面図であ
る。FIG. 9 is a cross-sectional view illustrating a semiconductor device according to another embodiment.
【図１０】他の実施例の半導体装置の入力電圧波形及び
出力電圧波形を示すグラフである。FIG. 10 is a graph showing an input voltage waveform and an output voltage waveform of a semiconductor device according to another embodiment.
１…半導体基体，ＩＧＢＴチップ，ＭＯＳＦＥＴチップ
基体、２…Ｃｕベース板、３，３′…ろう材、４，４′
…厚膜Ａｇ−Ｐｔ導体，導体層、４Ａ…スルーホール厚
膜Ａｇ−Ｐｔ導体、５…アルミナ基板，窒化アルミニウ
ム基板、６，６′…Ａｌワイヤ，Ａｕ細線、７…端子、
８…エポキシ樹脂、９…シリコーン樹脂接着剤、１０…
制御回路、１１…厚膜抵抗、１２…ＩＣチップ基体、１
３…コンデンサチップ、１３Ａ…サージ保護素子、１４
…ガラススリーブ型ツェナーダイオードチップ，ダイオ
ード、３０…半導体装置。DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, IGBT chip, MOSFET chip base, 2 ... Cu base plate, 3, 3 '... Brazing material, 4, 4'
... Thick film Ag-Pt conductor, conductor layer, 4A ... Through hole thick film Ag-Pt conductor, 5 ... Alumina substrate, aluminum nitride substrate, 6,6 '... Al wire, Au fine wire, 7 ... Terminal,
8 ... epoxy resin, 9 ... silicone resin adhesive, 10 ...
Control circuit, 11: thick film resistor, 12: IC chip base, 1
3 ... Capacitor chip, 13A ... Surge protection element, 14
... Glass sleeve type Zener diode chip, diode, 30 ... Semiconductor device.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 根岸 幹夫 埼玉県入間郡毛呂山町旭台15番地 日立東 部セミコンダクタ株式会社内 (72)発明者 小山 賢治 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 飯塚 守 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 遠藤 恒雄 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 金井 紀洋士 茨城県ひたちなか市大字高場2520番地 株 式会社日立製作所自動車機器事業部内 (72)発明者 大久保 利男 茨城県ひたちなか市大字高場2520番地 株 式会社日立製作所自動車機器事業部内 Ｆターム(参考） 5E319 AC04 BB01 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mikio Negishi 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Hitachi East Division Semiconductor Co., Ltd. Within Hitachi Semiconductor Co., Ltd. (72) Inventor Mamoru Iizuka 5--20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated Hitachi Semiconductor Co., Ltd. (72) Inventor Tsuneo Endo Kamisuihoncho, Kodaira-shi 5-20-1, Hitachi, Ltd.Semiconductor Division, Hitachi, Ltd. (72) Inventor: Norihiro Kanai 2520, Oji-Koba, Hitachinaka-shi, Ibaraki Prefecture, Ltd.Automotive Equipment Division, Hitachi, Ltd. 2520 Takaba, Oita-shi F-term (reference) in the Automotive Equipment Division of Hitachi, Ltd. 5E31 9 AC04 BB01
Claims (3)
材上に、Ｓｎからなるろう材又はＳｎ，Ｓｂ，Ａｇ，Ｃ
ｕ，Ｎｉ，Ｐ，Ｂｉ，ＺＮ，ＡｕそしてＩｎの群から選
択された２種以上の物質からなるろう材により固着さ
れ、該載置部材の該固着部にＰｔを含む原膜導体層が設
けられていることを特徴とする半導体装置。1. A brazing material made of Sn or Sn, Sb, Ag, C on a mounting member whose chip component is made of ceramic.
u, Ni, P, Bi, ZN, Au, and In are fixed by a brazing material made of two or more kinds of substances selected from the group of In, and a raw film conductor layer containing Pt is provided on the fixing portion of the mounting member. A semiconductor device characterized in that:
又はガラスセラミックス又は窒化アルミニウムセラミッ
クスからなることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein said mounting member is made of alumina, glass ceramics, or aluminum nitride ceramics.
材上に、Ｓｎからなるろう材又はＳｎ，Ｓｂ，Ａｇ，Ｃ
ｕ，Ｎｉ，Ｐ，Ｂｉ，ＺＮ，ＡｕそしてＩｎの群から選
択された２種以上の物質からなるろう材により固着さ
れ、該載置部材の該固着部にＰｔを含む原膜導体層が設
けられている半導体装置が、負荷に給電する回路に組み
込まれたことを特徴とする電子装置。3. A brazing material made of Sn or Sn, Sb, Ag, C on a mounting member whose chip component is made of ceramic.
u, Ni, P, Bi, ZN, Au, and In are fixed by a brazing material made of two or more kinds of substances selected from the group of In, and a raw film conductor layer containing Pt is provided on the fixing portion of the mounting member. An electronic device, wherein the semiconductor device is incorporated in a circuit for supplying power to a load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7915199A JP2000277909A (en) | 1999-03-24 | 1999-03-24 | Semiconductor device and electronic device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7915199A JP2000277909A (en) | 1999-03-24 | 1999-03-24 | Semiconductor device and electronic device using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000277909A true JP2000277909A (en) | 2000-10-06 |
Family
ID=13681970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7915199A Withdrawn JP2000277909A (en) | 1999-03-24 | 1999-03-24 | Semiconductor device and electronic device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000277909A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005020315A1 (en) * | 2003-08-26 | 2005-03-03 | Tokuyama Corporation | Substrate for device bonding, device bonded substrate, and method for producing same |
-
1999
- 1999-03-24 JP JP7915199A patent/JP2000277909A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005020315A1 (en) * | 2003-08-26 | 2005-03-03 | Tokuyama Corporation | Substrate for device bonding, device bonded substrate, and method for producing same |
| JPWO2005020315A1 (en) * | 2003-08-26 | 2007-11-01 | 株式会社トクヤマ | Element bonding substrate, element bonding substrate and manufacturing method thereof |
| KR100825354B1 (en) * | 2003-08-26 | 2008-04-28 | 가부시끼가이샤 도꾸야마 | Substrate for device bonding, device bonded substrate, and method for producing same |
| CN100423217C (en) * | 2003-08-26 | 2008-10-01 | 德山株式会社 | Substrate for device bonding, device bonded substrate, and method for producing same |
| US7459794B2 (en) | 2003-08-26 | 2008-12-02 | Tokuyama Corporation | Substrate for device bonding, device bonded substrate, and method for producing same |
| JP4979944B2 (en) * | 2003-08-26 | 2012-07-18 | 株式会社トクヤマ | Element bonding substrate, element bonding substrate and manufacturing method thereof |
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