JP2000236161A - Manufacturing method of printed wiring board - Google Patents

Manufacturing method of printed wiring board

Info

Publication number
JP2000236161A
JP2000236161A JP11035272A JP3527299A JP2000236161A JP 2000236161 A JP2000236161 A JP 2000236161A JP 11035272 A JP11035272 A JP 11035272A JP 3527299 A JP3527299 A JP 3527299A JP 2000236161 A JP2000236161 A JP 2000236161A
Authority
JP
Japan
Prior art keywords
circuit pattern
palladium
alkylbenzimidazole
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11035272A
Other languages
Japanese (ja)
Inventor
Osamu Kobayashi
修 小林
Takushi Osawa
卓士 大澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Avionics Co Ltd
Original Assignee
Nippon Avionics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Avionics Co Ltd filed Critical Nippon Avionics Co Ltd
Priority to JP11035272A priority Critical patent/JP2000236161A/en
Publication of JP2000236161A publication Critical patent/JP2000236161A/en
Pending legal-status Critical Current

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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a printed wiring board which is high in accuracy and reliability by a method, wherein a catalyst such as palladium left on the surface of an insulating layer is inactivated, preventing a trouble such as a constricted part or a bridge from being formed on a circuit pattern for improving it in insulating properties in a method of manufacturing a printed wiring board through an additive method, where a circuit pattern is formed of a copper plating layer formed on the surface of an insulating layer. SOLUTION: After a circuit pattern is formed, a board is dipped into an alklbenzimidazole solution, an alkylbenzimidazole protective film is formed around a circuit pattern with respect to a sulfide compound, the board is dipped into a palladium deactivation processing solution whose main component is a sulfide compound, by which palladium as a catalyst is deactivated, and furthermore the board is dipped into a hydrochloric acid, by which an alkylbenzimidazole film serving as a protective film for a circuit pattern is removed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、絶縁層の表面にパ
ラジウムからなる触媒を付与した後銅めっきを施し、こ
の銅めっき層に回路パターンを形成するプリント配線板
の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, in which a palladium catalyst is applied to the surface of an insulating layer, and then copper plating is performed to form a circuit pattern on the copper plating layer.

【0002】[0002]

【従来の技術】従来、絶縁層の表面に銅めっきを施し、
この銅めっき層によって回路パターンを形成するアディ
ティブ法が公知である。また、発明者達は、特願平10
−218504号により、絶縁層に残る触媒たるパラジ
ウムを不活性化するパラジウム不活性化処理液及びこの
処理液を用いたプリント配線板の製造方法を提示した。
2. Description of the Related Art Conventionally, copper plating is applied to the surface of an insulating layer,
An additive method for forming a circuit pattern using the copper plating layer is known. Also, the inventors have filed Japanese Patent Application No.
No. 218504 discloses a palladium inactivation treatment liquid for inactivating palladium as a catalyst remaining in an insulating layer, and a method for manufacturing a printed wiring board using the treatment liquid.

【0003】[0003]

【発明が解決しようとする課題】特願平10−2185
04号に提示した方法により、パラジウム不活性化処理
液で絶縁層に残る触媒たるパラジウムを硫化物化して不
活性化を行うと、このときに回路パターンを形成してい
る銅も、また、パラジウム不活性化処理液によって硫化
物化して硫化銅を生成する。この硫化銅は、絶縁性など
に問題を生じる。
[Problems to be Solved by the Invention] Japanese Patent Application No. 10-2185
According to the method presented in No. 04, when palladium as a catalyst remaining in the insulating layer is deactivated by sulfide with a palladium deactivation treatment liquid, copper forming a circuit pattern at this time also contains palladium. It is sulfided by the passivation solution to produce copper sulfide. This copper sulfide causes a problem in insulation and the like.

【0004】従って、ここで生成された硫化銅を除去し
なければならない。硫化銅を除去する方法としては、研
磨して硫化銅を物理的に除去する研磨法と、生じた硫化
銅の膜の下にある銅を溶解して硫化銅の膜とともに除去
する溶解法とがある。しかし、研磨法では、回路パター
ンの側面とか、回路パターンの凹部に生じた硫化銅は研
磨できない、即ち除去できない。また、溶解法では、銅
を均一に溶解するということが非常に困難で、しばしば
回路パターンに細りや断線が生じた。
[0004] Therefore, the copper sulfide generated here must be removed. As a method of removing copper sulfide, there are a polishing method of physically removing copper sulfide by polishing, and a dissolving method of dissolving copper under the generated copper sulfide film and removing it together with the copper sulfide film. is there. However, in the polishing method, copper sulfide generated on the side surface of the circuit pattern or the concave portion of the circuit pattern cannot be polished, that is, cannot be removed. In addition, it is very difficult to uniformly dissolve copper in the melting method, and thinning and disconnection often occur in a circuit pattern.

【0005】本発明は、上記課題を解決するためになさ
れたもので、パラジウム不活性化処理液で絶縁層に残る
触媒たるパラジウムを硫化物化して不活性化を図る際、
回路パターンを形成している銅が、硫化物化しない、即
ち硫化銅が生成されることのない、プリント配線板の製
造方法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and when palladium as a catalyst remaining in an insulating layer is converted into sulfide by a palladium deactivation treatment liquid to deactivate the catalyst,
An object of the present invention is to provide a method for manufacturing a printed wiring board, in which copper forming a circuit pattern does not sulfide, that is, copper sulfide is not generated.

【0006】[0006]

【課題を解決するための手段】本発明は、絶縁層の表面
に形成しためっき層により回路パターンを形成するアデ
ィティブ法によるプリント配線板の製造方法であって、
前記回路パターンを形成した後、前記回路パターンが形
成されている基板をアルキルベンズイミダゾールの溶液
に浸漬し、少なくとも前記回路パターンの表面をアルキ
ルベンズイミダゾールの皮膜で覆い、ついで、パラジウ
ム不活性化処理液に前記基板を浸漬し、触媒たるパラジ
ウムを硫化物化して不活性化し、その後、前記基板を塩
酸に浸漬し、前記回路パターンの表面を覆っていた前記
アルキルベンズイミダゾールを除去することにより、目
的を達成する。
SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a printed wiring board by an additive method of forming a circuit pattern by a plating layer formed on a surface of an insulating layer,
After forming the circuit pattern, the substrate on which the circuit pattern is formed is immersed in a solution of alkylbenzimidazole, and at least the surface of the circuit pattern is covered with a film of alkylbenzimidazole, and then a palladium deactivation treatment liquid The substrate is immersed in the catalyst, palladium serving as a catalyst is sulfided and inactivated, and then, the substrate is immersed in hydrochloric acid to remove the alkylbenzimidazole covering the surface of the circuit pattern. To achieve.

【0007】[0007]

【発明の実施の形態】図1は本発明の1実施形態を示す
プロセスフローである。図1を用いて本発明の実施の形
態を説明する。まず、基板の両面の絶縁体の表面に触媒
であるパラジウムを付与し、無電解銅めっきを施し、更
に電解銅めっきを施し、銅めっき層を得る。続いて、こ
の銅めっき層の上に、回路を形成すべきパターンでエッ
チングレジストを形成し、エッチングを施し、エッチン
グ後エッチングレジストを除去すれば、所望の回路パタ
ーンを得ることができる(図1のステップS0)。この
工程を図2を用いて詳しく説明する。
FIG. 1 is a process flow showing an embodiment of the present invention. An embodiment of the present invention will be described with reference to FIG. First, palladium as a catalyst is applied to the surfaces of the insulators on both sides of the substrate, electroless copper plating is performed, and further electrolytic copper plating is performed to obtain a copper plating layer. Subsequently, an etching resist is formed on the copper plating layer in a pattern in which a circuit is to be formed, etching is performed, and after etching, the etching resist is removed to obtain a desired circuit pattern (see FIG. 1). Step S0). This step will be described in detail with reference to FIG.

【0008】まず基板10を作る(図2の(A))。こ
の基板10は、絶縁板12の両面にコア層となる第2層
14および第3層16の回路パターンを形成し、これら
の両面に他の絶縁層18、18を積層または絶縁樹脂を
塗布したものである。次に、第二スズイオンがパラジウ
ム金属の周囲に保護コロイドを形成したパラジウムのコ
ロイド溶液に浸漬することにより、基板10に触媒たる
パラジウム20を付与する(図2の(B))。続いて、
この基板10を無電解銅めっき浴に浸漬し、さらに電解
銅めっきし、所定厚さの銅めっき層22が形成される
(図2の(C))。次に、この銅めっき層22に対し、
写真法や印刷法により回路を形成する、即ち回路パター
ンに沿ってエッチングレジストを形成し、エッチングを
行う。そして、エッチングレジストを除去すると、回路
パターン24が得られる。ただし、この結果、表面に現
れた絶縁層18の表面には前記のパラジウム20が残っ
ている(図2の(D))。
First, a substrate 10 is made (FIG. 2A). In the substrate 10, circuit patterns of a second layer 14 and a third layer 16 serving as core layers are formed on both surfaces of the insulating plate 12, and other insulating layers 18 and 18 are laminated or coated with an insulating resin on both surfaces. Things. Next, the stannic ion is immersed in a palladium colloid solution in which a protective colloid is formed around the palladium metal, so that the substrate 10 is provided with palladium 20 as a catalyst (FIG. 2B). continue,
This substrate 10 is immersed in an electroless copper plating bath, and is further subjected to electrolytic copper plating to form a copper plating layer 22 having a predetermined thickness (FIG. 2C). Next, for the copper plating layer 22,
A circuit is formed by a photographic method or a printing method, that is, an etching resist is formed along a circuit pattern and etching is performed. Then, when the etching resist is removed, a circuit pattern 24 is obtained. However, as a result, the palladium 20 remains on the surface of the insulating layer 18 that has appeared on the surface (FIG. 2D).

【0009】再び、図1に戻って説明するが、図1のス
テップS0の結果は、図2の(D)のように、回路パタ
ーンは確かに形成されているが、表面に現れた絶縁層の
表面には、まだ、触媒のパラジウムが残っている。続い
て、図1のステップS1に進むが、ここでは、基板を3
5°Cのアルキルベンズイミダゾールの溶液に2〜3分
浸漬する。これにより、回路パターンにはアルキルベン
ズイミダゾールの保護被膜が形成される。当然、パラジ
ウムにも被膜が形成されるが、パラジウム不活性化溶液
とは十分反応ができる。一方、回路パターンの銅に対す
る被膜は保護する力が強く、パラジウム不活性化溶液と
化合して硫化物化することはない。次に、基板を水洗し
て、余分なアルキルベンズイミダゾールを除去する(ス
テップS2)。続いて、アンモニア水と硫化ナトリウム
の混合液であるパラジウム不活性化溶液の中に、基板を
約1分間浸漬し(ステップS3)、引き上げて、水洗
し、付着した処理液を洗い流す(ステップS4)。終わ
りに、1N(規定)の塩酸(無機酸または有機酸)に基
板を室温で約1分間浸漬し、回路パターンの銅を被覆し
ていたアルキルベンズイミダゾールを除去した(ステッ
プS5)後、基板を水洗して、基板に残留している塩酸
を完全に除去する(ステップS6)。なお、この実施の
形態では、回路を4層にした基板10を用いているが、
本発明はこれに限定されない。
Referring back to FIG. 1, the result of step S0 in FIG. 1 is that the circuit pattern is certainly formed as shown in FIG. The catalyst palladium still remains on the surface. Subsequently, the process proceeds to step S1 in FIG.
Immerse in a solution of alkylbenzimidazole at 5 ° C for 2-3 minutes. As a result, a protective coating of alkylbenzimidazole is formed on the circuit pattern. Naturally, a film is formed on palladium, but it can sufficiently react with the palladium inactivating solution. On the other hand, the coating of the circuit pattern against copper has a strong protecting power and does not combine with the palladium inactivating solution to form sulfide. Next, the substrate is washed with water to remove excess alkylbenzimidazole (step S2). Subsequently, the substrate is immersed in a palladium deactivating solution, which is a mixed solution of aqueous ammonia and sodium sulfide, for about 1 minute (step S3), pulled up, washed with water, and rinsed out of the attached processing liquid (step S4). . At the end, the substrate is immersed in 1N (regulated) hydrochloric acid (inorganic acid or organic acid) at room temperature for about 1 minute to remove the alkylbenzimidazole covering the copper of the circuit pattern (Step S5). The substrate is washed with water to completely remove the hydrochloric acid remaining on the substrate (Step S6). In this embodiment, the substrate 10 having four layers of circuits is used.
The present invention is not limited to this.

【0010】[0010]

【発明の効果】本発明によれば、回路パターンをアルキ
ルベンズイミダゾールにより、硫化物化されないように
保護した後で、触媒たるパラジウムの硫化物化による不
活性化を行い、パラジウムの不活性化処理後、銅パター
ンの硫化物化からの保護被膜たるアルキルベンズイミダ
ゾールを除去しているので、硫酸銅が生成されることは
ない。そのため、硫酸銅を除去する必要がなく、硫酸銅
の除去に伴う配線の細りや断線もない。このため、高精
細かつ高信頼性のプリント配線板を得ることができる。
According to the present invention, after the circuit pattern is protected from alkylation with alkylbenzimidazole, the catalyst is deactivated by sulfided palladium, and after the inactivation treatment of palladium, Since the alkylbenzimidazole which is a protective film from sulfide formation of the copper pattern is removed, no copper sulfate is generated. Therefore, there is no need to remove copper sulfate, and there is no thinning or disconnection of wiring due to removal of copper sulfate. For this reason, a printed wiring board with high definition and high reliability can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の1実施の形態を示すプロセスフローで
ある。
FIG. 1 is a process flow showing one embodiment of the present invention.

【図2】基板に銅めっき〜回路パターン形成の工程を示
す図。
FIG. 2 is a diagram showing steps of copper plating to circuit pattern formation on a substrate.

【符号の説明】[Explanation of symbols]

10 基板 12、18 絶縁層 14、16 内層(第2、3層)回路パターン 20 パラジウム(触媒) 22 銅めっき層 24 外層回路パターン DESCRIPTION OF SYMBOLS 10 Substrate 12, 18 Insulating layer 14, 16 Inner layer (2nd, 3rd layer) circuit pattern 20 Palladium (catalyst) 22 Copper plating layer 24 Outer layer circuit pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁層の表面にパラジウムを触媒にして
めっき層を形成し形成しためっき層により回路パターン
を形成するアディティブ法によるプリント配線板の製造
方法において、前記回路パターンを形成した後、前記回
路パターンが形成されている基板をアルキルベンズイミ
ダゾールの溶液に浸漬し、少なくとも前記回路パターン
の表面をアルキルベンズイミダゾールの皮膜で覆い、つ
いで、パラジウム不活性化処理液に前記基板を浸漬し、
触媒たるパラジウムを硫化物化して不活性化し、その
後、前記基板を塩酸に浸漬し、前記回路パターンの表面
を覆っていた前記アルキルベンズイミダゾールを除去す
ることを特徴とするプリント配線板の製造方法。
In a method for manufacturing a printed wiring board by an additive method, wherein a circuit pattern is formed by forming a plating layer on a surface of an insulating layer using palladium as a catalyst and forming the plating layer, after forming the circuit pattern, Immerse the substrate on which the circuit pattern is formed in a solution of alkylbenzimidazole, cover at least the surface of the circuit pattern with a film of alkylbenzimidazole, and then immerse the substrate in a palladium deactivation treatment liquid,
A method for manufacturing a printed wiring board, comprising: inactivating palladium, which is a catalyst, by sulphidizing it; and thereafter immersing the substrate in hydrochloric acid to remove the alkylbenzimidazole covering the surface of the circuit pattern.
JP11035272A 1999-02-15 1999-02-15 Manufacturing method of printed wiring board Pending JP2000236161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11035272A JP2000236161A (en) 1999-02-15 1999-02-15 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11035272A JP2000236161A (en) 1999-02-15 1999-02-15 Manufacturing method of printed wiring board

Publications (1)

Publication Number Publication Date
JP2000236161A true JP2000236161A (en) 2000-08-29

Family

ID=12437165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11035272A Pending JP2000236161A (en) 1999-02-15 1999-02-15 Manufacturing method of printed wiring board

Country Status (1)

Country Link
JP (1) JP2000236161A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1178624A2 (en) 2000-08-03 2002-02-06 NTT DoCoMo, Inc. Retransmission control method and system for multicast information distribution service, retransmission control apparatus, wireless base station and wireless terminal
US7056448B2 (en) 2002-05-20 2006-06-06 Daiwa Fine Chemicals Co., Ltd. Method for forming circuit pattern
JP2007173676A (en) * 2005-12-26 2007-07-05 Sumitomo Metal Mining Co Ltd Circuit formation method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1178624A2 (en) 2000-08-03 2002-02-06 NTT DoCoMo, Inc. Retransmission control method and system for multicast information distribution service, retransmission control apparatus, wireless base station and wireless terminal
US7056448B2 (en) 2002-05-20 2006-06-06 Daiwa Fine Chemicals Co., Ltd. Method for forming circuit pattern
JP2007173676A (en) * 2005-12-26 2007-07-05 Sumitomo Metal Mining Co Ltd Circuit formation method

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