JP2000232130A - Mounting method of semiconductor chip - Google Patents

Mounting method of semiconductor chip

Info

Publication number
JP2000232130A
JP2000232130A JP11031814A JP3181499A JP2000232130A JP 2000232130 A JP2000232130 A JP 2000232130A JP 11031814 A JP11031814 A JP 11031814A JP 3181499 A JP3181499 A JP 3181499A JP 2000232130 A JP2000232130 A JP 2000232130A
Authority
JP
Japan
Prior art keywords
chip
wiring board
electrode
substrate
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11031814A
Other languages
Japanese (ja)
Inventor
Kuniaki Takahashi
邦明 高橋
Ikko Murakami
壱皇 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11031814A priority Critical patent/JP2000232130A/en
Publication of JP2000232130A publication Critical patent/JP2000232130A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
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    • H01L2224/13017—Shape in side view being non uniform along the bump connector
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    • H01L2224/1301—Shape
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    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mounting method of semiconductor chip in which reliability of electrical connection between a semiconductor bare chip and a printed wiring board can be enhanced and strain developed at the junction of the chip and the wiring board due to temperature variation can be relaxed. SOLUTION: A bump 3 having conical forward end is formed on the electrode 2 of a semiconductor bare chip 1 and bonded surely to the electrode 7 on a printed wiring board 6 while penetrating an insulating resin 8 applied thereon. Difference of the coefficient of thermal expansion between the semiconductor bare chip 1 and the printed wiring board 6 is reduced simulatively using an insulating resin 8 having a coefficient of thermal expansion after curing substantially equal to the intermediate value of that of a preform of the semiconductor bare chip 1 and that of the preform of the printed wiring board 6 thus relaxing strain developed at the junction of the chip 1 and the wiring board 6 due to temperature variation after mounting the chip 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体べアチップ
をプリント配線板等に直接実装するための実装技術に関
する。The present invention relates to a mounting technique for directly mounting a semiconductor bare chip on a printed wiring board or the like.

【０００２】[0002]

【従来の技術】近年、電子機器の小型化、高密度化の要
求に対応し、半導体ベアチップをリードを介さず配線基
板に直接実装するベアチップ実装技術（ベアチップオン
サブストレート：Bare Chip on Substrate）の研究が進
められてきたが、このベアチップ実装技術の中でも特に
フリップチップボンディング方式（Flip Chip Bonding:
FCB）がここにきて注目されている。この理由の一つと
しては、実装した半導体ベアチップと配線基板との間隙
に特定の絶縁樹脂を充填すると、温度変化が起こったと
きに、チップの材質と基板の材質との熱膨張係数の差に
より、チップと基板との接合部に発生する歪みが分散さ
れ、この接合部分の接続信頼性が向上することが、最近
になって判ってきたからである。2. Description of the Related Art In recent years, in response to demands for miniaturization and high-density of electronic devices, a bare chip mounting technology (Bare Chip on Substrate) for directly mounting a semiconductor bare chip on a wiring board without using leads has been adopted. Research has been advanced, but among these bare chip mounting technologies, flip chip bonding (Flip Chip Bonding:
FCB) is attracting attention here. One of the reasons is that when a specific insulating resin is filled in the gap between the mounted semiconductor bare chip and the wiring board, when the temperature changes, the difference in the thermal expansion coefficient between the material of the chip and the material of the substrate causes This is because it has recently been found that the strain generated at the junction between the chip and the substrate is dispersed, and the connection reliability at this junction is improved.

【０００３】すなわち、実装する半導体ベアチップが、
例えばＳｉ（シリコン）チップであるとすると熱膨張係
数は２．８ｐｐｍ／℃程度であり、これに対し配線基板
がガラスエポキシ製であった場合には、熱膨張係数は約
１５ｐｐｍ／℃であることから、これにより、熱膨張係
数の差が５倍を超える大きなものとなってしまうが、絶
縁樹脂として、例えばシリカ（二酸化ケイ素: Ｓｉ
Ｏ2 ）質粉末等の混合材が混入された、熱膨張係数がチ
ップと基板との中間の値である約９ｐｐｍ／℃程度のエ
ポキシ系の樹脂を、チップと基板との接合部近傍の間隙
に充填することで、チップと基板との熱膨張係数の差を
疑似的に低減し、温度変化により発生する接合部の歪み
を緩和させることが可能となる。That is, the semiconductor bare chip to be mounted is
For example, in the case of a Si (silicon) chip, the thermal expansion coefficient is about 2.8 ppm / ° C., whereas when the wiring board is made of glass epoxy, the thermal expansion coefficient is about 15 ppm / ° C. Therefore, this results in a large difference in the coefficient of thermal expansion exceeding 5 times, but as the insulating resin, for example, silica (silicon dioxide: Si
An epoxy resin having a thermal expansion coefficient of about 9 ppm / ° C., which is an intermediate value between the chip and the substrate, mixed with a mixed material such as O 2 ) powder, is mixed with a gap near the junction between the chip and the substrate. In this way, the difference in the coefficient of thermal expansion between the chip and the substrate can be reduced in a pseudo manner, and the distortion of the joint caused by the temperature change can be reduced.

【０００４】ところで、既述してきたように、この半導
体チップの実装方法はべアチップを配線基板に直接実装
する方法であるため、半導体ベアチップに設けられた複
数の電極にそれぞれバンプと呼ばれる導電性の凸部を形
成し、配線基板の個々の電極とチップの各バンプとを対
向させた状態で加熱溶融接合を行うようにしている。ま
た、この実装方法は、図６及び図７に示すように、半導
体べアチップ５１に形成された複数の電極５２上の個々
のバンプ５３の高さを揃えることで、個々のバンプ５３
を配線基板の各電極にほぼ均一に接触させ実装できるよ
う、電極５２に一旦、バンプ５３を形成した後、専用の
成形加工型５４を各バンプ５３の先端部に押し当てるフ
ラットニング処理（平坦化処理）を一般に施すものとな
っている。As described above, since this semiconductor chip mounting method is a method in which a bare chip is directly mounted on a wiring board, a plurality of electrodes provided on a semiconductor bare chip are each provided with a conductive material called a bump. The heat fusion bonding is performed in a state where the convex portions are formed and the individual electrodes of the wiring board and the bumps of the chip are opposed to each other. In this mounting method, as shown in FIGS. 6 and 7, the heights of the individual bumps 53 on the plurality of electrodes 52 formed on the semiconductor bare chip 51 are made uniform, so that the individual bumps 53 are formed.
After the bumps 53 are once formed on the electrodes 52 so that they can be brought into almost uniform contact with the electrodes of the wiring board and mounted, a flattening process (flattening) is performed in which a dedicated molding die 54 is pressed against the tips of the bumps 53. Processing) is generally performed.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の半導体チップの実装方法では、フラットニン
グ処理が行われた後、図８に示すように、半導体ベアチ
ップ５１の電極５２に形成されたバンプ５３と配線基板
５５の電極５６とを接触させて実施する加熱溶融接合の
際に、絶縁樹脂５７の中に混入されている比較的粒子が
粗く、無論絶縁性を有するフィラー５８が、図９に示す
ように、半導体ベアチップ５１の電極５２に形成された
バンプ５３と配線基板５５の電極５６との間に介在され
てしまうことがあり、接合不良が発生することがあっ
た。However, in such a conventional method of mounting a semiconductor chip, after a flattening process is performed, as shown in FIG. 8, bumps formed on electrodes 52 of a semiconductor bare chip 51 are formed. At the time of the heat fusion bonding performed by bringing the electrode 53 of the wiring board 55 into contact with the electrode 53, the filler 58 having relatively coarse particles mixed in the insulating resin 57 and of course having insulating properties is shown in FIG. As shown in the figure, the bumps 53 formed on the electrodes 52 of the semiconductor bare chip 51 may be interposed between the electrodes 56 of the wiring board 55, and a bonding failure may occur.

【０００６】本発明はこのような課題を解決するために
なされたものであり、半導体チップと配線基板との電気
的な接続信頼性を向上させることができるとともに、実
装後において、温度変化によりチップと基板との接合部
に発生する歪みを緩和することが可能な半導体チップの
実装方法を提供しようとするものである。SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and can improve the reliability of the electrical connection between a semiconductor chip and a wiring board. It is an object of the present invention to provide a method of mounting a semiconductor chip capable of reducing distortion generated at a joint between a semiconductor chip and a substrate.

【０００７】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体チップの実装方法は、請求項１に記
載されているように、半導体チップに鋭角な先端を有す
る電極を形成する工程と、基板に設けられた電極上に絶
縁樹脂を塗布する工程と、前記半導体チップに形成され
た鋭角な先端を有する前記電極を、前記基板の電極上に
塗布された前記絶縁樹脂を貫通させ該基板の電極に接合
する工程とを有することを特徴とする。また、本発明の
半導体チップの実装方法は、請求項２に記載されている
ように、半導体チップの電極に鋭角な先端を有するバン
プを形成する工程と、基板に設けられた電極上に絶縁樹
脂を塗布する工程と、前記半導体チップの電極に形成さ
れた鋭角な先端を有する前記バンプを、前記基板の電極
上に塗布された前記絶縁樹脂を貫通させ該基板の電極に
接合する工程とを有することを特徴とする。In order to achieve the above object, a method of mounting a semiconductor chip according to the present invention forms an electrode having a sharp tip on a semiconductor chip as described in claim 1. A step of applying an insulating resin on an electrode provided on the substrate, and allowing the electrode having an acute tip formed on the semiconductor chip to penetrate the insulating resin applied on the electrode of the substrate. Bonding to the electrode of the substrate. According to a second aspect of the present invention, there is provided a method of mounting a semiconductor chip, comprising the steps of: forming a bump having a sharp tip on an electrode of the semiconductor chip; and forming an insulating resin on the electrode provided on the substrate. And bonding the bump having an acute tip formed on the electrode of the semiconductor chip to the electrode of the substrate by penetrating the insulating resin applied on the electrode of the substrate. It is characterized by the following.

【０００８】さらに、本発明の半導体チップの実装方法
は、請求項３に記載されているように、請求項１又は２
記載の半導体チップの実装方法において、前記絶縁樹脂
の硬化後の熱膨張係数の値は、前記半導体チップの熱膨
張係数の値と前記基板の熱膨張係数の値との間にあるこ
とを特徴とする。Further, the method of mounting a semiconductor chip according to the present invention is as described in claim 3 or 2.
In the method for mounting a semiconductor chip according to the above, the value of the thermal expansion coefficient after curing of the insulating resin is between the value of the thermal expansion coefficient of the semiconductor chip and the value of the thermal expansion coefficient of the substrate. I do.

【０００９】本発明の半導体チップの実装方法によれ
ば、バンプ等により形成された鋭角な先端を有する半導
体チップの電極を、基板の電極上に塗布された絶縁樹脂
を貫通させ当該基板の電極に確実に接合することができ
る。すなわち、本発明の半導体チップの実装方法は、絶
縁樹脂中に例えばフィラー等の比較的粒子の粗い混合材
が混入されている場合でも、加熱溶融接合を行うために
チップの電極と基板の電極とを接触させる際に、半導体
チップの電極の鋭角な先端部分を、混合材の粒子を掻き
分ける作用として働かせることができ、これにより、チ
ップの電極と基板の電極との間に混合材を介在させてし
まうような可能性を低減し、半導体チップと基板との電
気的な接続信頼性を向上させることが可能である。According to the method of mounting a semiconductor chip of the present invention, the electrode of the semiconductor chip having an acute tip formed by a bump or the like is passed through the insulating resin applied on the electrode of the substrate, and the electrode of the substrate is connected to the electrode of the substrate. It is possible to surely join. That is, the method of mounting a semiconductor chip of the present invention, even when a relatively coarse mixed material such as a filler is mixed in the insulating resin, for example, to perform the heat fusion bonding between the chip electrode and the substrate electrode. When the contact is made, the sharp tip portion of the electrode of the semiconductor chip can act as an action of pushing out particles of the mixture material, whereby the mixture material is interposed between the electrode of the chip and the electrode of the substrate. It is possible to reduce the possibility that the semiconductor chip and the substrate are electrically connected, and to improve the reliability of electrical connection between the semiconductor chip and the substrate.

【００１０】また、本発明の半導体チップの実装方法
は、前述したように、半導体チップと基板との電気的な
接続信頼性を向上させることが可能なので、絶縁樹脂の
材質、及び絶縁樹脂に混入する混合材の材質を、チップ
の電極と基板の電極との接続性のみにとらわれることな
く、自由に選択することができる。したがって、本発明
は、硬化後の熱膨張係数の値が、例えば半導体チップの
熱膨張係数の値と基板のの熱膨張係数の値とのほぼ中間
にある絶縁樹脂を選択し、半導体チップと基板との接合
部近傍の間隙に、この選択した絶縁樹脂を充填すること
が可能である。これにより、実装された半導体チップの
熱膨張係数と基板の熱膨張係数との差が比較的大きい場
合であっても、この熱膨張係数の差を疑似的に低減し、
実装後において、温度変化によりチップと基板との接合
部に発生する歪みを、緩和することが可能となる。In addition, the method of mounting a semiconductor chip according to the present invention can improve the reliability of electrical connection between the semiconductor chip and the substrate as described above. The material of the mixed material to be used can be freely selected without being limited only to the connectivity between the electrode of the chip and the electrode of the substrate. Therefore, the present invention selects an insulating resin in which the value of the coefficient of thermal expansion after curing is, for example, approximately halfway between the value of the coefficient of thermal expansion of the semiconductor chip and the value of the coefficient of thermal expansion of the substrate, and It is possible to fill the selected insulating resin in the gap near the junction with the insulating resin. Thereby, even if the difference between the coefficient of thermal expansion of the mounted semiconductor chip and the coefficient of thermal expansion of the substrate is relatively large, the difference in the coefficient of thermal expansion is reduced in a pseudo manner,
After the mounting, it is possible to reduce the distortion generated at the junction between the chip and the substrate due to a temperature change.

【００１１】[0011]

【発明の実施の形態】以下、本発明を実施する場合の形
態について図面に基づき説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１２】図１は本発明の実施形態にかかる、電極に
バンプの形成された半導体ベアチップを示す断面図、図
２は図１の半導体ベアチップに形成されたバンプにフォ
ーミング処理を施すための成形加工型を示す断面図、図
３は電極に絶縁樹脂が塗布されたプリント配線板と図２
の成形加工型によってバンプがフォーミングされた半導
体ベアチップとを示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor bare chip having bumps formed on electrodes according to an embodiment of the present invention. FIG. 2 is a molding process for forming a bump on the semiconductor bare chip shown in FIG. FIG. 3 is a sectional view showing a mold, and FIG. 3 is a printed wiring board in which an insulating resin is applied to electrodes and FIG.
FIG. 4 is a cross-sectional view showing a semiconductor bare chip on which bumps have been formed by a molding die.

【００１３】図１に示すように、Ｓｉチップである半導
体ベアチップ１には、各電極２にそれぞれ金製のバンプ
３が設けられている。また、図２に示すように、成形加
工型４には、半導体ベアチップ１の各電極２に形成され
たバンプ３の先端部を、円錐状の鋭角な先端部に加工す
るために、半導体ベアチップ１上の電極２の位置及び個
々のピッチ等が考慮され、円錐形状に対応する複数の彫
込部５が設けられている。この彫込部５は、半導体べア
チップ１の各電極２上の個々のバンプ３の高さを揃える
ことで、バンプ３をプリント配線板の各電極にほぼ均一
に接触させ実装できるよう、それぞれが同一の彫込深さ
となっている。さらに、成形加工型４は、加熱処理機能
を有しており、各バンプ３を均一な高さに加工するフォ
ーミン処理時に、バンプ３を約１３０℃〜１８０℃に加
熱することが可能である。As shown in FIG. 1, a bump 3 made of gold is provided on each electrode 2 of a semiconductor bare chip 1 which is a Si chip. As shown in FIG. 2, the molding die 4 is provided with a semiconductor bare chip 1 in order to process the tip of the bump 3 formed on each electrode 2 of the semiconductor bare chip 1 into a sharp conical tip. In consideration of the position of the upper electrode 2 and individual pitches, a plurality of engraved portions 5 corresponding to the conical shape are provided. The engraved portions 5 are arranged such that the bumps 3 on the respective electrodes 2 of the semiconductor bare chip 1 are uniform in height so that the bumps 3 can be almost uniformly contacted with the respective electrodes of the printed wiring board and mounted. It has the same engraving depth. Furthermore, the molding die 4 has a heat treatment function, and can heat the bumps 3 to about 130 ° C. to 180 ° C. at the time of forming processing for processing each bump 3 to a uniform height.

【００１４】また、図３に示すように、ガラスエポキシ
製のプリント配線板６には、半導体ベアチップ１の各バ
ンプ３が接合される位置に複数の電極７が設けられてい
る。半導体ベアチップ１の実装時には、この電極７を覆
うように液状の絶縁樹脂８がディスペンサ等により例え
ばポッティング塗布される。実装部分の封止材である絶
縁樹脂８は、エポキシ系又はフェノール系の材料等が主
成分であり、無論絶縁性を有する比較的粒子の粗いシリ
カ（二酸化ケイ素: ＳｉＯ2 ）質粉末であるフィラー９
が混合材として混入されている。As shown in FIG. 3, the printed wiring board 6 made of glass epoxy is provided with a plurality of electrodes 7 at positions where the bumps 3 of the semiconductor bare chip 1 are joined. When the semiconductor bare chip 1 is mounted, a liquid insulating resin 8 is applied by, for example, potting with a dispenser or the like so as to cover the electrodes 7. The insulating resin 8 serving as a sealing material for the mounting portion is mainly composed of an epoxy-based or phenol-based material, and is a filler which is a relatively coarse silica (silicon dioxide: SiO 2 ) powder having insulating properties. 9
Is mixed as a mixture.

【００１５】さらに、この絶縁樹脂８は、チップ１と配
線板６との接合部分の電気的な接続信頼性を向上させる
ことができるように半導体ベアチップ１とプリント配線
板６との熱膨張係数の差を考慮したものが用いられてい
る。すなわち、半導体ベアチップ１がＳｉチップである
ことから熱膨張係数は２．８ｐｐｍ／℃程度であり、一
方プリント配線板６はガラスエポキシ製なので熱膨張係
数は約１５ｐｐｍ／℃となることから、熱膨張係数の差
が５倍を超える大きなものとなってしまうが、本実施形
態では、熱膨張係数が約９ｐｐｍ／℃程度になるものを
絶縁樹脂８として用いており、チップ１と配線板６との
中間の値の熱膨張係数を有する絶縁樹脂８を、チップ１
と配線板６との接合部近傍の間隙に充填することで、各
部材の熱膨張係数の差を疑似的に低減し、温度変化によ
り接合部に発生する歪みを緩和させるとともに、半導体
ベアチップ１本体に悪影響（外部からの応力等）を与え
ないようにしている。Further, the insulating resin 8 has a coefficient of thermal expansion between the semiconductor bare chip 1 and the printed wiring board 6 so as to improve the electrical connection reliability of the joint between the chip 1 and the wiring board 6. Those that take the difference into account are used. That is, since the semiconductor bare chip 1 is a Si chip, the coefficient of thermal expansion is about 2.8 ppm / ° C., while the printed wiring board 6 is made of glass epoxy, so that the coefficient of thermal expansion is about 15 ppm / ° C. Although the difference in coefficient becomes as large as more than five times, in the present embodiment, a material having a thermal expansion coefficient of about 9 ppm / ° C. is used as the insulating resin 8. The insulating resin 8 having a thermal expansion coefficient of an intermediate value is
Filling the gap in the vicinity of the joint between the semiconductor bare chip 1 and the wiring board 6 reduces the difference in thermal expansion coefficient of each member in a simulated manner, alleviates the distortion generated at the joint due to a temperature change, and reduces the temperature of the semiconductor bare chip 1 itself. To prevent adverse effects (such as external stresses) from being exerted.

【００１６】次に、上述した半導体ベアチップを実際に
プリント配線板に実装する場合について説明する。Next, a case where the above-described semiconductor bare chip is actually mounted on a printed wiring board will be described.

【００１７】まず、図１に示すように、半導体ベアチッ
プ１の各電極２にバンプ３を形成する。次に、図２に示
すように、予め約１５０℃程度に加熱してある成形加工
型４を移動させ、彫込部５でバンプ３の先端部を押圧
し、個々のバンプ３を均一な高さに加工するとともに、
各バンプ３の先端部を円錐状に加工するフォーミング処
理を行う。この後、図３に示すように、予め電極７を覆
うように液状の絶縁樹脂８がディスペンサ等によりポッ
ティング塗布されたプリント配線板６に、半導体ベアチ
ップ１を実装する。この際、図４に示すように、加熱溶
融接合を行うためにチップ１のバンプ３と配線板６の電
極７とを接触させるときに、半導体ベアチップ１に円錐
状に形成されたバンプ３の先端部を、配線板６の電極７
上より絶縁樹脂８中のフィラー９を掻き分ける作用とし
て働かせることができるので、チップ１のバンプ３と配
線板６の電極７との間にフィラー９を介在させてしまう
ような恐れはなく、図５に示すように、半導体ベアチッ
プ１のバンプ３とプリント配線板６の電極７とを確実に
加熱溶融接合することができる。First, as shown in FIG. 1, a bump 3 is formed on each electrode 2 of a semiconductor bare chip 1. Next, as shown in FIG. 2, the molding die 4 which has been heated to about 150 ° C. in advance is moved, and the tip of the bump 3 is pressed by the engraved portion 5, so that each bump 3 is uniformly high. While processing to the
A forming process for processing the tip of each bump 3 into a conical shape is performed. Thereafter, as shown in FIG. 3, the semiconductor bare chip 1 is mounted on the printed wiring board 6 to which the liquid insulating resin 8 has been applied by potting with a dispenser or the like so as to cover the electrodes 7 in advance. At this time, as shown in FIG. 4, when the bumps 3 of the chip 1 and the electrodes 7 of the wiring board 6 are brought into contact with each other in order to perform the heat fusion bonding, the tip of the conical bump 3 formed on the semiconductor bare chip 1 is formed. To the electrode 7 of the wiring board 6
Since the filler 9 in the insulating resin 8 can be worked from above, it can act as a function of pushing out the filler 9, and there is no fear that the filler 9 is interposed between the bump 3 of the chip 1 and the electrode 7 of the wiring board 6. As shown in FIG. 5, the bumps 3 of the semiconductor bare chip 1 and the electrodes 7 of the printed wiring board 6 can be reliably heated and fused.

【００１８】このように、本実施形態の半導体チップの
実装方法によれば、半導体ベアチップ１に鋭角な先端を
有するバンプ３を形成した後、実装を行うものであるこ
とから、半導体ベアチップ１のバンプ３とプリント配線
板６の電極７との間に絶縁樹脂８に混合されたフィラー
９を介在させてしまうような可能性が低減され、半導体
ベアチップ１とプリント配線板６との電気的な接続信頼
性を向上させることが可能である。As described above, according to the method for mounting a semiconductor chip of the present embodiment, the bump 3 having an acute tip is formed on the semiconductor bare chip 1 and then mounted. The possibility that the filler 9 mixed in the insulating resin 8 is interposed between the semiconductor bare chip 1 and the electrode 7 of the printed wiring board 6 is reduced, and the electrical connection reliability between the semiconductor bare chip 1 and the printed wiring board 6 is reduced. It is possible to improve the performance.

【００１９】また、本実施形態の半導体チップの実装方
法は、前述したように、半導体ベアチップ１とプリント
配線板６との電気的な接続信頼性を向上させることが可
能なので、絶縁樹脂の材質、及び絶縁樹脂に混入する混
合材の材質を、チップの電極と基板の電極との接続性の
みにとらわれることなく、自由に選択することができ
る。したがって、絶縁樹脂８のように硬化後の熱膨張係
数の値が、半導体ベアチップ１の熱膨張係数の値とプリ
ント配線板６の熱膨張係数の値とのほぼ中間にある絶縁
樹脂を用い、チップ１と配線板６との接合部近傍の間隙
に、この絶縁樹脂を充填することで、チップ１の熱膨張
係数と配線板６の熱膨張係数との差が比較的大きい場合
であっても、この熱膨張係数の差を疑似的に低減し、実
装後において、温度変化によりチップ１と配線板６との
接合部に発生する歪みを、緩和することが可能となる。
これにより、温度変化による接合部の歪み防止対策とし
て、加工性又はコスト面で問題のある例えばアラミド樹
脂や石英ガラス布を基材に用いた基板材料（熱膨張係数
＝２〜７ｐｐｍ／℃）を敢えて使用する必要がなくな
る。The method of mounting a semiconductor chip according to the present embodiment can improve the reliability of electrical connection between the semiconductor bare chip 1 and the printed wiring board 6 as described above. Also, the material of the mixed material mixed into the insulating resin can be freely selected without being limited only to the connectivity between the electrode of the chip and the electrode of the substrate. Therefore, using an insulating resin such as the insulating resin 8 whose thermal expansion coefficient after curing is substantially in the middle between the value of the thermal expansion coefficient of the semiconductor bare chip 1 and the value of the thermal expansion coefficient of the printed wiring board 6, By filling this insulating resin into the gap near the joint between the first and the wiring board 6, even if the difference between the thermal expansion coefficient of the chip 1 and the thermal expansion coefficient of the wiring board 6 is relatively large, This difference in the coefficient of thermal expansion is reduced in a pseudo manner, and the distortion generated at the junction between the chip 1 and the wiring board 6 due to a temperature change after mounting can be reduced.
Thus, as a measure for preventing the joint from being distorted due to a temperature change, for example, a substrate material (thermal expansion coefficient = 2 to 7 ppm / ° C.) using aramid resin or quartz glass cloth as a base material, which has a problem in workability or cost, is used. There is no need to use it.

【００２０】[0020]

【発明の効果】以上説明したように、本発明の半導体チ
ップの実装方法によれば、バンプ等により形成された鋭
角な先端を有する半導体チップの電極を、基板の電極上
に塗布された絶縁樹脂を貫通させ当該基板の電極に確実
に接合することができる。すなわち、本発明の半導体チ
ップの実装方法は、絶縁樹脂中に例えばフィラー等の比
較的粒子の粗い混合材が混入されている場合でも、加熱
溶融接合を行うためにチップの電極と基板の電極とを接
触させる際に、半導体チップの電極の鋭角な先端部分
を、混合材の粒子を掻き分ける作用として働かせること
ができ、これにより、チップの電極と基板の電極との間
に混合材を介在させてしまうような可能性を低減し、半
導体チップと基板との電気的な接続信頼性を向上させる
ことが可能である。As described above, according to the method of mounting a semiconductor chip of the present invention, the electrode of the semiconductor chip having a sharp tip formed by a bump or the like is provided with the insulating resin coated on the electrode of the substrate. Can be penetrated to securely connect to the electrode of the substrate. That is, the method of mounting a semiconductor chip of the present invention, even when a relatively coarse mixed material such as a filler is mixed in the insulating resin, for example, to perform the heat fusion bonding between the chip electrode and the substrate electrode. When the contact is made, the sharp tip portion of the electrode of the semiconductor chip can act as an action of pushing out particles of the mixture material, whereby the mixture material is interposed between the electrode of the chip and the electrode of the substrate. It is possible to reduce the possibility that the semiconductor chip and the substrate are electrically connected, and to improve the reliability of electrical connection between the semiconductor chip and the substrate.

【００２１】また、本発明の半導体チップの実装方法
は、前述したように、半導体チップと基板との電気的な
接続信頼性を向上させることが可能なので、絶縁樹脂の
材質、及び絶縁樹脂に混入する混合材の材質を、チップ
の電極と基板の電極との接続性のみにとらわれることな
く、自由に選択することができる。したがって、本発明
は、硬化後の熱膨張係数の値が、例えば半導体チップの
熱膨張係数の値と基板のの熱膨張係数の値とのほぼ中間
にある絶縁樹脂を選択し、半導体チップと基板との接合
部近傍の間隙に、この選択した絶縁樹脂を充填すること
が可能である。これにより、実装された半導体チップの
熱膨張係数と基板の熱膨張係数との差が比較的大きい場
合であっても、この熱膨張係数の差を疑似的に低減し、
実装後において、温度変化によりチップと基板との接合
部に発生する歪みを、緩和することが可能となる。Further, as described above, the method for mounting a semiconductor chip of the present invention can improve the reliability of the electrical connection between the semiconductor chip and the substrate. The material of the mixed material to be used can be freely selected without being limited only to the connectivity between the electrode of the chip and the electrode of the substrate. Therefore, the present invention selects an insulating resin in which the value of the coefficient of thermal expansion after curing is, for example, approximately halfway between the value of the coefficient of thermal expansion of the semiconductor chip and the value of the coefficient of thermal expansion of the substrate, and It is possible to fill the selected insulating resin in the gap near the junction with the insulating resin. Thereby, even if the difference between the coefficient of thermal expansion of the mounted semiconductor chip and the coefficient of thermal expansion of the substrate is relatively large, the difference in the coefficient of thermal expansion is reduced in a pseudo manner,
After the mounting, it is possible to reduce the distortion generated at the junction between the chip and the substrate due to a temperature change.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形態にかかる、電極にバンプの形
成された半導体ベアチップを示す断面図。FIG. 1 is a sectional view showing a semiconductor bare chip having bumps formed on electrodes according to an embodiment of the present invention.

【図２】図１の半導体ベアチップに形成されたバンプに
フォーミング処理を施すための成形加工型を示す断面
図。FIG. 2 is a sectional view showing a molding die for performing a forming process on bumps formed on the semiconductor bare chip of FIG. 1;

【図３】電極に絶縁樹脂が塗布されたプリント配線板と
図２の成形加工型によってバンプがフォーミングされた
半導体ベアチップとを示す断面図。FIG. 3 is a cross-sectional view showing a printed wiring board in which an insulating resin is applied to electrodes and a semiconductor bare chip in which bumps are formed by a molding die of FIG. 2;

【図４】加熱溶融接合の際に、図２の半導体ベアチップ
のバンプと図３のプリント配線板の電極とを接触させる
ときの状態を示す断面図。FIG. 4 is a cross-sectional view showing a state where the bumps of the semiconductor bare chip of FIG. 2 and the electrodes of the printed wiring board of FIG.

【図５】図２の半導体ベアチップのバンプを図３のプリ
ント配線板の電極に実装したときの状態を示す断面図。FIG. 5 is a sectional view showing a state where the bumps of the semiconductor bare chip of FIG. 2 are mounted on the electrodes of the printed wiring board of FIG. 3;

【図６】電極にバンプの形成された従来の半導体ベアチ
ップを示す断面図。FIG. 6 is a sectional view showing a conventional semiconductor bare chip having bumps formed on electrodes.

【図７】図６の半導体ベアチップに形成されたバンプに
フラットニング処理を施すための成形加工型を示す断面
図。FIG. 7 is a sectional view showing a molding die for performing a flattening process on bumps formed on the semiconductor bare chip of FIG. 6;

【図８】電極に絶縁樹脂が塗布されたプリント配線板、
及び図７の成形加工型によってバンプがフラットニング
処理された半導体ベアチップを示す断面図。FIG. 8 is a printed wiring board in which an insulating resin is applied to electrodes;
FIG. 8 is a cross-sectional view showing a semiconductor bare chip in which bumps have been flattened by the molding die of FIG. 7 and FIG.

【図９】図７の半導体ベアチップのバンプと図８のプリ
ント配線板の電極との間に絶縁樹脂中のフィラーが介在
されたときの状態を示す断面図。9 is a cross-sectional view showing a state in which a filler in an insulating resin is interposed between the bumps of the semiconductor bare chip of FIG. 7 and the electrodes of the printed wiring board of FIG. 8;

【符号の説明】[Explanation of symbols]

１……半導体ベアチップ ２……半導体ベアチップの電極 ３……バンプ ４……成形加工型 ５……彫込部 ６……プリント配線板 ７……プリント配線板の電極 ８……絶縁樹脂 ９……フィラー DESCRIPTION OF SYMBOLS 1 ... Semiconductor bare chip 2 ... Electrode of semiconductor bare chip 3 ... Bump 4 ... Molding mold 5 ... Engraved part 6 ... Printed wiring board 7 ... Electrode of printed wiring board 8 ... Insulating resin 9 ... Filler

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップに鋭角な先端を有する電極
を形成する工程と、 基板に設けられた電極上に絶縁樹脂を塗布する工程と、 前記半導体チップに形成された鋭角な先端を有する前記
電極を、前記基板の電極上に塗布された前記絶縁樹脂を
貫通させ該基板の電極に接合する工程とを有することを
特徴とする半導体チップの実装方法。A step of forming an electrode having an acute tip on a semiconductor chip; a step of applying an insulating resin on an electrode provided on a substrate; and an electrode having an acute tip formed on the semiconductor chip. And bonding the insulating resin applied on the electrodes of the substrate to the electrodes of the substrate. 【請求項２】 半導体チップの電極に鋭角な先端を有す
るバンプを形成する工程と、 基板に設けられた電極上に絶縁樹脂を塗布する工程と、 前記半導体チップの電極に形成された鋭角な先端を有す
る前記バンプを、前記基板の電極上に塗布された前記絶
縁樹脂を貫通させ該基板の電極に接合する工程とを有す
ることを特徴とする半導体チップの実装方法。A step of forming a bump having a sharp tip on an electrode of the semiconductor chip; a step of applying an insulating resin on an electrode provided on a substrate; and a sharp tip formed on an electrode of the semiconductor chip. Bonding the bumps having the above structure to the electrodes of the substrate by penetrating the insulating resin applied on the electrodes of the substrate. 【請求項３】 請求項１又は２記載の半導体チップの実
装方法において、 前記絶縁樹脂の硬化後の熱膨張係数の値は、前記半導体
チップの熱膨張係数の値と前記基板の熱膨張係数の値と
の間にあることを特徴とする半導体チップの実装方法。3. The method of mounting a semiconductor chip according to claim 1, wherein a value of a thermal expansion coefficient of the insulating resin after curing is a value of a thermal expansion coefficient of the semiconductor chip and a value of a thermal expansion coefficient of the substrate. And mounting the semiconductor chip.
JP11031814A 1999-02-09 1999-02-09 Mounting method of semiconductor chip Withdrawn JP2000232130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11031814A JP2000232130A (en) 1999-02-09 1999-02-09 Mounting method of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11031814A JP2000232130A (en) 1999-02-09 1999-02-09 Mounting method of semiconductor chip

Publications (1)

Publication Number Publication Date
JP2000232130A true JP2000232130A (en) 2000-08-22

Family

ID=12341572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11031814A Withdrawn JP2000232130A (en) 1999-02-09 1999-02-09 Mounting method of semiconductor chip

Country Status (1)

Country Link
JP (1) JP2000232130A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311584A (en) * 2007-06-18 2008-12-25 Elpida Memory Inc Mounting structure of semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311584A (en) * 2007-06-18 2008-12-25 Elpida Memory Inc Mounting structure of semiconductor package

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