JP3893798B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP3893798B2
JP3893798B2 JP16329299A JP16329299A JP3893798B2 JP 3893798 B2 JP3893798 B2 JP 3893798B2 JP 16329299 A JP16329299 A JP 16329299A JP 16329299 A JP16329299 A JP 16329299A JP 3893798 B2 JP3893798 B2 JP 3893798B2
Authority
JP
Japan
Prior art keywords
electrode
semiconductor element
substrate
bonded
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16329299A
Other languages
Japanese (ja)
Other versions
JP2000353722A (en
Inventor
彰 斉藤
靖之 阪下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP16329299A priority Critical patent/JP3893798B2/en
Publication of JP2000353722A publication Critical patent/JP2000353722A/en
Application granted granted Critical
Publication of JP3893798B2 publication Critical patent/JP3893798B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はフリップチップ実装工法を用いて、半導体素子を基板等の被接合体にバンプ実装する半導体装置の製造方法に関するものであり、特に製造リードタイムを向上させることができる半導体装置の製造方法に関するものである。
【０００２】
【従来の技術】
近年、樹脂基板、セラミック基板等の半導体キャリアや半導体素子、またはプリント基板等のマザーボードヘのチップ実装技術として、主とする半導体素子をフリップチップ実装する工法が盛んに開発されている。
【０００３】
以下、従来のフリップチップ実装工法を用いた半導体装置の製造方法について図面を参照しながら説明する。
【０００４】
図１０〜図１８は、フリップチップ実装工法を用いた従来の半導体装置の製造方法を示す各工程ごとの断面図である。
【０００５】
まず図１０に示すように、フリップチップしようとする半導体素子１を用意する。そしてこの半導体素子１には、その主面の例えば周辺部に電極パッド（図示せず）が形成されているものである。
【０００６】
次に図１１に示すように、半導体素子１上の複数の電極パッド上にワイヤーボンド法により複数の突起電極２（バンプ）を形成する。
【０００７】
次に図１２に示すように、半導体素子１上の各電極パッド上に形成された突起電極２の頭頂部の高さを一定にそろえるためにバンプレベリングを行う。このレベリングでは、平坦板治具を用いた加圧によるレベリングを行う。この時点で突起電極２の高さは、概ね５０［μｍ］にレベリング調整されている。
【０００８】
次に図１３に示すように、半導体素子１のレベリングされた突起電極２の面を下にして、導電性接着剤３が形成されたディスク基板４に対して押圧し、そして引き上げ、突起電極２の先端部に導電性接着剤３を形成する。ここでディスク基板４上の導電性接着剤３は回転ディスクとブレードにより撹拌され、表面状態が均一な状態に維持されているものである。
【０００９】
図１４は半導体素子１上の各突起電極２上に導電性接着剤３が形成された状態を示している。そして導電性接着剤３は突起電極２の先端部のみに形成されているものである。
【００１０】
そして図１５に示すように、各突起電極２上に導電性接着剤３が形成された半導体素子１のその面を下にして、被接合基板５の表面上の電極６に対向させて位置合わせする。
【００１１】
そして図１６に示すように、位置合わせ後の半導体素子１と被接合基板５とを対向させ、突起電極２およびその先端に形成された導電性接着剤３と被接合基板５の表面の電極６とを押圧して接合する。この時点で被接合基板５の電極６と半導体素子１の突起電極２が接合するとともに、突起電極２の先端部に形成された導電性接着剤３と電極６とが接合する。
【００１２】
そして図１７に示すように、表面の電極６とその主面の突起電極２が接合された半導体素子１と被接合基板５との間隙に封止樹脂である絶縁性樹脂７をシリンジ８（注入針）により注入し、封止する。
【００１３】
そして図１８に示すように、半導体素子１上の突起電極２が導電性接着剤３を介して、被接合基板５の電極６と接合され、間隙が絶縁性樹脂７で封止され、フリップチップ実装された半導体装置を得ることができる。
【００１４】
【発明が解決しようとする課題】
しかしながら前記従来の半導体装置の製造方法では、１０［ｍｍ］×１０［ｍｍ］のサイズの半導体素子の場合では、製造リードタイム上、問題なく製造可能であるが、半導体素子のサイズが、５［ｍｍ］×５［ｍｍ］以下の例えば１［ｍｍ］×１［ｍｍ］程度の小チップである場合、その都度、チップ単位（半導体素子単位）で各製造工程を通じて半導体装置を製造しなければならず、フリップチップ実装における多量生産の実際の工場での量産工程においては、製造リードタイム上、解決すべき課題となっていた。
【００１５】
本発明は前記従来の課題を解決するものであり、量産工程において、小チップと称される半導体素子を用いて、多量生産可能なフリップチップ実装における半導体装置の製造方法を提供することを目的とする。
【００１６】
【課題を解決するための手段】
前記従来の課題を解決するために本発明の半導体装置の製造方法は、以下のような構成を有している。すなわち、本発明の製造方法は、サイズが５ｍｍ×５ｍｍ以下の半導体素子が複数形成された半導体ウェハーに対して、複数個の半導体素子を１つのチップブロックとし、前記チップブロックのサイズが５ｍｍ×５ｍｍより大きくなるように分割する工程と、前記チップブロックの各半導体素子の電極パッド上に突起電極を形成する工程と、前記チップブロックを個々の半導体素子に分割する工程と、前記半導体素子の前記突起電極が形成された面を導電性接着剤層が形成された基板に対して押圧し、引き上げることにより前記半導体素子の前記突起電極の先端部領域にのみ導電性接着剤を形成する工程と、前記半導体素子の前記導電性接着剤が形成された突起電極面と被接合基板の電極が形成された面とを対向させ、そして前記突起電極上の前記導電性接着剤を前記被接合基板の電極に接触させて押圧し、前記半導体素子上の前記突起電極と前記被接合基板上の電極とを接合する工程とよりなる半導体装置の製造方法である。
【００１７】
さらに具体的には、半導体素子の導電性接着剤が形成された突起電極面と被接合基板の電極が形成された面とを対向させ、そして前記突起電極上の前記導電性接着剤を前記被接合基板の電極に接触させて押圧し、前記半導体素子上の前記突起電極と前記被接合基板上の電極とを接合する工程の後に、前記半導体素子と前記被接合基板との間隙に絶縁性樹脂を注入し、前記絶縁性樹脂を硬化して樹脂封止する工程を付加する半導体装置の製造方法である。
【００１８】
また、半導体素子の電極パッド上に突起電極を形成する工程の後に、形成した前記突起電極の各頭頂部の高さを均一にそろえるために加圧によるレベリング工程を付加する半導体装置の製造方法である。
【００１９】
また、被接合基板は底面に複数のランド電極が形成され、そのランド電極と電気的に接続した電極をその表面に有する絶縁性の半導体キャリアである半導体装置の製造方法である。
【００２０】
また、被接合基板は第２の半導体素子である半導体装置の製造方法である。また、被接合基板はプリント基板等のマザー実装基板である半導体装置の製造方法である。
【００２２】
前記構成の通り、半導体素子の電極パッド上に突起電極を形成する際は、複数個の半導体素子よりなるチップブロックの状態で行い、その後は個別の半導体素子の状態で処理するものである。したがって、本発明の半導体装置の製造方法は、従来の製造工程と比較して、突起電極形成の際の製造タクトを大幅に短縮し、フリップチップ実装の製造リードタイムを短縮し、効果的な製造工程を実現することができる。
【００２３】
特に１枚の半導体ウェハー中に多数の半導体素子が形成された場合のように、１チップ当たりのサイズが小さい場合は、個々の半導体素子に対して突起電極を個別チップごとに形成すると、それだけ突起電極形成のための製造時間を要するものであり、本実施形態ではチップブロック状に対して突起電極を連続して形成してそのトータル処理時間を短縮することにより、全体として製造リードタイムを短縮できるものである。
【００２４】
【発明の実施の形態】
以下、本発明の半導体装置の製造方法の一実施形態について、図面を参照しながら説明する。
【００２５】
図１〜図９は本実施形態の半導体装置の製造方法を示す各工程ごとの断面図である。
【００２６】
まず図１に示すように、複数の半導体素子が形成された半導体ウェハー９を用意する。ここで用意する半導体ウェハー９は、５［ｍｍ］×５［ｍｍ］などの小チップの半導体素子が形成されたウェハーである。また半導体ウェハー９の半導体素子には、その主面の例えば周辺部に電極パッド（図示せず）が形成されているものである。もちろん、電極パッドは半導体素子の周辺部以外にも、中央部領域を含む素子領域全面に形成されている場合であってもよい。
【００２７】
次に図２に示すように、半導体ウェハー９に対して、複数個の半導体素子を１つのチップブロック１０としてダイシング（フルカット）により分割する。そしてそのチップブロック１０の各半導体素子１１上の複数の電極パッド上にワイヤーボンド法により複数の突起電極２（バンプ）を形成する。例えばチップサイズが５［ｍｍ］×５［ｍｍ］の小チップの場合は、４個を１つのチップブロックとして１０［ｍｍ］×１０［ｍｍ］の場合と同様な大きさを構成する。ここで突起電極２の形成では、ネイルヘッドボンディングにより、図示するようにスタッドバンプ（ＳＢＢ）と称される上部が下部よりも面積的に小さい二段突起電極を形成する。この時点では突起電極２の高さは、多少の高さバラツキがあるものの、概ね５０［μｍ］の高さである。なお、突起電極２の形成は、ワイヤーボンド法による形成以外、メッキ法、転写バンプ法により形成してもよい。また、この段階で形成した突起電極２の各突起電極２の頭頂部の高さを均一にするための治具による加圧レベリングを行う。
【００２８】
次に図３に示すように、突起電極２が形成されたチップブロック１０を個々の半導体素子１１に分割する。通常はダイシングによりフルカットして個片の半導体素子１１に分割する。
【００２９】
次に図４に示すように、個片化した半導体素子１１に形成された突起電極２の面を下にして、導電性接着剤３が形成されたディスク基板４に対して押圧し、そして引き上げ、突起電極２の先端部領域に導電性接着剤３を形成する。ここでディスク基板４上の導電性接着剤３は回転ブレードにより撹拌され、粘度等の表面状態を含む接着剤成分が均一な状態に維持されているものである。また、ディスク基板４上の導電性接着剤３の厚みは１７［μｍ］であり、突起電極２の高さは５０［μｍ］であり、上段部の高さは２８［μｍ］である。したがって導電性接着剤３の厚みは、突起電極２の先端部すなわち上段部の６０［％］に相当する膜厚に設定している。この条件で半導体素子１１の突起電極２を押圧させることにより、突起電極２の先端部のみに導電性接着剤３を形成することができる。実際には突起電極２の先端部から１０［μｍ］程度突出した量の導電性接着剤３が形成され、この突出量により、半導体素子１１を基板実装する際、基板自体の反り量を吸収して接合することができ、フェースダウン実装の信頼性を向上させることができる。
【００３０】
図５には、前記工程によって半導体素子１１の突起電極２の先端部領域のみに導電性接着剤３が形成された半導体素子１１の状態を示している。
【００３１】
次に図６に示すように、突起電極２の先端部に導電性接着剤３が形成された半導体素子１１のその面を下にして、被接合基板５の表面の電極６に対向させて位置合わせする。そして半導体素子１１を被接合基板５に対して押圧し、半導体素子１１上の突起電極２と被接合基板５上の電極６とを導電性接着剤３を介して接合する。
【００３２】
図７には、被接合基板５の電極６と半導体素子１１とが導電性接着剤３を介した突起電極２で接合された状態を示している。
【００３３】
そして図８に示すように、表面の電極６とその主面の突起電極２が接合された半導体素子１１と被接合基板５との間隙に封止樹脂である絶縁性樹脂７をシリンジ８（注入針）により注入し、封止する。この工程では、被接合基板５の電極６と導電性接着剤３を介した突起電極２で接合された半導体素子１１の接合体を基台に載置し、その基台を傾けた状態で絶縁性樹脂７を注入し、ボイドの発生をなくして樹脂を間隙に充填封止するものである。
【００３４】
そして図９に示すように、半導体素子１１上の突起電極２が導電性接着剤３を介して、被接合基板５の電極６と接合され、間隙が絶縁性樹脂７で封止され、フリップチップ実装された半導体装置を得ることができる。
【００３５】
本実施形態では、半導体素子１１と被接合基板５とを絶縁性樹脂７を介して接合して後、その絶縁性樹脂７を熱硬化させる工程を有するものである。本実施形態では、絶縁性樹脂７は、エポキシ樹脂を主成分とする熱硬化型樹脂である。また本実施形態では熱硬化の温度は１５０［℃］である。この絶縁性樹脂７の熱硬化によって、半導体素子１１上の突起電極２と被接合基板５の電極６との接合を保持し、電気的接続を形成するものである。
【００３６】
また本実施形態では、被接合基板５としては、底面に複数の外部接続用のランド電極が形成され、そのランド電極と内部ビアによって電気的に接続した電極をその表面に有する絶縁性基材よりなる半導体キャリアであり、また被接合基板５は別の第２の半導体素子であってもよい、さらに、被接合基板５は、プリント基板等のマザー実装基板であってもよい。
【００３７】
また前記した本実施形態の半導体装置の製造方法を応用することにより、一定個数の半導体素子のチップブロックに加えて、半導体素子の個数に対応した被接合基板をも基板ブロックとして用い、複数対複数でフリップチップ実装することにより、製造リードタイムを短縮することができる。すなわち、複数の半導体素子が形成された半導体ウェハーに対して、複数個の半導体素子を１つのチップブロックとして分割し、そのチップブロックの各半導体素子の電極パッド上に突起電極を形成し、チップブロックの各半導体素子の突起電極が形成された面を導電性接着剤層が形成された基板に対して押圧し、引き上げることにより半導体素子の突起電極の先端部領域にのみ導電性接着剤を形成し、チップブロックの各半導体素子の導電性接着剤が形成された突起電極面と被接合基板の電極が形成された面とを対向させ、そして突起電極上の導電性接着剤を被接合基板の電極に接触させて押圧し、半導体素子上の突起電極と被接合基板上の電極とを接合し、そしてチップブロックの各半導体素子の突起電極が導電性接着剤を介して被接合基板の電極に接合された半導体ブロックに対して、チップブロックと被接合基板との間隙に絶縁性樹脂を注入し、樹脂封止し、チップブロックの個々の半導体素子ごとに分割し、半導体装置を得ることができる。
【００３８】
以上、本実施形態では、半導体素子１１の電極パッド上に突起電極２を形成する際は、複数個の半導体素子１１よりなるチップブロック１０の状態で行い、その後は個別の半導体素子の状態で処理するものである。したがって、本実施形態の半導体装置の製造方法は、従来の製造工程と比較して、突起電極形成の際の製造タクトを大幅に短縮し、フリップチップ実装の製造リードタイムを短縮し、効果的な製造工程を実現することができる。特に１枚の半導体ウェハー中に多数の半導体素子が形成された場合のように、１チップ当たりのサイズが小さい場合はそれだけ突起電極形成のための製造時間を要するものであり、本実施形態ではその時間を短縮することにより、全体として製造リードタイムを短縮できるものである。さらにチップブロック化することにより、小チップ対応のための製造設備の変更、新規な設備投資をすることなく、大幅なコストアップなく製造できるものである。
【００３９】
【発明の効果】
以上、本発明の半導体装置の製造方法により、１チップ処理ではなく、複数個のチップブロックとして処理することにより、搬送、位置合わせ等の処理時間を省略し、製造リードタイムを大幅に短縮し、効果的な製造工程を実現することができる。そして本発明の半導体装置の製造方法は、従来の製造工程と比較して、特に１枚の半導体ウェハー中に多数の半導体素子が形成された場合のように、１チップ当たりのサイズが小さい場合は、個々の半導体素子に対して突起電極を個別チップごとに形成すると、それだけ突起電極形成のための製造時間を要するものであり、本実施形態ではチップブロック状に対して突起電極を連続して形成してそのトータル処理時間を短縮することにより、全体として製造リードタイムを短縮できるものである。
【図面の簡単な説明】
【図１】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図２】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図３】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図４】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図５】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図６】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図７】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図８】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図９】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図１０】従来の半導体装置の製造方法を示す断面図
【図１１】従来の半導体装置の製造方法を示す断面図
【図１２】従来の半導体装置の製造方法を示す断面図
【図１３】従来の半導体装置の製造方法を示す断面図
【図１４】従来の半導体装置の製造方法を示す断面図
【図１５】従来の半導体装置の製造方法を示す断面図
【図１６】従来の半導体装置の製造方法を示す断面図
【図１７】従来の半導体装置の製造方法を示す断面図
【図１８】従来の半導体装置の製造方法を示す断面図
【符号の説明】
１ 半導体素子
２ 突起電極
３ 導電性接着剤
４ ディスク基板
５ 被接合基板
６ 電極
７ 絶縁性樹脂
８ シリンジ
９ 半導体ウェハー
１０ チップブロック
１１ 半導体素子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor element is bump-mounted on an object to be bonded such as a substrate using a flip chip mounting method, and more particularly to a method of manufacturing a semiconductor device capable of improving manufacturing lead time. Is.
[0002]
[Prior art]
In recent years, as a chip mounting technique on a semiconductor carrier such as a resin substrate or a ceramic substrate, a semiconductor element, or a mother board such as a printed circuit board, a method for flip-chip mounting a main semiconductor element has been actively developed.
[0003]
Hereinafter, a semiconductor device manufacturing method using a conventional flip chip mounting method will be described with reference to the drawings.
[0004]
10 to 18 are cross-sectional views for each process showing a conventional method of manufacturing a semiconductor device using a flip chip mounting method.
[0005]
First, as shown in FIG. 10, a semiconductor element 1 to be flip-chip is prepared. The semiconductor element 1 has an electrode pad (not shown) formed on, for example, a peripheral portion of the main surface thereof.
[0006]
Next, as shown in FIG. 11, a plurality of protruding electrodes 2 (bumps) are formed on the plurality of electrode pads on the semiconductor element 1 by wire bonding.
[0007]
Next, as shown in FIG. 12, bump leveling is performed in order to make the heights of the tops of the protruding electrodes 2 formed on the electrode pads on the semiconductor element 1 constant. In this leveling, leveling by pressurization using a flat plate jig is performed. At this time, the height of the protruding electrode 2 is adjusted to approximately 50 [μm].
[0008]
Next, as shown in FIG. 13, the leveled protruding electrode 2 of the semiconductor element 1 is faced down, pressed against the disk substrate 4 on which the conductive adhesive 3 is formed, and then lifted up. Conductive adhesive 3 is formed at the tip of the substrate. Here, the conductive adhesive 3 on the disk substrate 4 is agitated by a rotating disk and a blade, and the surface state is maintained in a uniform state.
[0009]
FIG. 14 shows a state in which the conductive adhesive 3 is formed on each protruding electrode 2 on the semiconductor element 1. The conductive adhesive 3 is formed only at the tip of the protruding electrode 2.
[0010]
Then, as shown in FIG. 15, the surface of the semiconductor element 1 on which the conductive adhesive 3 is formed on each protruding electrode 2 is faced down to face the electrode 6 on the surface of the substrate 5 to be bonded. To do.
[0011]
Then, as shown in FIG. 16, the aligned semiconductor element 1 and the substrate to be bonded 5 are opposed to each other, the protruding electrode 2, the conductive adhesive 3 formed at the tip thereof, and the electrode 6 on the surface of the substrate to be bonded 5. And are joined. At this time, the electrode 6 of the substrate to be bonded 5 and the protruding electrode 2 of the semiconductor element 1 are bonded, and the conductive adhesive 3 formed at the tip of the protruding electrode 2 and the electrode 6 are bonded.
[0012]
Then, as shown in FIG. 17, an insulating resin 7 as a sealing resin is injected into a gap between the semiconductor element 1 to which the electrode 6 on the surface and the protruding electrode 2 on the main surface are bonded and the substrate 5 to be bonded. Inject with a needle) and seal.
[0013]
Then, as shown in FIG. 18, the protruding electrode 2 on the semiconductor element 1 is bonded to the electrode 6 of the substrate to be bonded 5 through the conductive adhesive 3, the gap is sealed with the insulating resin 7, and the flip chip A mounted semiconductor device can be obtained.
[0014]
[Problems to be solved by the invention]
However, in the conventional method for manufacturing a semiconductor device, in the case of a semiconductor element having a size of 10 [mm] × 10 [mm], the semiconductor device can be manufactured without any problem in terms of manufacturing lead time. In the case of a small chip of, for example, about 1 [mm] × 1 [mm], which is equal to or less than [mm] × 5 [mm], a semiconductor device must be manufactured through each manufacturing process in units of chips (units of semiconductor elements) each time. First, in the mass production process at the actual factory of mass production in flip chip mounting, it has been a problem to be solved in terms of manufacturing lead time.
[0015]
An object of the present invention is to solve the above-described conventional problems, and to provide a method for manufacturing a semiconductor device in flip-chip mounting capable of mass production using a semiconductor element called a small chip in a mass production process. To do.
[0016]
[Means for Solving the Problems]
In order to solve the above-described conventional problems, a semiconductor device manufacturing method of the present invention has the following configuration. That is, the production method of the present invention, the semiconductor wafer size is 5mm × 5mm below the semiconductor element formed with a plurality, the plurality of semiconductor elements as one chip block, size 5mm × 5mm of the chip block A step of dividing the chip block into individual semiconductor elements, a step of forming a protruding electrode on an electrode pad of each semiconductor element of the chip block, a step of dividing the chip block into individual semiconductor elements, and the protrusion of the semiconductor element Forming the conductive adhesive only in the tip region of the protruding electrode of the semiconductor element by pressing the surface on which the electrode is formed against the substrate on which the conductive adhesive layer is formed and pulling up the surface; The protruding electrode surface on which the conductive adhesive of the semiconductor element is formed and the surface on which the electrode of the bonded substrate is formed are opposed to each other, and on the protruding electrode A method of manufacturing a semiconductor device, comprising: pressing the conductive adhesive in contact with an electrode of the substrate to be bonded, and bonding the protruding electrode on the semiconductor element and the electrode on the substrate to be bonded. .
[0017]
More specifically, the protruding electrode surface on which the conductive adhesive of the semiconductor element is formed and the surface on which the electrode of the bonded substrate is formed are opposed to each other, and the conductive adhesive on the protruding electrode is applied to the covered electrode. Insulating resin in the gap between the semiconductor element and the bonded substrate after the step of contacting and pressing the electrode of the bonded substrate to bond the protruding electrode on the semiconductor element and the electrode on the bonded substrate The semiconductor device is manufactured by adding a step of curing the insulating resin and sealing the resin.
[0018]
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a leveling step by pressurization is added after the step of forming a protruding electrode on an electrode pad of a semiconductor element so that the heights of the tops of the protruding electrodes formed are uniform. is there.
[0019]
Further, the bonded substrate is a method of manufacturing a semiconductor device which is an insulating semiconductor carrier having a plurality of land electrodes formed on the bottom surface and having electrodes on the surface electrically connected to the land electrodes.
[0020]
Further, the bonded substrate is a method for manufacturing a semiconductor device which is a second semiconductor element. Further, the bonded substrate is a method for manufacturing a semiconductor device which is a mother mounting substrate such as a printed circuit board.
[0022]
As described above, when the protruding electrode is formed on the electrode pad of the semiconductor element, it is performed in the state of a chip block composed of a plurality of semiconductor elements, and thereafter, the processing is performed in the state of individual semiconductor elements. Therefore, the manufacturing method of the semiconductor device of the present invention greatly reduces the manufacturing tact when forming the bump electrode, shortens the manufacturing lead time of the flip chip mounting, and effectively manufactures compared to the conventional manufacturing process. A process can be realized.
[0023]
In particular, when a large number of semiconductor elements are formed in one semiconductor wafer, and when the size per chip is small, if the protruding electrode is formed for each individual semiconductor element for each individual chip, the protrusion is increased accordingly. Manufacturing time for electrode formation is required, and in this embodiment, the manufacturing lead time can be reduced as a whole by continuously forming the protruding electrodes on the chip block shape and reducing the total processing time. Is.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings.
[0025]
1 to 9 are cross-sectional views for each process showing the method of manufacturing a semiconductor device of this embodiment.
[0026]
First, as shown in FIG. 1, a semiconductor wafer 9 on which a plurality of semiconductor elements are formed is prepared. The semiconductor wafer 9 prepared here is a wafer on which small chip semiconductor elements such as 5 [mm] × 5 [mm] are formed. The semiconductor element of the semiconductor wafer 9 has an electrode pad (not shown) formed on, for example, the peripheral portion of the main surface thereof. Of course, the electrode pad may be formed on the entire surface of the element region including the central region other than the peripheral portion of the semiconductor element.
[0027]
Next, as shown in FIG. 2, a plurality of semiconductor elements are divided into one chip block 10 by dicing (full cut) on the semiconductor wafer 9. Then, a plurality of protruding electrodes 2 (bumps) are formed on the plurality of electrode pads on each semiconductor element 11 of the chip block 10 by wire bonding. For example, in the case of a small chip having a chip size of 5 [mm] × 5 [mm], the same size as that of 10 [mm] × 10 [mm] is formed with four chips as one chip block. Here, in the formation of the protruding electrode 2, a two-step protruding electrode whose upper portion called a stud bump (SBB) is smaller in area than the lower portion is formed by nail head bonding. At this time, the height of the protruding electrode 2 is approximately 50 [μm] although there is some height variation. The protruding electrode 2 may be formed by a plating method or a transfer bump method, other than the wire bonding method. Further, pressure leveling is performed with a jig for making the height of the top of each protruding electrode 2 of the protruding electrode 2 formed at this stage uniform.
[0028]
Next, as shown in FIG. 3, the chip block 10 on which the protruding electrodes 2 are formed is divided into individual semiconductor elements 11. Usually, it is fully cut by dicing and divided into individual semiconductor elements 11.
[0029]
Next, as shown in FIG. 4, the protruding electrode 2 formed on the separated semiconductor element 11 is faced down, pressed against the disk substrate 4 on which the conductive adhesive 3 is formed, and then lifted. The conductive adhesive 3 is formed on the tip end region of the protruding electrode 2. Here, the conductive adhesive 3 on the disk substrate 4 is agitated by a rotating blade, and the adhesive component including the surface state such as viscosity is maintained in a uniform state. Further, the thickness of the conductive adhesive 3 on the disk substrate 4 is 17 [μm], the height of the protruding electrode 2 is 50 [μm], and the height of the upper portion is 28 [μm]. Therefore, the thickness of the conductive adhesive 3 is set to a film thickness corresponding to 60 [%] of the tip portion, that is, the upper step portion of the protruding electrode 2. By pressing the protruding electrode 2 of the semiconductor element 11 under these conditions, the conductive adhesive 3 can be formed only on the tip of the protruding electrode 2. Actually, the conductive adhesive 3 is formed in an amount protruding about 10 [μm] from the tip of the protruding electrode 2, and this protruding amount absorbs the amount of warpage of the substrate itself when the semiconductor element 11 is mounted on the substrate. And the reliability of face-down mounting can be improved.
[0030]
FIG. 5 shows a state of the semiconductor element 11 in which the conductive adhesive 3 is formed only in the tip region of the protruding electrode 2 of the semiconductor element 11 by the above process.
[0031]
Next, as shown in FIG. 6, the surface of the semiconductor element 11 having the conductive adhesive 3 formed on the tip end portion of the protruding electrode 2 is faced down to face the electrode 6 on the surface of the bonded substrate 5. Match. Then, the semiconductor element 11 is pressed against the substrate to be bonded 5, and the protruding electrode 2 on the semiconductor element 11 and the electrode 6 on the substrate to be bonded 5 are bonded via the conductive adhesive 3.
[0032]
FIG. 7 shows a state in which the electrode 6 of the substrate to be bonded 5 and the semiconductor element 11 are bonded by the protruding electrode 2 with the conductive adhesive 3 interposed therebetween.
[0033]
Then, as shown in FIG. 8, an insulating resin 7 as a sealing resin is injected into the gap between the semiconductor element 11 to which the surface electrode 6 and the protruding electrode 2 on the main surface are bonded and the substrate 5 to be bonded. Inject with a needle) and seal. In this step, a bonded body of the semiconductor element 11 bonded to the electrode 6 of the substrate to be bonded 5 and the protruding electrode 2 via the conductive adhesive 3 is placed on the base, and the base is tilted and insulated. The resin 7 is injected to eliminate voids and fill and seal the resin in the gap.
[0034]
Then, as shown in FIG. 9, the protruding electrode 2 on the semiconductor element 11 is bonded to the electrode 6 of the substrate to be bonded 5 through the conductive adhesive 3, the gap is sealed with the insulating resin 7, and the flip chip A mounted semiconductor device can be obtained.
[0035]
In this embodiment, the semiconductor element 11 and the to-be-joined substrate 5 are joined through the insulating resin 7 and then the step of thermosetting the insulating resin 7 is included. In this embodiment, the insulating resin 7 is a thermosetting resin whose main component is an epoxy resin. In this embodiment, the thermosetting temperature is 150 [° C.]. By thermal curing of the insulating resin 7, the bonding between the protruding electrode 2 on the semiconductor element 11 and the electrode 6 of the substrate to be bonded 5 is maintained and an electrical connection is formed.
[0036]
In the present embodiment, the bonded substrate 5 is formed of an insulating base material having a plurality of external connection land electrodes formed on the bottom surface and an electrode electrically connected to the land electrode by an internal via on the surface. The bonded substrate 5 may be another second semiconductor element. Further, the bonded substrate 5 may be a mother mounting substrate such as a printed circuit board.
[0037]
Further, by applying the semiconductor device manufacturing method of the present embodiment described above, in addition to a predetermined number of semiconductor element chip blocks, a substrate to be bonded corresponding to the number of semiconductor elements is also used as a substrate block. Thus, the manufacturing lead time can be shortened by flip-chip mounting. That is, for a semiconductor wafer on which a plurality of semiconductor elements are formed, the plurality of semiconductor elements are divided into one chip block, and a protruding electrode is formed on the electrode pad of each semiconductor element of the chip block. The surface on which the protruding electrode of each semiconductor element is formed is pressed against the substrate on which the conductive adhesive layer is formed and pulled up to form a conductive adhesive only in the tip end region of the protruding electrode of the semiconductor element. The protruding electrode surface on which the conductive adhesive of each semiconductor element of the chip block is formed is opposed to the surface on which the electrode of the bonded substrate is formed, and the conductive adhesive on the protruding electrode is applied to the electrode of the bonded substrate. The bump electrode on the semiconductor element and the electrode on the substrate to be bonded are bonded, and the bump electrode of each semiconductor element of the chip block is bonded via a conductive adhesive. Insulating resin is injected into the gap between the chip block and the substrate to be bonded to the semiconductor block bonded to the electrode of the plate, resin-sealed, and divided into individual semiconductor elements of the chip block. Obtainable.
[0038]
As described above, in the present embodiment, when the protruding electrode 2 is formed on the electrode pad of the semiconductor element 11, it is performed in the state of the chip block 10 including the plurality of semiconductor elements 11, and thereafter, the processing is performed in the state of individual semiconductor elements. To do. Therefore, the manufacturing method of the semiconductor device of this embodiment significantly reduces the manufacturing tact when forming the protruding electrode, and shortens the manufacturing lead time of the flip chip mounting compared with the conventional manufacturing process, and is effective. A manufacturing process can be realized. Particularly, when a large number of semiconductor elements are formed in one semiconductor wafer, when the size per chip is small, the manufacturing time for forming the protruding electrode is required. By reducing the time, the manufacturing lead time can be shortened as a whole. Further, by making a chip block, it is possible to manufacture without significant cost increase without changing manufacturing equipment for small chips and investing in new equipment.
[0039]
【The invention's effect】
As described above, by processing the semiconductor device according to the present invention as a plurality of chip blocks instead of one chip processing, processing time such as conveyance and alignment is omitted, and manufacturing lead time is greatly reduced. An effective manufacturing process can be realized. The semiconductor device manufacturing method of the present invention is smaller than the conventional manufacturing process when the size per one chip is small, particularly when a large number of semiconductor elements are formed in one semiconductor wafer. When the bump electrodes are formed for each individual chip for each semiconductor element, it takes much time to form the bump electrodes. In this embodiment, the bump electrodes are continuously formed on the chip block shape. By reducing the total processing time, the manufacturing lead time can be reduced as a whole.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 10 is a cross-sectional view showing a method for manufacturing a conventional semiconductor device. Sectional drawing which shows the manufacturing method of the semiconductor device of FIG. FIG. 13 is a sectional view showing a conventional method for manufacturing a semiconductor device. FIG. 14 is a sectional view showing a method for manufacturing a conventional semiconductor device. FIG. 15 is a sectional view showing a method for manufacturing a conventional semiconductor device. 16 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device. FIG. 17 is a cross-sectional view showing a method for manufacturing a conventional semiconductor device. FIG. 18 is a cross-sectional view showing a method for manufacturing a conventional semiconductor device.
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Protruding electrode 3 Conductive adhesive 4 Disc substrate 5 Bonded substrate 6 Electrode 7 Insulating resin 8 Syringe 9 Semiconductor wafer 10 Chip block 11 Semiconductor element

Claims (6)

サイズが５ｍｍ×５ｍｍ以下の半導体素子が複数形成された半導体ウェハーに対して、複数個の半導体素子を１つのチップブロックとし、前記チップブロックのサイズが５ｍｍ×５ｍｍより大きくなるように分割する工程と、前記チップブロックの各半導体素子の電極パッド上に突起電極を形成する工程と、前記チップブロックを個々の半導体素子に分割する工程と、前記半導体素子の前記突起電極が形成された面を導電性接着剤層が形成された基板に対して押圧し、引き上げることにより前記半導体素子の前記突起電極の先端部領域にのみ導電性接着剤を形成する工程と、前記半導体素子の前記導電性接着剤が形成された突起電極面と被接合基板の電極が形成された面とを対向させ、そして前記突起電極上の前記導電性接着剤を前記被接合基板の電極に接触させて押圧し、前記半導体素子上の前記突起電極と前記被接合基板上の電極とを接合する工程とよりなることを特徴とする半導体装置の製造方法。The semiconductor wafer size is 5mm × 5mm below the semiconductor element formed with a plurality, the plurality of semiconductor elements as one chip block, the step size of the chip block is divided so as to be larger than 5mm × 5mm A step of forming a protruding electrode on an electrode pad of each semiconductor element of the chip block; a step of dividing the chip block into individual semiconductor elements; and a surface of the semiconductor element on which the protruding electrode is formed is conductive. A step of forming a conductive adhesive only in a tip region of the protruding electrode of the semiconductor element by pressing against the substrate on which the adhesive layer is formed and pulling up; and the conductive adhesive of the semiconductor element The formed protruding electrode surface and the surface on which the electrode of the bonded substrate is formed are opposed to each other, and the conductive adhesive on the protruding electrode is bonded to the bonded substrate A method of manufacturing a semiconductor device, comprising: pressing a contacted electrode on a plate to bond the protruding electrode on the semiconductor element and the electrode on the bonded substrate. 半導体素子の導電性接着剤が形成された突起電極面と被接合基板の電極が形成された面とを対向させ、そして前記突起電極上の前記導電性接着剤を前記被接合基板の電極に接触させて押圧し、前記半導体素子上の前記突起電極と前記被接合基板上の電極とを接合する工程の後に、前記半導体素子と前記被接合基板との間隙に絶縁性樹脂を注入し、前記絶縁性樹脂を硬化して樹脂封止する工程を付加することを特徴とする請求項１に記載の半導体装置の製造方法。The protruding electrode surface on which the conductive adhesive of the semiconductor element is formed and the surface on which the electrode of the bonded substrate is formed face each other, and the conductive adhesive on the protruding electrode contacts the electrode of the bonded substrate And pressing, and after the step of bonding the protruding electrode on the semiconductor element and the electrode on the substrate to be bonded, an insulating resin is injected into the gap between the semiconductor element and the substrate to be bonded. The method for manufacturing a semiconductor device according to claim 1 , further comprising a step of curing the resin and sealing the resin. 半導体素子の電極パッド上に突起電極を形成する工程の後に、形成した前記突起電極の各頭頂部の高さを均一にそろえるために加圧によるレベリング工程を付加することを特徴とする請求項１に記載の半導体装置の製造方法。Claim, characterized in adding the leveling process by the pressure in order to align after the step of forming a protruding electrode on the electrode pads of the semiconductor element, the height of each top portion of the formed the protruding electrodes uniformly 1 The manufacturing method of the semiconductor device as described in any one of Claims 1-3. 被接合基板は底面に複数のランド電極が形成され、そのランド電極と電気的に接続した電極をその表面に有する絶縁性の半導体キャリアであることを特徴とする請求項１に記載の半導体装置の製造方法。2. The semiconductor device according to claim 1 , wherein the bonded substrate is an insulating semiconductor carrier having a plurality of land electrodes formed on a bottom surface and an electrode electrically connected to the land electrode on the surface. Production method. 被接合基板は第２の半導体素子であることを特徴とする請求項１または請求項３に記載の半導体装置の製造方法。Manufacturing method of the bonded substrate is a semiconductor device according to claim 1 or claim 3, characterized in that the second semiconductor element. 被接合基板はプリント基板等のマザー実装基板であることを特徴とする請求項１に記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1 , wherein the substrate to be bonded is a mother mounting substrate such as a printed circuit board.
JP16329299A 1999-06-10 1999-06-10 Manufacturing method of semiconductor device Expired - Fee Related JP3893798B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16329299A JP3893798B2 (en) 1999-06-10 1999-06-10 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16329299A JP3893798B2 (en) 1999-06-10 1999-06-10 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2000353722A JP2000353722A (en) 2000-12-19
JP3893798B2 true JP3893798B2 (en) 2007-03-14

Family

ID=15771064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16329299A Expired - Fee Related JP3893798B2 (en) 1999-06-10 1999-06-10 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP3893798B2 (en)

Also Published As

Publication number Publication date
JP2000353722A (en) 2000-12-19

Similar Documents

Publication Publication Date Title
US7598121B2 (en) Method of manufacturing a semiconductor device
JP3819851B2 (en) Semiconductor device and manufacturing method thereof
US6555917B1 (en) Semiconductor package having stacked semiconductor chips and method of making the same
WO2002103793A1 (en) Semiconductor device and manufacturing method thereof
US20030036219A1 (en) Semiconductor device manufacturing method
JP2002033411A (en) Semiconductor device with heat spreader and its manufacturing method
JP2907188B2 (en) Semiconductor device, method of mounting semiconductor device, and method of manufacturing semiconductor device
JP2002270717A (en) Semiconductor device
JP3561209B2 (en) Flip chip mounting binder and method of manufacturing semiconductor device using the same
KR100533847B1 (en) Stacked flip chip package using carrier tape
JP2002110856A (en) Manufacturing method of semiconductor device
JP3893798B2 (en) Manufacturing method of semiconductor device
JPH10154726A (en) Semiconductor device and its manufacture
JP3370842B2 (en) Semiconductor device mounting structure
JP2001176908A (en) Manufacturing method of semiconductor device
JPH09172021A (en) Semiconductor device and manufacturing method and packaging method thereof
JP2002237566A (en) Three-dimensional mounting structure of semiconductor device, and method of manufacturing the same
JP2000357713A (en) Manufacture of semiconductor device
JP2002009111A (en) Method for mounting semiconductor flip chip
JP4331179B2 (en) Semiconductor device
JPH11204572A (en) Mounting structure of semiconductor device and manufacture thereof
JP2000332052A (en) Manufacture of semiconductor device, and the semiconductor device
JPH11224888A (en) Semiconductor device and its manufacturing
JP2002299548A (en) Laminated semiconductor device and manufacturing method therefor
JP2005311209A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050317

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20050629

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060721

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060725

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060906

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061003

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061026

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061121

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20061204

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091222

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101222

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees