JP2000223711A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the reliability the same as or higher than that of a MOS transistor by forming a second impurity region and a plurality channel formation regions so that these regions may overlap a gate electrode through a gate insulating film. SOLUTION: Considering the driving voltages of an n-channel TFT 204 of a pixel matrix circuit and n-channel TFTs 201, 202, 203 of a CMOS circuit, a second impurity region and a third impurity region, both of which will become LDD regions, can be easily differentiated in length in the channel length direction on one and the same substrate to be formed into the most appropriate shape for each TFT which constitutes each circuit, In a TFT of a single-gate multichannel structure wherein a plurality of channel formation regions divided by low density impurity regions which will become LDD regions are formed for one gate electrode, the number of channel formation regions and the number of second impurity regions corresponding to one gate electrode can be determined based on characteristics of a TFT to be fabricated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of thin film transistors on a substrate having an insulating surface, and a method for manufacturing the same. For example, the present invention relates to a configuration of an electro-optical device typified by a liquid crystal display device and an electronic apparatus equipped with the electro-optical device. Note that in this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic apparatus equipped with the electro-optical device in its category.

[0002]

2. Description of the Related Art A semiconductor device having a large-area integrated circuit formed by a thin film transistor (hereinafter, referred to as a TFT) on a substrate having an insulating surface is being developed. Active matrix liquid crystal display devices, EL display devices, and contact image sensors are known as typical examples. T
FTs are classified according to their structure and manufacturing method. In particular, a TFT in which a semiconductor film having a crystalline structure is used as an active layer
(Crystalline TFT) has high field-effect mobility, so that various functional circuits could be formed.

For example, an active matrix type liquid crystal display device includes a pixel matrix circuit composed of n-channel TFTs for each functional block, a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like. Was formed on one substrate. In the contact type image sensor, integrated circuits such as a sample hold circuit, a shift register circuit, and a multiplexer circuit are formed using TFTs.

Since the operating conditions of these circuits are not always the same, the characteristics required for the TFT naturally differed to some extent. The pixel matrix circuit has a configuration in which a switch element including an n-channel TFT and an auxiliary storage capacitor are provided, and a liquid crystal is driven by applying a voltage. Here, the liquid crystal needs to be driven by an alternating current, and a method called frame inversion driving has been adopted. Therefore, the required TFT characteristics required that the leakage current be sufficiently reduced. Further, since a high driving voltage is applied to the buffer circuit, it is necessary to increase the breakdown voltage. Further, in order to enhance the current driving capability, it is necessary to secure a sufficient ON current.

However, there is a problem that the off current of the crystalline TFT tends to be high. And crystalline TF
It is said that T still falls short of MOS transistors (transistors manufactured on a single crystal semiconductor substrate) used for LSIs and the like in terms of reliability. For example, crystalline TFT
In some cases, a deterioration phenomenon such as a decrease in on-current was observed. The cause is the hot carrier effect, and it has been considered that hot carriers generated by a high electric field near the drain cause a deterioration phenomenon.

The structure of the TFT includes a low-concentration drain (LD)
D: Lightly Doped Drain) structure is known. In this structure, a low-concentration impurity region is provided between a channel region and a source or drain region to which a high-concentration impurity is added.
This is called the D region. The LDD structure further includes a GOLD (Gate-drain Overlapped LDD) structure that overlaps with the gate electrode and an offset LDD structure that does not overlap with the gate electrode, depending on the positional relationship with the gate electrode. The GOLD structure was able to reduce the high electric field near the drain, prevent the hot carrier effect, and improve the reliability. For example, "Mutsuko Hatano, Hajime Ak
imoto and Takeshi Sakai, IEDM97 TECHNICAL DIGE
ST, p523-526, 1997] has a GOLD structure with sidewalls made of silicon, but TFTs with other structures
It has been confirmed that extremely superior reliability can be obtained as compared with.

Further, an active matrix type liquid crystal display device used for direct viewing and for projectors has a TFT
It was necessary to provide a light-shielding film in order to block stray light entering the camera. The light-shielding film is formed on the substrate on which the TFT is formed or on the opposing substrate in accordance with the arrangement of the TFTs.

[0008]

SUMMARY OF THE INVENTION However, GOL
The D structure has a problem that the off-state current is larger than that of the normal LDD structure. In order to prevent an increase in off-state current, one TFT has a multi-gate multi-channel structure in which a plurality of channel formation regions and a plurality of gate electrodes provided corresponding to the plurality of channel formation regions are provided. Although it is possible, the T
FT alone was not enough. Therefore, it is not always preferable to form all the TFTs of a large-area integrated circuit with the same structure. For example, in an n-channel TFT forming a pixel matrix circuit, an increase in off-state current causes an increase in power consumption or an abnormality in image display. Therefore, it is not preferable to use a crystalline TFT having a GOLD structure as it is. Further, the offset LDD structure has a problem that the on-current is reduced due to an increase in series resistance. Although the on-current can be freely designed depending on the channel width of the TFT, for example, it is not always necessary to provide an offset TFT in the TFT constituting the buffer circuit.

Further, in an active matrix type liquid crystal display device used for direct viewing or a projector, it is important to improve the aperture ratio in order to improve the image quality. In order to improve the aperture ratio, the area where the light-shielding film is to be formed may be reduced as much as possible. Was. However, if the pixel TFT has a multi-gate / multi-channel structure in order to reduce the off-current, the size of the TFT is inevitably increased due to restrictions on design rules.

The present invention is a technique for solving such a problem, and an object of the present invention is to realize a crystalline TFT having a reliability equal to or higher than that of a MOS transistor. It is another object of the present invention to improve the reliability of a semiconductor device having a large-area integrated circuit in which various functional circuits are formed using such a crystalline TFT.

Another object of the present invention relates to a configuration of a TFT and a storage capacitor of a pixel matrix circuit, and aims at improving an aperture ratio of an active matrix type liquid crystal display device.

[0012]

In order to solve the above-mentioned problems, the structure of the present invention provides an island-shaped semiconductor layer and a gate formed in contact with the island-shaped semiconductor layer on a substrate having an insulating surface. In a semiconductor device having an insulating film and one gate electrode provided in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer, the island-shaped semiconductor layer includes a plurality of channel formation regions, a source, A first impurity region of one conductivity type forming a region or a drain region; a third impurity region of one conductivity type formed in contact with the first impurity region; A second impurity region of one conductivity type formed in contact with the second impurity region of one conductivity type formed at both ends in contact with the channel formation region; The plurality of channel forming regions are Through the over gate insulating film is characterized in that overlaps with the gate electrode. Further, a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and one end formed in contact with the first impurity region in the island-shaped semiconductor layer. A second impurity region of one conductivity type, both ends of which are in contact with the channel formation region, the second impurity region and the plurality of channel formation regions; May be configured to overlap with the gate electrode via the gate insulating film.

Another structure of the present invention is a semiconductor device having a matrix circuit formed by n-channel thin film transistors, wherein the n-channel thin film transistors are:
A plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and a third impurity region of one conductivity type formed in contact with the first impurity region; A second impurity region of one conductivity type formed at one end in contact with the third impurity region, and a second impurity region of one conductivity type formed at both ends in contact with the channel formation region; The second impurity region and the plurality of channel formation regions are overlapped with one gate electrode provided corresponding to the n-channel thin film transistor with a gate insulating film interposed therebetween.

Another structure of the present invention is a semiconductor device having a CMOS circuit formed by an n-channel thin film transistor and a p-channel thin film transistor.
The plurality of n-channel thin film transistors include a plurality of channel formation regions, a first conductivity type first impurity region forming a source region or a drain region, and a first conductivity type formed in contact with the first impurity region. A second impurity region of one conductivity type, one end of which is in contact with the third impurity region, and a second impurity region of one conductivity type, both ends of which are in contact with the channel formation region. The second impurity region and the plurality of channel formation regions overlap one gate electrode provided corresponding to the n-channel thin film transistor with a gate insulating film interposed therebetween. It is characterized by having. Further, the plurality of n-channel thin film transistors are formed in such a manner that a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and one end in contact with the first impurity region. A second impurity region of one conductivity type;
A second impurity region of one conductivity type, both ends of which are formed in contact with the channel formation region;
The plurality of channel formation regions may overlap with one gate electrode provided corresponding to the n-channel thin film transistor with a gate insulating film interposed therebetween.

Another structure of the present invention is a semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors. Semiconductor layer, a gate insulating film formed in contact with the island-shaped semiconductor layer, and one gate electrode provided in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer, The island-shaped semiconductor layer includes a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and a first impurity region of one conductivity type formed in contact with the first impurity region. And a second impurity region of one conductivity type, one end of which is provided so as to overlap the gate electrode with a gate insulating film interposed therebetween and one end of which is in contact with the third impurity region. And a second impurity region of one conductivity type formed in contact with the Le forming region, said storage capacitor,
A first insulating layer having a first opening on the thin film transistor; a conductive film formed on the thin film transistor via the first insulating layer; and a pixel electrode extending on the conductive film And a dielectric film provided between the conductive film and the pixel electrode, and connected to the thin film transistor via the first opening. In addition, the thin film transistor includes an island-shaped semiconductor layer, a gate insulating film formed in contact with the island-shaped semiconductor layer, and one provided in contact with the gate insulating film and provided corresponding to the island-shaped semiconductor layer. And a gate electrode,
The island-shaped semiconductor layer includes a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and a first impurity region of one conductivity type formed in contact with the first impurity region. And a second impurity region of one conductivity type which is provided so as to overlap with the gate electrode via a gate insulating film, one end of which is formed in contact with the third impurity region. A second impurity region of one conductivity type formed in contact with the region;
A first insulating layer having a first opening on the thin film transistor, and a second insulating layer patterned on the first insulating layer and having a second opening overlapping the first opening. A conductive film formed on the thin film transistor, a pixel electrode extending over the conductive film, and a conductive film formed between the conductive film and the pixel electrode via the first insulating layer. And a structure formed from the dielectric film provided and connected to the thin film transistor via the first opening and the second opening.

According to another structure of the present invention, a plurality of thin film transistors arranged in a matrix, a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors, and a plurality of thin film transistors formed on the pixel electrode are provided. A semiconductor device having an alignment film, wherein the thin film transistor is an island-like semiconductor layer, a gate insulating film formed in contact with the island-like semiconductor layer, and a contact with the gate insulating film, and the island-like semiconductor layer A plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, A third impurity region of one conductivity type, which is formed in contact with the first impurity region, and which overlaps with the gate electrode with a gate insulating film interposed therebetween, and has one end formed in contact with the third impurity region; A second impurity region of one conductivity type, and a second impurity region of one conductivity type formed at both ends in contact with the channel formation region, and the storage capacitor has a first impurity region on the thin film transistor. A first insulating layer having an opening, a conductive film formed over the thin film transistor via the first insulating layer, the pixel electrode extending over the conductive film, and the conductive film. A dielectric film provided between the pixel electrode and the pixel electrode, and connected to the thin film transistor through the first opening, and the alignment film is formed of the same material as the dielectric film. It is characterized by being. In addition, the thin film transistor includes an island-shaped semiconductor layer, a gate insulating film formed in contact with the island-shaped semiconductor layer, and one provided in contact with the gate insulating film and provided corresponding to the island-shaped semiconductor layer. And a gate electrode,
The island-shaped semiconductor layer includes a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and a first impurity region of one conductivity type formed in contact with the first impurity region. And a second impurity region of one conductivity type which is provided so as to overlap with the gate electrode via a gate insulating film, one end of which is formed in contact with the third impurity region. A second impurity region of one conductivity type formed in contact with the region;
A first insulating layer having a first opening on the thin film transistor, and a second insulating layer patterned on the first insulating layer and having a second opening overlapping the first opening. An insulating layer, a conductive film formed on the thin film transistor via the first insulating layer, the pixel electrode extending over the conductive film, and between the conductive film and the pixel electrode. A dielectric film provided, connected to the thin film transistor through the first opening and the second opening, and the alignment film is formed of the same material as the dielectric film. It is good also as a structure which was performed.

Further, a method for manufacturing a semiconductor device according to the present invention comprises:
A step of forming an island-shaped semiconductor layer over a substrate having an insulating surface; a step of forming a gate insulating film in contact with the island-shaped semiconductor layer; Forming a first impurity region forming a source region or a drain region by adding to the region thus formed;
A first conductivity type impurity element is added to a selected region of the island-shaped semiconductor layer to form a third impurity region in contact with the first impurity region and a second impurity region having one end in contact with the third impurity region. Forming an impurity region and a second impurity region both ends of which are in contact with a channel formation region; and forming a gate electrode overlapping the second impurity region via the gate insulating film. It is characterized by.

Further, another structure of the present invention includes a step of forming an island-shaped semiconductor layer on a substrate having an insulating surface, a step of forming a gate insulating film in contact with the island-shaped semiconductor layer,
Adding a one-conductivity-type impurity element to a selected region of the island-shaped semiconductor layer to form a first impurity region forming a source region or a drain region; Forming a second impurity region having one end in contact with the first impurity region and a second impurity region having both ends in contact with the channel forming region by adding to a selected region of the semiconductor layer; Through the gate insulating film,
Forming a gate electrode overlapping the second impurity region.

Another structure of the present invention is a method of manufacturing a semiconductor device having a matrix circuit formed of n-channel thin film transistors, wherein the n-channel thin film transistors are formed on an island-shaped semiconductor on a substrate having an insulating surface. Forming a layer, forming a gate insulating film in contact with the island-shaped semiconductor layer, adding one conductivity type impurity element to a selected region of the island-shaped semiconductor layer, and forming a source region or Forming a first impurity region forming a drain region; and adding a one-conductivity-type impurity element to a selected region of the island-shaped semiconductor layer to form a third impurity in contact with the first impurity region. Forming a region, a second impurity region having one end in contact with the third impurity region, and a second impurity region having both ends in contact with the channel formation region;
Forming a gate electrode overlying the second impurity region via the gate insulating film.

Another structure of the present invention is a method for manufacturing a semiconductor device having a CMOS circuit formed by an n-channel thin film transistor and a p-channel thin film transistor, wherein the n-channel thin film transistor is a substrate having an insulating surface. Forming an island-shaped semiconductor layer thereon, forming a gate insulating film in contact with the island-shaped semiconductor layer, and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer Forming a first impurity region forming a source region or a drain region; and adding a one-conductivity-type impurity element to a selected region of the island-shaped semiconductor layer to form a first impurity region. A third impurity region in contact with the second impurity region and a second impurity region having one end in contact with the third impurity region.
Impurity region and a second region in which both ends are in contact with the channel formation region.
And a step of forming a gate electrode overlapping the second impurity region via the gate insulating film.

Another aspect of the present invention is a method for manufacturing a semiconductor device having a CMOS circuit formed by an n-channel thin film transistor and a p-channel thin film transistor, wherein the n-channel thin film transistor is a substrate having an insulating surface. Forming an island-shaped semiconductor layer thereon, forming a gate insulating film in contact with the island-shaped semiconductor layer, and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer Forming a first impurity region for forming a source region or a drain region; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer. Forming a second impurity region in contact with the impurity region and a second impurity region having both ends in contact with the channel formation region; and forming the second impurity region through the gate insulating film. Forming a gate electrode overlapping with the impurity region, that is formed from are characterized.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors. Forming an island-shaped semiconductor layer on a substrate having an insulating surface, forming a gate insulating film in contact with the island-shaped semiconductor layer, and adding one conductivity-type impurity element to the island-shaped semiconductor layer. Forming a first impurity region forming a source region or a drain region by adding the impurity element to a selected region of the island-shaped semiconductor layer; A third impurity region in contact with the first impurity region, a second impurity region in which one end is in contact with the third impurity region, and a second impurity in which both ends are in contact with the channel forming region. Forming a region, and forming a gate electrode overlapping the second impurity region via the gate insulating film, wherein the storage capacitor has a first opening on the thin film transistor. Forming a first insulating layer having: a step of forming a conductive film on the thin film transistor via the first insulating layer; and forming a dielectric film on the conductive film. Forming a pixel electrode extending on the conductive film via the dielectric film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors. Forming an island-shaped semiconductor layer on a substrate having an insulating surface, forming a gate insulating film in contact with the island-shaped semiconductor layer, and adding one conductivity-type impurity element to the island-shaped semiconductor layer. Forming a first impurity region forming a source region or a drain region by adding the impurity element to a selected region of the island-shaped semiconductor layer; A third impurity region in contact with the first impurity region, a second impurity region in which one end is in contact with the third impurity region, and a second impurity in which both ends are in contact with the channel forming region. And a step of forming a gate electrode overlapping the second impurity region through the gate insulating film, wherein the storage capacitor has a first opening on the thin film transistor. Forming a first insulating layer having a portion, and forming a second insulating layer having a second opening overlapping the first opening on a part of the first insulating layer. A step of forming a conductive film on the thin film transistor over the first insulating layer; a step of forming a dielectric film on the conductive film; and a step of forming a dielectric film on the conductive film. Forming a pixel electrode extending on the conductive film.

In another structure of the present invention, a plurality of thin film transistors arranged in a matrix, a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors, and a plurality of thin film transistors formed on the pixel electrode And a method for manufacturing a semiconductor device having the oriented film, wherein the thin film transistor has a step of forming an island-shaped semiconductor layer over a substrate having an insulating surface, and a step of forming a gate insulating film in contact with the island-shaped semiconductor layer. Forming a first impurity region forming a source region or a drain region by adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer; An impurity element is added to a selected region of the island-shaped semiconductor layer to form a third impurity region in contact with the first impurity region and a second impurity in which one end is in contact with the third impurity region. Forming a region and a second impurity region both ends of which are in contact with the channel formation region; and forming a gate electrode overlapping the second impurity region via the gate insulating film. The storage capacity is
Forming a first insulating layer having a first opening on the thin film transistor; forming a conductive film on the thin film transistor via the first insulating layer; A step of forming a dielectric film on the conductive film, and a step of forming the pixel electrode by extending the pixel electrode on the conductive film with the dielectric film interposed therebetween. It is characterized by being formed of the same material.

Another structure of the present invention includes a plurality of thin film transistors arranged in a matrix, a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors, and a structure formed on the pixel electrode. And a method for manufacturing a semiconductor device having the oriented film, wherein the thin film transistor has a step of forming an island-shaped semiconductor layer over a substrate having an insulating surface, and a step of forming a gate insulating film in contact with the island-shaped semiconductor layer. Forming a first impurity region forming a source region or a drain region by adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer; An impurity element is added to a selected region of the island-shaped semiconductor layer to form a third impurity region in contact with the first impurity region and a second impurity in which one end is in contact with the third impurity region. Forming a region and a second impurity region both ends of which are in contact with the channel formation region; and forming a gate electrode overlapping the second impurity region via the gate insulating film; Forming a first insulating layer having a first opening on the thin film transistor; and forming a first insulating layer on a part of the first insulating layer overlapping the first opening. Forming a second insulating layer having two openings, forming a conductive film on the thin film transistor via the first insulating layer, and forming a dielectric film on the conductive film. Forming a pixel electrode on the conductive film via the dielectric film, and forming the pixel electrode on the conductive film.
It is formed of the same material as the dielectric film.

[0026]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel matrix circuit and a TFT of a driver circuit provided therearound will be described.

(Process of forming island-shaped semiconductor layer and gate insulating film)
1) In FIG. 1, the substrate 101 has a heat resistance
A quartz substrate was used. The TFT of the substrate 101 is formed
A silicon oxide film, silicon nitride film, or nitride
Plasma CVD for base film 102 made of a silicon oxide film
Formed to a thickness of 100 to 400 nm by sputtering or sputtering.
Was. The base film 102 is made of a silicon nitride film having a thickness of 25 to 100 n.
m, here a 50 nm thick silicon oxide film
Up to 300 nm, here a 150 nm thick two-layer structure
It may be formed by molding (not shown). The base film 102 is
It is provided to prevent impurity contamination from the plate.
If a quartz substrate is used, it is not necessary to provide
No. Next, a 20 to 100 nm
An amorphous silicon film having a thickness was formed by a known film forming method.
The amorphous silicon film depends on the hydrogen content, but is preferably
Dehydrogenation by heating at 400-550 ° C for several hours,
The crystallization process is performed with the hydrogen content being 5 atom% or less.
It is desirable. The amorphous silicon film is sputtered.
It may be formed by another manufacturing method such as evaporation or vapor deposition.
Impurity elements such as oxygen and nitrogen contained in
It is desirable to keep. Underlayer and amorphous silicon film
Can be formed by the same film forming method.
May be continuously formed. After forming the base film,
Prevent surface contamination by avoiding exposure
To reduce the variation in the characteristics of the TFTs to be manufactured.
Can be reduced. From amorphous silicon film to crystalline silicon
The step of forming a recon film is a known laser crystallization technique.
Alternatively, a thermal crystallization technique may be used. Also silicon
Thermal crystallization using a catalyst element that promotes crystallization
A crystalline silicon film may be formed. In addition, microcrystals
A silicon film may be used, or a crystalline silicon film may be directly
It may be deposited and formed. In addition, single-crystal silicon
SOI (Silicon On Insulators)
A crystalline silicon film may be formed using a known technique.
No. Unnecessary portions of the crystalline silicon film thus formed
Is removed by etching to form island-like semiconductor layers 103 to 106.
Formed. N-channel TFT made of crystalline silicon film
In order to control the threshold voltage,
1x10¹⁵~ 5 × 10¹⁷cm ^-3Boro with moderate concentration
(B) may be added. Next, the island-shaped semiconductor layer
Covering silicon oxide or silicon nitride
A gate insulating film 107 mainly containing silicon was formed. Get
The gate insulating film 107 has a thickness of 10 to 200 nm, preferably 5 to 200 nm.
It may be formed to a thickness of 0 to 150 nm. For example, plastic
N by Zuma CVD_TwoO and SiH_FourOxide nitride
A recon film is formed to a thickness of 75 nm, and then
Is hot at 800-1000 ° C in a mixed atmosphere of oxygen and hydrochloric acid
It may be oxidized to form a 115 nm gate insulating film (FIG. 1)
(A)).

(Formation of Low Concentration Impurity Region) In order to form a low concentration impurity region (hereinafter, referred to as a second impurity region and a third impurity region in the present invention) serving as an LDD region in an n-channel TFT, The entire surface of the island-shaped semiconductor layer 103;
Resist masks 108 to 111 covering channel formation regions of the island-shaped semiconductor layers 104 to 105 were formed. At this time,
A resist mask may be formed in a region where a wiring is to be formed. Then, a step of forming a low-concentration impurity region by adding an impurity element imparting n-type was performed. Here, ion doping was performed using phosphorus and phosphine (PH ₃ ). In this step, the gate insulating film 10
7, phosphorus was added to the underlying semiconductor layer. Phosphorus concentration to be added, 1 × is preferably in the range of ^{10 16 ~1 × 10 19 atoms /} cm 3, 1 × 10 1 8 atoms / cm 3 here
And Then, low-concentration impurity regions 112 to 120 in which phosphorus was added to the island-shaped semiconductor layer were formed. In order to realize the configuration of the present invention, for example, two or more low-concentration impurity regions are formed in the island-shaped semiconductor layer 106 of the pixel matrix circuit. Thereafter, a heat treatment is performed in a nitrogen atmosphere at 400 to 900 ° C., preferably 600 to 800 ° C. for 1 to 12 hours, and a step of activating the n-type impurity element added in this step is performed (FIG. 1 (B)).

(Formation of Conductive Film for Gate Electrode and Wiring) The first conductive film 121 is mainly composed of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W). 10-1
It was formed to a thickness of 00 nm. For the first conductive layer, tantalum nitride (TaN) or tungsten nitride (WN) can be used. Although not shown, a silicon film may be formed under the first conductive film to a thickness of about 2 to 20 nm. Then, aluminum (Al) and copper (Cu)
A second conductive film 122 mainly composed of
nm (FIG. 1C). Then, a wiring 123 made of the second conductive film was formed in a region where a wiring from the input / output terminal to the input / output of the driver circuit was formed. For example, when Al was used for the second conductive film, etching could be performed with a phosphoric acid solution with good selectivity to the base TaN.
Further, a third conductive film 124 is formed over the first conductive layer 121 and the wiring 123 with a thickness of 100 to 400 nm using a conductive material mainly containing an element selected from Ta, Ti, Mo, and W. did. For example, Ta may be formed to a thickness of 200 nm (FIG. 1C).

(Steps of Forming Gate Electrode (p-ch) and Wiring Electrode and B Doping) Resist masks 125 to 130 are formed, and the first and third conductive films are partially removed by etching. The wiring 131 from the input / output terminal to the input / output of the driving circuit, the gate electrode 132 of the p-channel TFT, the gate wiring 135 in the driving circuit, and the gate wiring 136 in the pixel matrix circuit were formed. The wiring 131 was completed with a clad structure in which the second conductive film (Al) was covered with the first conductive film (TaN) and the third conductive film (Ta).
With such a structure, the wiring resistance can be reduced and the heat resistance can be increased. Since the gate electrode of the n-channel TFT is formed in a later step, the first conductive film and the third conductive film are left over the entire surface of the semiconductor layers 104 to 106. Then, a step of adding an impurity element imparting p-type to a part of the semiconductor layer 103 where the p-channel TFT is formed was performed while leaving the resist masks 125 to 130 as a mask. Here, boron was added as an impurity element by ion doping using diborane (B ₂ H ₆ ). Here, boron was added to a concentration of 2 × 10 ²⁰ atoms / cm ³ . Then, as shown in FIG. 2A, the fourth impurity region 13 doped with boron at a high concentration is formed.
8, 139 were formed. In this step, the gate insulating film 1 is formed using the resist masks 125 to 130.
07 is removed by etching to form the island-shaped semiconductor layer 103.
After exposing a part of the semiconductor layer, a step of adding an impurity element imparting p-type may be performed.

(Formation of Gate Electrode (n-ch)) After forming resist masks 140 to 145, an n-channel type TFT is formed.
Gate electrodes 146 to 148 were formed. At this time, the gate electrodes 146 to 148 are connected to the low concentration impurity regions 112 to 12.
0 (FIG. 2 (B)).

(P doping step) Resist mask 149
To 154, and a step of forming a first impurity region functioning as a source region or a drain region in the n-channel TFT. Resist mask 15
1, 154 are gate electrodes 146 of an n-channel TFT,
148 and a part of the second impurity regions 112, 117 and 120. This is the offset LDD
This is for forming a third impurity region to be a region. Then, an impurity element imparting n-type is added to form first impurity regions, and the first impurity regions 156, 157, and 192 to be source regions and the first impurity regions 155 and 158 to be drain regions are formed. , 160 were formed. Also in this case, the ion doping method using phosphine (PH ₃ ) is performed, and the concentration of phosphorus in this region is higher than that in the step of adding the first impurity element imparting n-type, and is 1 × 10 3 ¹⁹ it is preferable to be ^{~1 × 10 21 atoms / cm 3} , here was ^{1 × 10 2 0 atoms / cm} 3. Also,
A part of the gate insulating film 107 is removed by etching using the resist masks 149 to 154, and the island-shaped semiconductor layer 10 is removed.
After exposing a part of 4 to 106, a step of adding an impurity element imparting n-type may be performed (FIG. 2).
(C)).

(Step of thermal activation) First interlayer insulating film on the entire surface of the gate insulating film and the gate electrode (and also on the upper surface when a part of island-like semiconductor layers 103 to 106 is exposed) 161 was formed. The first interlayer insulating film may be formed using a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. Further, it may have a two-layer structure of a silicon nitride film and a silicon oxide film or a silicon oxynitride film (not shown). In any case, the first interlayer insulating film is 500 to 1
It may be formed so as to have a thickness of 000 nm. Thereafter, a heat treatment step for activating the n-type or p-type impurity element added at each concentration was performed. This step includes a thermal annealing method using an electric heating furnace,
It can be performed by a rapid thermal annealing method (RTA method) using a halogen lamp. Here, the activation step was performed by a thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550.
C., here 500 ° C., for 2 hours. Further, in an atmosphere containing 3 to 100% hydrogen, 300 to 4
Heat treatment was performed at 50 ° C. for 1 to 12 hours to perform a step of hydrogenating the island-shaped semiconductor layer. In this step, a heat treatment at 200 to 450 ° C. may be performed in a hydrogen atmosphere generated by plasma using a plasma hydrogenation method (FIG. 3A).

(Formation of Source / Drain Electrodes and Interlayer Insulating Film) The first interlayer insulating film 161
A contact hole reaching the source region and the drain region of the FT was formed. Then, the source electrodes 162, 16
5, 166, 168, drain electrodes 163, 164,
167 and 169 were formed. Although not shown, in this embodiment, this electrode is formed of a Ti film having a thickness of 100 nm and an A film containing Ti.
An l film having a thickness of 300 nm and a Ti film having a thickness of 150 nm were successively formed by a sputtering method and used as an electrode having a three-layer structure. At the same time, a wiring 200 from the input / output terminal to the input / output of the driving circuit, a source wiring 198 in the driving circuit, and a source wiring 199 in the pixel matrix circuit were formed. Then, a passivation film 170 was formed on the first interlayer insulating film, the source electrode, the drain electrode, and the respective wiring electrodes. The passivation film 170 was formed using a silicon nitride film, a silicon oxide film, or a silicon oxynitride film with a thickness of 50 to 500 nm. Performing the hydrogenation treatment in this state requires T
This was favorable for improving the characteristics of FT. For example, 3-1
1% at 300-450 ° C in an atmosphere containing 00% hydrogen
It is preferable that the heat treatment is performed for up to 12 hours. Alternatively, the heat treatment may be performed at 200 to 450 ° C. in a hydrogen atmosphere generated by plasma conversion using a plasma hydrogenation method. After that, a part of the passivation film on the drain electrode 169 is removed to form a contact hole, and a second interlayer insulating film 210 made of an organic resin is
It was formed to a thickness of 00 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used.

(Formation of Storage Capacitor and Pixel Electrode) A step of forming a light shielding film 171 on the second interlayer insulating film was performed. The light-shielding film 171 was formed of a film mainly containing an element selected from Ti, Al, Cr, Ta, and W. Then, the light shielding film 17
A dielectric film 172 is formed on the first and second interlayer insulating films.
It was formed with a thickness of 0 to 200 nm. This dielectric film 172
May be formed of an inorganic insulating film such as a silicon oxide film or a silicon nitride film, but it is more suitable to form a dielectric film without pinholes with an organic insulating film containing polyimide as a main component. Was. For example, when polyimide is used, a liquid crystal alignment film material having a dielectric constant of 3.0 to 3.8 (1 kHz) and a volume resistivity of 7 × 10 ¹⁵ to 1 × 10 ¹⁷ Ωcm can be used as it is. Was. Such a polyimide film could be formed by letterpress printing or spin coating. However, when the viscosity of the solution was as low as 25 to 35 cp, it was necessary to apply multiple layers to increase the thickness of the dielectric. Then, the opening 223 provided in the dielectric film 172 and the opening 2 provided in the second interlayer insulating film 210 are formed.
21 and the opening 220 provided in the passivation film 170, a contact hole reaching the drain electrode 169 was formed, and the pixel electrode 173 was formed. Pixel electrode 17
For the transmission liquid crystal display device 3, a transparent conductive film may be used, and for a reflection liquid crystal display device, a metal film may be used. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method. The pixel electrode 173 was formed to extend over the light shielding film 171 via the dielectric film 172, and a storage capacitor was formed in a region where the pixel electrode 173 overlapped the light shielding film 171 (FIG. 3B).

Through the above steps, an active matrix substrate in which the pixel matrix circuit and the TFTs of the driving circuits provided around the pixel matrix circuit are formed on the same substrate is manufactured.

A p-channel TFT 201 of a CMOS circuit
The channel formation region 174 and the fourth impurity region 17
5, 176 were formed. Then, the fourth impurity region 1
75 is a source region, and the fourth impurity region 176 is a drain region.

The n-channel TFT 202 includes a channel formation region 177, first impurity regions 178 and 179, second impurity regions 180 and 181a overlapping the gate electrode via a gate insulating film, and a third impurity region not overlapping the gate electrode. Of impurity region 181b was formed. First impurity region 17
8 functions as a source region, and the first impurity region 179 functions as a drain region.

The n-channel TFT 203 has a plurality of channel forming regions 182 and 183 and a first impurity region 18.
4, 188, a plurality of second impurity regions 185 to 187 overlapping with the gate electrode via the gate insulating film were formed.
The first impurity region 184 functioned as a source region, and the first impurity region 188 functioned as a drain region.

The n-channel TFT 204 of the pixel matrix circuit has a plurality of channel forming regions 189-1.
91, first impurity regions 192 and 197, and a plurality of second impurity regions 1 overlapping the gate electrode via the gate insulating film.
93a, 194, 195, and 196a, and third impurity regions 193b and 196b that do not overlap with the gate electrode were formed.

The present invention relates to a pixel matrix circuit and a CM
In consideration of the drive voltage of each n-channel TFT of the OS circuit, it is easy to make the lengths in the channel length direction of the second impurity region and the third impurity region serving as LDD regions different on the same substrate. In addition, it was possible to form an optimal shape for a TFT constituting each circuit.

The n-channel TFT 202 shown in FIG. 3B has a single gate structure, and is suitable for a shift register circuit having a driving voltage of about 10 V. Third impurity region 181b serving as an offset LDD region only on the drain side
Is provided. The length (Loff) of this area is 0.5 to
It may be 3.0 μm, typically 1.5 μm. Further, the LDD region overlapping the gate electrode (second region)
In the case where the length of the channel formation region is 3.0 to 4.0 μm, the lengths (Lo
v) is from 1.0 to 3.0 μm, preferably from 1.5 to 2.5
μm may be used.

The n-channel type TFT 203 has a structure in which a plurality of channel formation regions corresponding to one gate electrode are provided and divided by a plurality of second impurity regions forming an LDD region (single-gate multi-channel TFT). Structure). Such a TFT is suitable for a level shifter circuit, a buffer circuit, or the like that requires a high driving voltage and a high current driving capability. Therefore, no offset LDD region (third impurity region) is provided,
When the length of the channel formation region is 3.0 to 4.0 μm, the LDD region (the second
Impurity region) 185 to 187 has a length (Lov) of 0.1.
The thickness may be 5 to 3.0 μm, preferably 1.0 to 2.0 μm.

N-channel TFT of pixel matrix circuit
204 also has a single-gate / multi-channel structure. However, since the polarity is inverted, third impurity regions 193b and 196b serving as offset LDD regions are provided on both the source side and the drain side. The length (Loff) of this region is 0.5 to 3.5 μm, typically 2.0 μm.
μm may be used. In addition, LDD regions (second impurity regions) 193a and 193a that overlap the gate electrode
4, 195 and 196a are channel forming regions 189, 1
The length of each of 90 and 191 is 1.0 to 3.0 μm,
When it is preferably 2.5 μm, its length (Lov) may be 1.0 to 3.0 μm, preferably 1.5 to 2.5 μm.

As described above, in a single-gate multi-channel TFT in which a plurality of channel formation regions are divided by a low-concentration impurity region serving as an LDD region for one gate electrode, one gate electrode is formed. The number of channel formation regions and the second impurity regions corresponding to the above may be appropriately determined by a practitioner in consideration of the characteristics of the target TFT. With such a configuration, the withstand voltage of the TFT could be increased as in the conventional multi-gate / multi-channel structure.

[Embodiment 2] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 4, an alignment film 401 is formed on the surface of the dielectric film 172 and the pixel electrode 173 for the substrate in the state of FIG. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. On the substrate 402 on the opposite side, a transparent conductive film 403 and an alignment film 404 were formed. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were parallel-aligned with a certain pretilt angle. Then, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the opposing substrate are bonded to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. Thereafter, a liquid crystal material 1508 was injected between the two substrates, and completely sealed with a sealing agent (not shown). Thus, the active matrix type liquid crystal display device shown in FIG. 15 was completed.

Next, the configuration of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 5 and the top view of FIG. 5 and 6 use the same reference numerals in order to correspond to the sectional structural views of FIGS. The active matrix substrate includes a pixel matrix circuit 501, a scanning (gate) line driving circuit 502, and a signal (source) line driving circuit 503 formed on the glass substrate 101. The pixel TFT 204 of the pixel matrix circuit has n
It is a channel type TFT, and a peripheral driving circuit is configured based on a CMOS circuit. Scanning (gate) line driving circuit 502 and signal (source) line driving circuit 5
Reference numeral 03 denotes a gate line 148 and a source line 199 connected to the pixel matrix circuit 501, respectively. Also, F
Wirings 149 and 200 are provided from the external input / output terminal 534 to which the PC 531 is connected to the input / output terminal of the drive circuit.

FIG. 6 is a top view showing a part of the pixel matrix circuit 501. A gate electrode 148 formed continuously with the gate wiring 136 intersects with the underlying semiconductor layer 106 via a gate insulating film (not shown).
Although not illustrated, a source region, a drain region, a second impurity region, and a third impurity region are formed in the semiconductor layer 106. Further, a storage capacitor is formed on the pixel TFT by a light shielding film 171, a dielectric film (not shown), and a pixel electrode 173. A plurality of channel forming regions and a plurality of low-concentration impurity regions serving as a plurality of LDD regions are continuously formed by the single-gate multi-channel TFT of the present invention, so that the pixel TFTs are compactly formed and the source line contact 251 is formed. , Drain line contact 252 and ITO contact 253 are pixel TFTs
Is formed above. As described above, by providing an area necessary for contact formation on the pixel TFT so as to overlap, the aperture ratio could be improved. In addition, A- shown in FIG.
The cross-sectional structure along A ′ corresponds to the AA ′ cross-sectional view of the pixel matrix circuit shown in FIG.

[0049]

[Embodiment 1] In this embodiment, an active matrix in which a pixel matrix circuit and a CMOS circuit which is a basic form of a driving circuit provided around the pixel matrix circuit are formed at the same time by using FIGS. A method for manufacturing a substrate will be described. First, as a first insulating layer over a substrate 1101, a silicon oxynitride film 1102a having a nitrogen content higher than the oxygen content is 50 to 500 nm, typically 10 nm.
A silicon nitride oxide film 302
b was formed to a thickness of 100 to 500 nm, typically 200 nm. The silicon oxynitride film 1102a is made of SiH ₄
, N ₂ O, and NH ₃ , and the concentration of nitrogen contained was adjusted to 25 atomic% or more and less than 50 atomic%. Further, island-shaped crystalline semiconductor films 1103, 110
4 and 1105, and a gate insulating film 1106 were formed. The island-shaped crystalline semiconductor film is obtained by forming a crystalline semiconductor film from an amorphous semiconductor film by a crystallization method using a catalytic element, and separating the crystalline semiconductor film into an island shape. Gate insulating film 11
Reference numeral 06 denotes a silicon oxynitride film formed from SiH ₄ and N ₂ O. Here, 10 to 200 nm, preferably 5 to 200 nm.
It was formed with a thickness of 0 to 150 nm. (FIG. 11A)

Next, an island-shaped semiconductor film 1103 and resist masks 1107 to 1110 covering the channel formation regions of the island-shaped semiconductor films 1104 and 1105 were formed. At this time,
A resist mask 1109 may be formed in a region where a wiring is to be formed. And phosphine (PH ₃ )
A second impurity region was formed by adding an impurity element imparting n-type by an ion doping method using GaN. In this step,
The acceleration voltage was set to 65 keV in order to add phosphorus to the underlying island-shaped semiconductor film through the gate insulating film 1106. The concentration of phosphorus added to the island-shaped semiconductor is 1 × 10 ¹⁶
It is preferable to set the range to 1 × 10 ¹⁹ atoms / cm ³ , and here, it is set to 1 × 10 ¹⁸ atoms / cm ³ . Then, regions 1111 to 1116 to which phosphorus was added were formed. Part of this region is a second impurity region that functions as an LDD region. (FIG. 11 (B))

After that, the resist mask is removed, and a tantalum nitride (TaN) film 11 is formed to form a gate electrode.
17 to a thickness of 10 to 50 nm, and tantalum (T
a) A film 1118 was formed to a thickness of 100 to 300 nm by a sputtering method. Here, Ta is sputtered, and Ar and X
e was formed using a mixed gas of e. (FIG. 11 (C))

Next, resist masks 1119 to 1122 are used.
And a gate electrode of a p-channel TFT and a CMO
Gate wiring and gate of S circuit and pixel matrix circuit
A bus line was formed. TaN film 1117 and Ta film 11
18 removes unnecessary portions by dry etching
Was. Etching of TaN film and Ta film is CF_FourAnd O_TwoMixing
Made by gas. The p-channel TFT gate
Gate electrode 1123, gate wiring 1125,
Slines 1126 and 1127 were formed. And les
Leaving the distant masks 1119 to 1122 as they are, p
Of the island-shaped semiconductor film 1103 where the channel type TFT is formed
Partly adding a fourth impurity element for imparting a p-type
Went through the process. Here, boron is the impurity element.
Diborane (B_TwoH₆) And added by ion doping method
Was. The boron concentration in this region is 2 × 10 ²⁰atoms / cm^Threeage
Was. Then, as shown in FIG.
The third impurity regions 1129 and 1130 added to
Was made.

After removing the resist mask provided in FIG. 12A, resist masks 1131 to 113 are newly added.
4 was formed. This is for forming the gate electrode of the n-channel TFT. The gate electrodes 1135 and 1136 of the n-channel TFT are formed by dry etching.
Was formed. At this time, the gate electrodes 1135, 1136
Are formed so as to overlap with a part of the second impurity regions 1111 to 1116. (FIG. 12 (B))

Then, a new resist mask 1137-
1140 was formed. Resist masks 1138, 114
0 is the gate electrodes 1135 and 113 of the n-channel TFT
6 and a part of the second impurity region. The offset amount of the LDD region is determined. Then, a step of forming a first impurity region by adding an impurity element imparting n-type conductivity is performed. Impurity regions 1143, 1146
Was formed. Further, regions 1141 and 1142 to which phosphorus was added were also formed in part of the island-shaped semiconductor layer 1103 where the p-channel TFT was formed. However, the phosphorus concentration in this region was about 1/2 of the boron concentration, and the conductivity type remained p-type. (FIG. 4 (C))

After the steps up to FIG. 12C are completed, the first interlayer insulating film 1147 is made of SiH by plasma CVD.
4, formed of a silicon oxynitride film using N2O and NH3 as raw materials. The concentration of hydrogen contained in this silicon oxynitride film is 1-3
It is desirable to form so as to be 0 atomic%. Then, in this state in a nitrogen atmosphere at 400 to 800 ° C., 1 to 1
The heat treatment was performed for 12 hours, for example, at 525 ° C. for 8 hours. The impurity element imparting n-type and p-type added by this step could be activated. Further, the regions 1141 to 1146 to which phosphorus was added became gettering sites, and the catalytic element remaining in the crystallization step could be segregated in this region. As a result, it was possible to remove the catalyst element from at least the channel formation region.

After this heat treatment, a hydrogenation step was performed. Here, 300 to 50% in a 3 to 100% hydrogen atmosphere
The hydrogenation step may be performed at 0 ° C, preferably 350 to 450 ° C for 2 to 12 hours. Or 200-500
Hydrogenation treatment may be performed using hydrogen generated by plasma conversion at a substrate temperature of 300C, preferably 300 to 450C. (FIG. 13A)

Thereafter, a predetermined resist mask was formed on the first insulating film 1147, and contact holes reaching the source region and the drain region of each TFT were formed by etching. Then, the source electrode 114
9, 1150, 1151 and drain electrodes 1152, 11
53 were formed. Although not shown, in this embodiment, this electrode is formed of a Ti film having a thickness of 100 nm and a Ti-containing Al film 300.
nm and a Ti film of 150 nm were used as an electrode having a three-layer structure formed continuously by a sputtering method.

Then, a passivation film 11 is formed thereon.
54 were formed. Passivation film is plasma CVD
A silicon nitride film formed from SiH ₄ , N ₂ O, and NH ₃ by a method, or a silicon nitride film formed from SiH ₄ , N ₂ , and NH ₃ may be used. First, prior to the formation of the film, a hydrogenation step was performed by introducing plasma such as N ₂ O, N ₂ , and NH ₃ . Hydrogen generated in the gas phase by being turned into plasma is supplied into the first interlayer insulating film, and if the substrate is heated to 200 to 400 ° C., the hydrogen is diffused to the lower layer side and the semiconductor is diffused. The layer could be hydrogenated. The conditions for forming the passivation film are not particularly limited, but a dense film is desirable. Also, after forming the passivation film,
The hydrogenation step is performed in an atmosphere containing hydrogen or nitrogen for 300 hours.
The heat treatment at 〜550 ° C. may be performed by a heat treatment for 1 to 12 hours.

Thereafter, a part of the passivation film on the drain electrode 1153 is removed to form a contact hole, and a second interlayer insulating film 115 made of an organic resin is formed.
5 was formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantage of using an organic resin film is that the film formation method is simple and the relative dielectric constant is low,
A point that the parasitic capacitance can be reduced and a point that the flatness is excellent can be raised. Note that an organic resin film other than those described above can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used.

A step of forming a light shielding film 1156 made of a Ti film on the second interlayer insulating film was performed. And the light shielding film 1
A dielectric film 115 made of a polyimide film is formed on 156 and the second interlayer insulating film 1155 in the same manner as in the first embodiment.
7 was formed with a thickness of 50 to 200 nm. An opening 1182 provided in the dielectric film 1157, an opening 1181 provided in the second interlayer insulating film 1155, and an opening 1180 provided in the passivation film 1154 form a drain electrode 1153. Was formed, and a pixel electrode 1158 was formed. Pixel electrode 115
In No. 8, a transparent conductive film was used for a transmissive liquid crystal display device, and a metal film was used for a reflective liquid crystal display device. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film having a thickness of 100 nm was used.
m was formed by a sputtering method. Pixel electrode 1158
Was formed to extend over the light shielding film 1156 via the dielectric film 1157, and a storage capacitor was formed in a region where the pixel electrode 1158 overlapped the light shielding film 1156. Through the above steps, the pixel matrix circuit and the T
An active matrix substrate having the FT formed on the same substrate was manufactured. The pixel matrix circuit has a structure in which a storage capacitor 1304 is connected to an n-channel TFT 1303. (FIG. 13 (B))

The p-channel TFT was formed in a self-aligned (self-aligned) manner, and the n-channel TFT was formed in a non-self-aligned (non-self-aligned) manner. A channel formation region 1159 and fourth impurity regions 1160 and 1161 were formed in a p-channel TFT 1301 of the CMOS circuit. In the fourth impurity region, a region 1160a to which boron (B) is added in contact with the channel formation region,
1161a and regions 1160b and 1111 which are not in contact with the channel formation region and to which boron (B) and phosphorus (P) are added.
There was 61b. Then, the fourth impurity region 1160 became a source region, and the fourth impurity region 1161 became a drain region. On the other hand, an n-channel TFT 1302 has a channel formation region 1162 and a first impurity region 11.
65, 1166, second impurity regions 1163a, 1164a overlapping the gate electrode via the gate insulating film, and third impurity regions 1163b, 116 not overlapping the gate electrode.
4b was formed. The first impurity region 1165 functioned as a source region, and the first impurity region 1166 functioned as a drain region. The n-channel TFT 1303 of the pixel matrix circuit has a plurality of channel formation regions 11.
67 to 1169, first impurity regions 1174 and 117
5. A plurality of second impurity regions 1170a, 1171, 1172, 11 overlapping the gate electrode via the gate insulating film
73a, third impurity region 11 not overlapping gate electrode
70b and 1173b were formed.

[Embodiment 2] In this embodiment, a configuration of a storage capacitor connected to a pixel TFT on an active matrix substrate will be described. FIG. 14 is a sectional structural view of an active matrix substrate manufactured in the same manner as in the first embodiment. The storage capacitor 1413 connected to the pixel TFT 1412 includes a light-shielding film 1402 formed on the second interlayer insulating film, a dielectric film 1404 formed on the light-shielding film 1402, and a pixel electrode 1405. . An insulating spacer 1403 is provided on the second interlayer insulating film, and an opening 1406 provided in the passivation film 1400 is provided.
The pixel electrode 1405 is connected to the drain electrode 1415 through an opening 1407 provided in the second interlayer insulating film, a 1408 provided in the spacer 1403, and an opening 1409 provided in the dielectric film 1404.

It is preferable to use an organic resin material for the dielectric film 1404 as in the first embodiment. As another method of forming a dielectric film, a light-shielding film 1402 is formed of an Al film,
The surface may be anodized. Since the dielectric constant of the anodic oxide film of Al was 7 to 8, a sufficient capacity could be formed.

[Embodiment 3] In this embodiment, another configuration of the storage capacitor connected to the pixel TFT of the active matrix substrate will be described. FIG. 15 is a sectional structural view of an active matrix substrate manufactured in the same manner as in the first embodiment. Storage capacitor 1513 connected to pixel TFT 1512
Are a transparent conductive film 1502 formed on the second interlayer insulating film 1501, a dielectric film 1504 formed on the transparent conductive film 1502, and a pixel electrode 1505 made of the transparent conductive film.
And is formed from With such a configuration,
The light transmittance of the pixel matrix circuit portion can be improved. Further, an insulator spacer 1503 is provided on the second interlayer insulating film 1501 so that the passivation film 1 is formed.
An opening 1506 provided in the opening 500, an opening 1507 provided in the second interlayer insulating film, an opening 1508 provided in the spacer 1503, and an opening 15 provided in the dielectric film 1504
At 09, the pixel electrode 1505 is connected to the drain electrode 1515.

[Example 4] The procedure for manufacturing the TFT of the present invention is not limited to the order of the steps in Embodiment 1 and Example 1, but the TFT can be manufactured in other steps. For example, as a procedure for manufacturing a p-channel TFT in a self-aligned manner and an n-channel TFT in a non-self-aligned manner, forming an island-shaped semiconductor layer and a gate insulating film, forming a low-concentration impurity region,
Formation of a conductive film for a gate electrode and a wiring electrode, formation of a gate electrode (n-channel TFT), P-doping process, formation of a gate electrode (p-channel TFT) and B-doping process, activation process, It is also possible to form a drain electrode and an interlayer insulating film, and form a storage capacitor and a pixel electrode.

If the p-channel type TFT is formed in a self-aligned manner and the n-channel type TFT is not formed in a non-self-aligned manner, a B-doped step is performed after the island-shaped semiconductor layer and the gate insulating film are formed. A low-concentration impurity region may be formed and P-doped, or a B-doped process, a P-doped process and a low-concentration impurity region may be formed. After the island-shaped semiconductor layer and the gate insulating film are formed, a P-doping step, a formation of a low-concentration impurity region, and a B-doping step may be performed. Can also be formed.

[Embodiment 5] In this embodiment, a method for manufacturing a semiconductor layer applicable to the present invention will be described. In FIG. 7, a substrate 701 can be a glass substrate, a ceramics substrate, a quartz substrate, or the like. Alternatively, a silicon substrate having a surface on which an insulating film such as a silicon oxide film or a silicon nitride film is formed, or a metal substrate represented by stainless steel may be used. In the case where a glass substrate is used, it is desirable to perform a heat treatment in advance at a temperature lower than the strain point. For example, if a Corning # 1737 substrate is used, 500-6
Heat treatment at 50 ° C, preferably 595 to 645 ° C, for 1 to 24 hours may be performed.

Then, a base film was formed on the main surface of the substrate 701. Although there is no particular limitation on the material of the base film, the base film is formed of the silicon oxynitride film 702. In addition, a single layer or a plurality of layers selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a tantalum oxide film can be used. When a silicon oxynitride film is used, it may be formed to a thickness of 20 to 100 nm, typically 50 nm. A silicon oxynitride film is formed on the silicon nitride film in a thickness of 50 to 500 nm, typically 50 to 20 nm.
It may be formed to a thickness of 0 nm. Then, the amorphous semiconductor layer 703 was formed over the first insulating layer. This may be an amorphous semiconductor formed by a film forming method such as a plasma CVD method, a low pressure CVD method, and a sputtering method.
i), germanium (Ge), a silicon germanium alloy, and silicon carbide. In addition, a compound semiconductor material such as gallium arsenide can be used. The semiconductor layer was formed to a thickness of 10 to 100 nm, typically 50 nm. In addition, the first insulating layer and the amorphous semiconductor layer 210
3 can also be formed continuously by a plasma CVD method or a sputtering method. After each layer is formed, the surface is prevented from being exposed to the atmosphere, thereby preventing the surface from being contaminated. (FIG. 7 (A))

Next, a crystallization step was performed. For the step of crystallizing the amorphous semiconductor layer, a known laser crystallization technique or thermal crystallization technique may be used. In addition, plasma CV
The amorphous semiconductor layer formed by the method D has a thickness of 10 to 40 atomic.
% Hydrogen is contained in the film, and prior to the crystallization step, a heat treatment step at 400 to 500 ° C. is performed to desorb hydrogen from the film so that the hydrogen content is 5 atomic% or less. Was desirable (FIG. 7B). Then, an island-shaped crystalline semiconductor layer 705 was formed from the crystalline semiconductor layer 704, and a gate insulating film 705 was further formed. The gate insulating film 705 may be formed using a material such as a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. The thickness of the gate insulating film 705 may be 10 to 1000 nm, preferably 50 to 400 nm. (FIG. 7
(C))

In FIG. 8, a base film 802 made of a silicon oxynitride film is formed on the main surface of a substrate 801, and an amorphous semiconductor layer 803 is formed on the surface as in FIG. The thickness of the amorphous semiconductor layer is 10 to 200 nm, preferably 30 to 200 nm.
What is necessary is just to form it in 100 nm. Furthermore, 10 in weight conversion
An aqueous solution containing ppm of a catalytic element was applied by a spin coating method to form a catalytic element-containing layer 804 over the entire surface of the amorphous semiconductor layer 803. The catalyst elements usable here are germanium (Ge), iron (F) in addition to nickel (Ni).
e), palladium (Pd), tin (Sn), lead (P
b), cobalt (Co), platinum (Pt), copper (Cu),
It was an element such as gold (Au). The internal stress of the amorphous semiconductor layer was not determined uniformly by the manufacturing conditions. However, 400-600 prior to the crystallization step.
It was necessary to perform a heat treatment process at a temperature of ° C. to remove hydrogen from the film (FIG. 8A). Then, heat treatment was performed at 500 to 600 ° C. for 4 to 12 hours, for example, at 550 ° C. for 8 hours, so that a crystalline semiconductor layer 805 was formed. (FIG. 8 (B))

Next, a step of removing the catalytic element used in the crystallization step from the crystalline semiconductor film was performed. In this case, the technique described in JP-A-10-135468 or 10-135469 was used. The technique described in this publication is a technique of removing the phosphorus using the gettering action of phosphorus. The concentration of the catalytic element in the crystalline semiconductor film is reduced to 1 × 10
It could be reduced to ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ . First, a mask insulating film 806 having a thickness of 150 nm was formed on the surface of the crystalline semiconductor layer 805, and an opening 807 was provided by patterning to provide a region where the crystalline semiconductor layer was exposed. Then, a step of adding phosphorus was performed to provide a phosphorus-containing region 808 in the crystalline semiconductor layer (FIG. 8C). In this state, in a nitrogen atmosphere at 550-800 ° C. for 5-24 hours, for example, 60
When heat treatment is performed at 0 ° C. for 12 hours, the phosphorus-containing region 808 is formed.
Works as a gettering site, and the crystalline semiconductor layer 80
5 could be segregated in the phosphorus-containing region 808 (FIG. 8D). Then, by removing the mask insulating film 806 and the phosphorus-containing region 808 by etching, the concentration of the catalyst element used in the crystallization step is reduced to 1 × 10 ¹⁷ atms / cm ³ or less. A high quality semiconductor layer was obtained. Then, a gate insulating film 810 was formed in close contact with the crystalline semiconductor layer 809 (FIG. 8E).

FIG. 9 shows that a base film 9 is formed on a substrate 901.
01, an amorphous semiconductor layer 902 was formed in this order, and a silicon oxide film 904 was formed on the surface of the amorphous semiconductor layer 902. At this time, the thickness of the silicon oxide film 904 is 150
nm. Further, the opening 905 was selectively formed by patterning the silicon oxide film 904, and then an aqueous solution containing 10 ppm by weight of a catalytic element was applied. Thus, a catalyst element-containing layer 906 was formed.
The catalyst-containing layer 906 was in contact with the amorphous semiconductor layer 903 only at the opening 905 (FIG. 9A). Next, 500-65
Heat treatment was performed at 0 ° C. for 4 to 24 hours, for example, 570 ° C. for 14 hours, so that a crystalline semiconductor layer 907 was formed. In the course of this crystallization, the region of the amorphous semiconductor layer in contact with the catalytic element crystallized first, and the crystallization proceeded laterally from there. The crystalline semiconductor layer 907 thus formed is made up of a collection of rod-shaped or needle-shaped crystals, each of which grows in a specific direction when viewed macroscopically, and thus has uniform crystallinity. (Fig. 9
(B)).

Next, a step of removing the catalytic element used in the crystallization step from the crystalline semiconductor film as in FIG. 8 was performed.
A step of adding phosphorus was performed on the substrate in the same state as in FIG. 9B, so that a phosphorus-containing region 909 was provided in the crystalline semiconductor layer. The phosphorus content in this region is 1 × 10 ¹⁹ to 1 × 1
0 ²¹ / cm ³ (FIG. 9C). In this state, in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 6 hours.
When heat treatment is performed at 00 ° C. for 12 hours, the phosphorus-containing region 90
9 serves as a gettering site and serves as a crystalline semiconductor layer 9.
07 could be segregated in the phosphorus-containing region 909 (FIG. 9D).

Then, the mask oxide film and the phosphorus-containing region 909 were removed by etching to form an island-shaped crystalline semiconductor layer 910. Then, the crystalline semiconductor layer 910
, A gate insulating film 911 was formed. The gate insulating film 911 was formed from one or more layers selected from a silicon oxide film and a silicon oxynitride film. The thickness may be 10 to 100 nm, preferably 50 to 80 nm. And halogen (typically chlorine)
Heat treatment was performed in an atmosphere containing oxygen and oxygen. For example, 95
The temperature was set to 0 ° C. for 30 minutes. Incidentally, the processing temperature is 700 to 1100.
The temperature may be selected in the range of ° C., and the processing time may be selected from 10 minutes to 8 hours. As a result, a thermal oxide film was formed at the interface between the crystalline semiconductor layer 910 and the second insulating layer 911, and a favorable interface having a low interface state density could be formed. (FIG. 9E).

In FIG. 10, as in FIG.
After forming the insulating layer 1002 and the crystalline semiconductor layer 1005, the catalytic element remaining in the crystalline semiconductor layer 1005 can be gettered in a liquid phase. For example, gettering can be performed by using sulfuric acid as a solution and dipping the substrate in the state of FIG. 10B in a sulfuric acid solution heated to 300 to 500 ° C. The remaining catalyst elements could be removed. In addition, a nitric acid solution, an aqueous solution, or a tin solution may be used. After that, the island-shaped semiconductor layer 1009, the second
Was formed.

[Embodiment 6] In this embodiment, an example in which the present invention is applied to an active matrix EL display device is shown in FIG.
This will be described in (A) and (B). FIG. 16A is a circuit diagram of an active matrix EL display device. The EL display device includes a display area 11 provided on a substrate 10, an X-direction peripheral drive circuit 12, and a Y-direction peripheral drive circuit 13. The display area 11 includes a switch TFT 14, a capacitor 15, a current control TFT 16, and an organic EL element 1.
7, X direction signal lines 18a, 18b, power supply lines 19a, 19
b, Y direction signal lines 20a, 20b, 20c and the like.

FIG. 16B is a partial sectional view of the display area 11 of the active matrix EL display device.
Here, the current control TFT 16 and the organic EL element 17
Shows a part of. The current control TFT 16 is an n-channel type T
FT, which is manufactured in the same manner as in the first embodiment. And T
The organic EL element 17 is provided by removing the insulating film in a region where the FT is not formed. The organic EL element includes a transparent electrode 21 made of ITO or the like, and an organic EL formed on the transparent electrode.
It is composed of a layer 23, an upper electrode 24 and the like. Then, an interlayer insulating film 25 is formed to cover the current control TFT 16, and a common electrode 26 is provided in contact with the upper electrode 24. The electrode 22b is provided for electrically connecting the drain electrode of the current control TFT and the transparent electrode 21. The electrode 22a is provided to maintain the adhesion between the electrode 22b and the transparent electrode 21.

In this embodiment, the structure in which the organic EL element 17 is provided in contact with the substrate 10 is shown. However, the present invention is not particularly limited to this structure. For example, the organic EL element 17 is provided above the TFT via an interlayer insulating film. A structure in which the EL element 17 is provided may be employed.

[Embodiment 7] In this embodiment, the TF of the present invention is used.
A semiconductor device incorporating an active matrix liquid crystal display device using a T circuit is described with reference to FIG.

Such semiconductor devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers,
TV and the like. One example of them is shown in FIG.

FIG. 17A shows a mobile phone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention is an audio output unit 900
2. The present invention can be applied to a display device 9004 including an audio input unit 9003 and an active matrix substrate.

FIG. 17B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention provides a voice input unit 9103,
910 provided with active matrix substrate
2. It can be applied to the image receiving unit 9106.

FIG. 17C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display device 9205. The present invention can be applied to the display device 9205 including the image receiving portion 9203 and the active matrix substrate.

FIG. 17D shows a head mounted display, which comprises a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 17E shows a rear type projector, which includes a main body 9401, a light source 9402, a display device 9403,
Polarizing beam splitter 9404, reflector 940
5, 9406 and a screen 9407. The invention can be applied to the display device 9403.

FIG. 17F shows a portable book, and a main body 95.
01, display devices 9502 and 9503, storage medium 950
4, comprising an operation switch 9505 and an antenna 9506 for displaying data stored on a mini disk (MD) or a DVD or data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

Although not shown here, the present invention is also applicable to a car navigation system and a display unit of an image sensor personal computer. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

[0088]

According to the present invention, a plurality of channel forming regions, a first impurity region of one conductivity type forming a source region or a drain region, and one end of an island-like semiconductor layer which is a component of a TFT are provided. Forming a second impurity region of one conductivity type formed in contact with the third impurity region and a second impurity region of one conductivity type formed at both ends in contact with the channel formation region; By forming the second impurity region and the plurality of channel formation regions so as to overlap with the gate electrode with the gate insulating film interposed therebetween, reliability can be improved. Further, a TFT of a pixel matrix circuit can be formed with a low off-state current.

Further, according to the present invention, a TFT can be formed more compactly than a conventional TFT having a multi-gate / multi-channel structure, and such a TFT can form a pixel matrix of an active matrix type liquid crystal display device. If a circuit is formed, the aperture ratio can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a logic circuit.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a logic circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a logic circuit.

FIG. 4 is a cross-sectional view of an active matrix liquid crystal display device.

FIG. 5 is a perspective view of an active matrix liquid crystal display device.

FIG. 6 is a top view of a pixel matrix circuit.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a driver circuit.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a driver circuit.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a driver circuit.

FIG. 14 illustrates a cross-sectional structure of a storage capacitor.

FIG. 15 illustrates a cross-sectional structure of a storage capacitor.

FIG. 16 is a circuit diagram and a cross-sectional structure diagram of an EL display device.

FIG. 17 illustrates an example of a semiconductor device.

[Explanation of symbols]

101, substrate 102, base film 103 to 106, island-shaped semiconductor layer 131, wiring from input / output terminals to input / output terminals of the drive circuit 132, 146, 147, 148 gate electrodes 135, 136 Gate wiring 161 first interlayer insulating film 162, 165, 166, 168 source electrode 163, 164, 167, 169 drain electrode 198, 200 source wiring 170 passivation film 171 light-shielding film 172 dielectric film 173 pixel electrode 210 second interlayer insulating film

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Satoshi Murakami 398 Hase, Hase, Atsugi-shi, Kanagawa Prefecture Inside the Semi-Conductor Energy Laboratory Co., Ltd. F term (reference) 5F048 AB10 AC04 BA16 BB09 BB11 BB12 BC06 BC11 BC16 BF02 BF07 BF12 BF16 BG01 BG03 BG07 DA18 DA20 5F110 AA04 AA06 AA28 AA30 BB02 BB04 BB10 CC02 DD01 DD02 DD03 DD13 DD14 EE02 FF03 GG30 GG32 GG34 GG43 GG45 HJ01 HJ04 HJ13 HJ23 HL02 HL03 HL07 HL12 HL23 HM14 HM15 NN02 NN03 NN22 NN23 NN24 NN27 NN35 NN36 NN46 NN47 NN54 NN73 NN74 PP02 Q03 Q24Q27 Q34

Claims (22)

[Claims] An island-shaped semiconductor layer formed on a substrate having an insulating surface, a gate insulating film formed in contact with the island-shaped semiconductor layer, and a gate insulating film in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer. The island-shaped semiconductor layer includes a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region. A third impurity region of one conductivity type formed in contact with the first impurity region; and a second impurity region of one conductivity type formed at one end in contact with the third impurity region. And a second impurity region of one conductivity type, both ends of which are formed in contact with the channel formation region, wherein the second impurity region and the plurality of channel formation regions form the gate insulating film. Overlaps with the gate electrode A semiconductor device characterized in that: 2. An island-shaped semiconductor layer on a substrate having an insulating surface, a gate insulating film formed in contact with the island-shaped semiconductor layer, and a gate insulating film in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer. The island-shaped semiconductor layer includes a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region. A second impurity region of one conductivity type, one end of which is formed in contact with the first impurity region; a second impurity region of one conductivity type, both ends of which are formed in contact with the channel formation region; Wherein the second impurity region and the plurality of channel formation regions overlap the gate electrode with the gate insulating film interposed therebetween. 3. A semiconductor device having a matrix circuit formed of n-channel thin film transistors, wherein the n-channel thin film transistors form a plurality of channel formation regions and a first conductivity type first region forming a source region or a drain region. An impurity region, a third impurity region of one conductivity type formed in contact with the first impurity region, and a second impurity region of one conductivity type formed at one end in contact with the third impurity region. And a second impurity region of one conductivity type, both ends of which are formed in contact with the channel formation region, wherein the second impurity region and the plurality of channel formation regions have a gate. A semiconductor device overlapped with one gate electrode provided corresponding to the n-channel thin film transistor with an insulating film interposed therebetween. 4. A semiconductor device having a CMOS circuit formed by an n-channel thin film transistor and a p-channel thin film transistor, wherein the plurality of n-channel thin film transistors form a plurality of channel formation regions and a source region or a drain region. A first impurity region of one conductivity type, a third impurity region of one conductivity type formed in contact with the first impurity region, and one end formed in contact with the third impurity region. A second impurity region of one conductivity type, and a second impurity region of one conductivity type formed at both ends in contact with the channel formation region; The channel formation region overlaps with one gate electrode provided corresponding to the n-channel thin film transistor via a gate insulating film. Semiconductor device. 5. A semiconductor device having a CMOS circuit formed by an n-channel thin film transistor and a p-channel thin film transistor, wherein the plurality of n-channel thin film transistors form a plurality of channel formation regions and a source region or a drain region. A first impurity region of one conductivity type, a second impurity region of one conductivity type formed at one end in contact with the first impurity region, and a second impurity region of one conductivity type formed at both ends in contact with the channel formation region. And a second impurity region of one conductivity type. The second impurity region and the plurality of channel formation regions are provided corresponding to the n-channel thin film transistor via a gate insulating film. A semiconductor device overlapping one of the gate electrodes. 6. A semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors, wherein the thin film transistor comprises: an island-shaped semiconductor layer; A gate insulating film formed in contact with the island-shaped semiconductor layer, and one gate electrode provided in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer; Forming a plurality of channel formation regions, a source region or a drain region, a first impurity region of one conductivity type, and a third impurity of one conductivity type formed in contact with the first impurity region. A region, which is provided so as to overlap with the gate electrode with a gate insulating film interposed therebetween, and one end of which is formed in contact with the third impurity region;
A second impurity region of one conductivity type, and a second impurity region of one conductivity type formed with both ends in contact with a channel formation region, wherein the storage capacitor has a first impurity region on the thin film transistor. A first insulating layer having an opening, a conductive film formed over the thin film transistor via the first insulating layer, a pixel electrode extending over the conductive film, And a dielectric film provided between the pixel electrode and the thin film transistor, wherein the semiconductor device is connected to the thin film transistor through the first opening. 7. A semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors, wherein the thin film transistor has an island-shaped semiconductor layer, A gate insulating film formed in contact with the island-shaped semiconductor layer, and one gate electrode provided in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer; Forming a plurality of channel formation regions, a source region or a drain region, a first impurity region of one conductivity type, and a third impurity of one conductivity type formed in contact with the first impurity region. A region, which is provided so as to overlap with the gate electrode with a gate insulating film interposed therebetween, and one end of which is formed in contact with the third impurity region;
A second impurity region of one conductivity type, and a second impurity region of one conductivity type formed with both ends in contact with a channel formation region, wherein the storage capacitor has a first impurity region on the thin film transistor. A first insulating layer having an opening, a second insulating layer having a second opening patterned on the first insulating layer and overlapping the first opening, A conductive film formed on the thin film transistor, a pixel electrode extending on the conductive film, a dielectric film provided between the conductive film and the pixel electrode, Wherein the semiconductor device is connected to the thin film transistor via the first opening and the second opening. 8. A semiconductor having a plurality of thin film transistors arranged in a matrix, a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors, and an alignment film formed on the pixel electrode. The device, wherein the thin film transistor is provided in correspondence with the island-shaped semiconductor layer, a gate insulating film formed in contact with the island-shaped semiconductor layer, and in contact with the gate insulating film, and corresponding to the island-shaped semiconductor layer. A single gate electrode, the island-shaped semiconductor layer includes a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and the first impurity A third impurity region of one conductivity type formed in contact with the region, a gate insulating film interposed therebetween, and a gate electrode overlapped with one end, and one end formed in contact with the third impurity region;
A second impurity region of one conductivity type, and a second impurity region of one conductivity type formed with both ends in contact with a channel formation region, wherein the storage capacitor has a first impurity region on the thin film transistor. A first insulating layer having an opening, a conductive film formed over the thin film transistor via the first insulating layer, a pixel electrode extending over the conductive film, and the conductive film. And a dielectric film provided between the pixel electrode and the pixel electrode, and connected to the thin film transistor through the first opening, and the alignment film is formed of the same material as the dielectric film. A semiconductor device characterized by being performed. 9. A semiconductor having a plurality of thin film transistors arranged in a matrix, a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors, and an alignment film formed on the pixel electrode. The device, wherein the thin film transistor is provided in contact with the island-shaped semiconductor layer, a gate insulating film formed in contact with the island-shaped semiconductor layer, and the gate insulating film, and provided in correspondence with the island-shaped semiconductor layer. A single gate electrode, the island-shaped semiconductor layer includes a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and the first impurity A third impurity region of one conductivity type formed in contact with the region, a gate insulating film interposed therebetween and provided over the gate electrode, and one end formed in contact with the third impurity region;
A second impurity region of one conductivity type, and a second impurity region of one conductivity type formed with both ends in contact with the channel formation region, wherein the storage capacitor has a first impurity region on the thin film transistor. A first insulating layer having an opening, a second insulating layer having a second opening patterned on the first insulating layer and overlapping the first opening, A conductive film formed on the thin film transistor via the first insulating layer; a pixel electrode extending on the conductive film; a dielectric film provided between the conductive film and the pixel electrode; , And connected to the thin film transistor via the first opening and the second opening, wherein the alignment film is formed of the same material as the dielectric film. Semiconductor device. 10. The semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device, an EL display device, or an image sensor. 11. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a mobile computer, a head-mounted display, a projector, a mobile book, a digital camera, a car navigation, a personal computer. A semiconductor device, characterized in that: 12. A step of forming an island-shaped semiconductor layer on a substrate having an insulating surface; a step of forming a gate insulating film in contact with the island-shaped semiconductor layer; Forming a first impurity region forming a source region or a drain region by adding to a selected region of the island-shaped semiconductor layer; and adding an impurity element of one conductivity type to the selected region of the island-shaped semiconductor layer. A third impurity region contacting the first impurity region; a second impurity region having one end contacting the third impurity region; a second impurity region having both ends contacting the channel forming region;
And a step of forming a gate electrode overlapping with the second impurity region with the gate insulating film interposed therebetween. 13. A step of forming an island-shaped semiconductor layer on a substrate having an insulating surface; a step of forming a gate insulating film in contact with the island-shaped semiconductor layer; Forming a first impurity region for forming a source region or a drain region by adding to a selected region of the island-shaped semiconductor layer; A second impurity region having one end in contact with the first impurity region; a second impurity region having both ends in contact with the channel formation region;
And a step of forming a gate electrode overlapping with the second impurity region with the gate insulating film interposed therebetween. 14. A method for manufacturing a semiconductor device having a matrix circuit formed of n-channel thin film transistors, wherein the n-channel thin film transistors form an island-shaped semiconductor layer on a substrate having an insulating surface; Forming a gate insulating film in contact with the island-shaped semiconductor layer; and adding a one-conductivity-type impurity element to a selected region of the island-shaped semiconductor layer to form a source region or a drain region. Forming an impurity region; adding a one-conductivity-type impurity element to a selected region of the island-shaped semiconductor layer to form a third impurity region in contact with the first impurity region; A second impurity region in contact with the impurity region of the second, a second impurity region in which both ends are in contact with the channel forming region,
And a step of forming a gate electrode overlapping the second impurity region with the gate insulating film interposed therebetween. 15. A method for manufacturing a semiconductor device having a CMOS circuit formed of an n-channel thin film transistor and a p-channel thin film transistor, wherein the n-channel thin film transistor has an island-shaped semiconductor layer formed on a substrate having an insulating surface. Forming a gate insulating film in contact with the island-shaped semiconductor layer; adding one conductivity type impurity element to a selected region of the island-shaped semiconductor layer to form a source region or a drain region Forming a first impurity region for forming a first impurity region; adding a first conductivity type impurity element to a selected region of the island-shaped semiconductor layer to form a third impurity region in contact with the first impurity region; A second impurity region having one end in contact with the third impurity region, a second impurity region having both ends in contact with the channel formation region,
And a step of forming a gate electrode overlapping the second impurity region with the gate insulating film interposed therebetween. 16. A method for manufacturing a semiconductor device having a CMOS circuit formed of an n-channel thin film transistor and a p-channel thin film transistor, wherein the n-channel thin film transistor has an island-shaped semiconductor layer formed on a substrate having an insulating surface. Forming a gate insulating film in contact with the island-shaped semiconductor layer; adding one conductivity type impurity element to a selected region of the island-shaped semiconductor layer to form a source region or a drain region Forming a first impurity region forming a first impurity region; adding a one conductivity type impurity element to a selected region of the island-shaped semiconductor layer; and forming a second impurity having one end in contact with the first impurity region. A second impurity region having both ends in contact with the channel forming region;
And a step of forming a gate electrode overlapping the second impurity region with the gate insulating film interposed therebetween. 17. A method for manufacturing a semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors, wherein the thin film transistor is formed on a substrate having an insulating surface. Forming an island-shaped semiconductor layer; forming a gate insulating film in contact with the island-shaped semiconductor layer; adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer. Forming a first impurity region for forming a source region or a drain region; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer. A third impurity region in contact with the second impurity region having one end in contact with the third impurity region, a second impurity region having both ends in contact with the channel formation region,
Forming a gate electrode that overlaps the second impurity region via the gate insulating film. The storage capacitor has a first opening on the thin film transistor. Forming a first insulating layer, forming a conductive film on the thin film transistor via the first insulating layer, and forming a dielectric film on the conductive film; Forming a pixel electrode extending over the conductive film with the dielectric film interposed therebetween. 18. A method for manufacturing a semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors, wherein the thin film transistors are formed on a substrate having an insulating surface. Forming an island-shaped semiconductor layer, forming a gate insulating film in contact with the island-shaped semiconductor layer, adding one conductivity type impurity element to a selected region of the island-shaped semiconductor layer. Forming a first impurity region forming a source region or a drain region; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer. A third impurity region in contact with the second impurity region having one end in contact with the third impurity region, a second impurity region having both ends in contact with the channel formation region,
Forming a gate electrode overlapping with the second impurity region via the gate insulating film. The storage capacitor includes a first opening on the thin film transistor. Forming a first insulating layer having; and forming a second insulating layer having, on a part of the first insulating layer, a second opening overlapping with the first opening. Forming a conductive film on the thin film transistor via the first insulating layer; forming a dielectric film on the conductive film; and forming the conductive film through the dielectric film. Forming a pixel electrode on a film by extending the pixel electrode. 19. A semiconductor device comprising: a plurality of thin film transistors arranged in a matrix; a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors; and an alignment film formed on the pixel electrode. In the method for manufacturing a semiconductor device, the thin film transistor includes: a step of forming an island-shaped semiconductor layer over a substrate having an insulating surface; a step of forming a gate insulating film in contact with the island-shaped semiconductor layer; Forming a first impurity region forming a source region or a drain region by adding an impurity element of the formula (1) to a selected region of the island-shaped semiconductor layer; A third impurity region in contact with the first impurity region, a second impurity region having one end in contact with the third impurity region, and a chamfer at both ends. A second impurity region in contact with the Le forming region,
Forming a gate electrode that overlaps the second impurity region via the gate insulating film. The storage capacitor has a first opening on the thin film transistor. Forming a first insulating layer, forming a conductive film on the thin film transistor via the first insulating layer, and forming a dielectric film on the conductive film; Forming the pixel electrode on the conductive film through the dielectric film, wherein the alignment film is formed of the same material as the dielectric film. Of manufacturing a semiconductor device. 20. A semiconductor device comprising: a plurality of thin film transistors arranged in a matrix; a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors; and an alignment film formed on the pixel electrode. In the method for manufacturing a semiconductor device, the thin film transistor includes: a step of forming an island-shaped semiconductor layer over a substrate having an insulating surface; a step of forming a gate insulating film in contact with the island-shaped semiconductor layer; Forming a first impurity region forming a source region or a drain region by adding an impurity element of the formula (1) to a selected region of the island-shaped semiconductor layer; A third impurity region in contact with the first impurity region, a second impurity region having one end in contact with the third impurity region, and a chamfer at both ends. A second impurity region in contact with the Le forming region,
Forming a gate electrode that overlaps the second impurity region via the gate insulating film. The storage capacitor has a first opening on the thin film transistor. Forming a first insulating layer having; and forming a second insulating layer having, on a part of the first insulating layer, a second opening overlapping with the first opening. Forming a conductive film on the thin film transistor via the first insulating layer; forming a dielectric film on the conductive film; and forming the conductive film through the dielectric film. Forming the pixel electrode on a film by extending the pixel electrode. The method of manufacturing a semiconductor device, wherein the alignment film is formed of the same material as the dielectric film. 21. The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor device is a liquid crystal display device, an EL display device, or an image sensor. 22. The semiconductor device according to claim 12, wherein the semiconductor device is a mobile phone, a video camera, a mobile computer, a head mounted display, a projector, a mobile book, a digital camera, a car navigation, a personal computer. A method for manufacturing a semiconductor device.