JP2000349290A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent occurrence of the failures caused by the contraction of a glass substrate. SOLUTION: The glass substrate of a semiconductor device is contracted in advance by crystallizing an amorphous silicon film through heat treatment of about 500-650 deg.C in a preceding process of photolithography processes. In the succeeding manufacturing processes, the contraction of the glass substrate is prevented, by preventing the temperature of the glass substrate from rising to 550 deg.C or higher. After the heat treatment, in addition, alignment markers are formed. In the photolithographic processes, mask alignment can be carried out by using the alignment markers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit formed of thin film transistors (hereinafter, referred to as TFTs) on a substrate having an insulating surface, and a method for manufacturing the same. In particular, the present invention can be suitably used for an electro-optical device typified by a liquid crystal display device in which a pixel matrix circuit and a control circuit provided therearound are provided on the same substrate, and an electronic apparatus equipped with the electro-optical device. Note that in this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic device including the electro-optical device.

[0002]

2. Description of the Related Art Development of a semiconductor device having a circuit formed by a TFT on a substrate having an insulating surface is in progress. An active matrix liquid crystal display device is well known as a typical example. Among them, a TFT having an active layer formed of a crystalline silicon film (hereinafter, referred to as a crystalline silicon TFT) has a high field-effect mobility, so that various functional circuits can be formed. An electro-optical device integrally formed thereon has been developed.

For example, an active matrix type liquid crystal display device is provided with a pixel matrix circuit for performing image display, a control circuit for performing image display, and the like. The control circuit includes a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like that are formed based on a CMOS circuit. In an active matrix display device, a pixel matrix circuit and a control street can be formed on the same substrate by using a crystalline silicon TFT.

[0004]

In order to satisfy the demand for a large screen and low price of the display device, it is required to use a glass substrate. However, the glass substrate is much less susceptible to thermal effects than the quartz substrate, close to the strain point,
It shrinks when heated at about 0 ° C for several hours. In a TFT manufacturing process, a process of heating a substrate at 500 ° C. or higher, for example, a thermal crystallization process of a silicon film, a process of activating impurities added to a source or a drain, and the like are processes in which shrinkage of a glass substrate is concerned. . If the glass substrate shrinks during the manufacturing process and the shrinkage is large, mask alignment in the subsequent photolithography process becomes impossible, resulting in a defective substrate. As a result, the yield decreases.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent the occurrence of a defect due to the shrinkage of a substrate and improve the yield of semiconductor devices.

[0006]

In order to solve the above-mentioned problems, the present invention provides a process of forming an amorphous semiconductor film on a glass substrate, and a step of heat-treating the amorphous semiconductor film to form a crystalline semiconductor film. Forming a silicon film, wherein in the steps subsequent to the step of forming the crystalline silicon film, the temperature of the glass substrate is not higher than the substrate temperature in a heat treatment step. A method for manufacturing a semiconductor device, comprising:

In the present invention, in a step prior to the photolithography step, the glass substrate is previously heat-treated at 500 ° C. or more, more preferably 550 ° C. or more, to shrink it. The process is simplified by combining this heat treatment and the crystallization of the amorphous semiconductor film. Note that the upper limit of the heat treatment of the glass substrate is, of course, not more than the strain point of the glass substrate.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION A glass substrate is prepared, and a silicon oxide film is formed on the surface to prevent impurity contamination from the glass substrate.
A base film such as a silicon nitride film is formed. An amorphous semiconductor film such as amorphous silicon is formed over the base film.

[0009] 500-650 ° C or more, more preferably 5
The amorphous silicon film is solid-phase grown and crystallized by a heat treatment at about 50 to 600 ° C. To crystallize at a temperature of 600 ° C. or less for a short time and about 2 to 8 hours, see Japanese Patent Application Laid-Open No.
It is preferable to use the crystallization technique disclosed in JP-A-130652. This crystallization technique uses Ni, Co, F
e, Ru, Rh, Pd, Os, Ir, Pt, Cu, A
A small amount of u, Ge catalyst elements are added to the amorphous semiconductor film,
This is a heat treatment method, which has the effect of increasing the crystal grain size as well as reducing the temperature and time of the crystallization step.

In the present invention, the glass substrate is preliminarily shrunk in this crystallization step, and in the subsequent steps, the substrate temperature is kept below the crystallization step to avoid shrinking the glass substrate.
Further, in the present invention, by shrinking the glass substrate before forming the alignment marker, the alignment of the mask can be performed using the alignment marker without considering the initial shrinkage of the glass substrate.

That is, in the process before forming the alignment marker, the substrate temperature is set to the highest temperature in the manufacturing process, and the glass substrate is shrunk at this time, and the glass substrate is shrunk in the subsequent processes. It is not to be characterized.

Further, by forming an alignment marker after the step in which the substrate temperature reaches the highest temperature in all the steps, it becomes possible to align all the photolithography masks and the substrate using this alignment marker. .

In the present invention, the temperature of the substrate after the crystallization step does not exceed the heat treatment temperature for the previous crystallization, and the amount of deformation of the 10 cm square glass substrate does not exceed 20 ppm. If the amount of deformation is 20 ppm or less,
By the alignment marker formed in the semiconductor film,
Positioning of a substrate and a photolithography mask can be performed. For this reason, the substrate temperature after the crystallization step is 550 ° C. or less, preferably 525 ° C., more preferably 5 ° C.
It should be below 00 ° C.

After the crystallization step, the step of raising the substrate temperature is to activate the impurities added to the source and drain. However, it is possible to activate the impurities at a substrate temperature of 500 to 550 ° C. Yes, and laser activation by excimer laser can be used instead of thermal activation.

[0015]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, a method of simultaneously manufacturing a pixel matrix circuit and a TFT of a control circuit provided around the pixel matrix circuit will be described. However, for the sake of simplicity, the control circuit shows a CMOS circuit as a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

In FIG. 1A, a low alkali glass substrate is used as a substrate 201. A base film 202 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a surface of the substrate 201 where a TFT is to be formed, in order to prevent impurity diffusion from the substrate 201. For example, a silicon oxynitride film formed by plasma CVD using SiH ₄ , NH ₃ , and N ₂ O as a source gas is 100 nm, and a silicon oxynitride film similarly formed from SiH ₄ , N ₂ O is 200 nm. It is preferable to form a laminate with a thickness of.

Next, 20 to 150 nm (preferably 30 to 150 nm)
Semiconductor film 203 having an amorphous portion with a thickness of 80 nm)
Is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. Examples of the semiconductor film having an amorphous portion include an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous portion such as an amorphous silicon germanium film may be used. Since the base film 202 and the amorphous silicon film 203a can be formed by the same film formation method, both may be formed continuously. After the formation of the base film, the surface of the base film can be prevented from being contaminated by not exposing it to the air atmosphere, and the variation in the characteristics of the TFT to be manufactured and the change over time in the threshold voltage can be reduced. (Fig. 1 (A))

Then, the amorphous silicon film is heat-treated,
From the amorphous silicon film 203a to the crystalline silicon film 203
b is formed. Here, the crystalline silicon film 203b is formed by a crystallization method using a catalytic element according to the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652. A nickel acetic acid solution is applied to the surface of the amorphous silicon film 203a by a spin coater and then heat-treated at 550 ° C. for 4 hours to form a crystalline silicon film 203b. In this step, the glass substrate 201 is contracted in advance.

Prior to the crystallization step, depending on the hydrogen content of the amorphous silicon film, heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content to 5 atomic% or less, and then the crystallization is performed. It is desirable to make it. When the amorphous silicon film is crystallized, rearrangement of atoms occurs and the film becomes denser. Therefore, the thickness of the crystalline silicon film is 1 to less than the initial thickness of the amorphous silicon film (55 nm in this embodiment). It is reduced by about 15%. (FIG. 1 (B))

The crystalline silicon film 203b is patterned into islands to form island-like semiconductor layers 204 to 207.
(FIG. 1C) At this time, an alignment marker 501 is also formed on the silicon film 203b.

FIG. 6 explains the position where the alignment marker is formed. FIG. 6 is a top view of the substrate 201, in which a pixel matrix circuit 502, a scanning signal control circuit 503, and an image signal control circuit 504 are integrated on the same substrate. Alignment marker portions 511 to 5 are provided on two opposite sides of the substrate.
16 are formed. Here, the alignment markers are formed at three places on one side, but the number and position of the alignment marker portions and the marker patterns are not limited to the present embodiment.

As shown in FIG. 7, the crystalline silicon film 20
3b, the alignment marker 51
Markers 521, 522, and 523 made of the crystalline silicon film 203b are formed on 1 to 516. FIG. 7 (A)
Is a top view of the marker portion, and FIG. 7B is a line YY ′.
FIG.

The marker 521 includes a rectangular portion 521a whose inside is extracted and a marker 5 serving as a horizontal index.
21b and a marker 251c serving as an index in the vertical direction. Markers 521 and rectangular patterns 522 are alternately arranged in rows. In the markers 521 arranged in a matrix like this, the markers 521b and 521c
By measuring the change in pitch, the amount of deformation of the substrate in the vertical and horizontal directions can be measured.

After patterning of the crystalline silicon film 203b, 50 to 1
A mask layer 208 of a silicon oxide film having a thickness of 00 nm is formed. A resist mask 209 is formed over the mask layer 208. At this time, a resist having a predetermined pattern is also formed on the alignment marker portions 511 to 516 to confirm alignment.

A p-type is applied to the entire surface of the island-shaped semiconductor layers 210 to 212 forming the n-channel TFT at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ for the purpose of controlling the threshold voltage. Boron (B) is added as an impurity element.
Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Here, it is preferable to add boron (B) to keep the threshold voltage of the n-channel TFT within a predetermined range. (Fig. 1 (D))

In order to form an LDD region of an n-channel TFT of a control circuit, an impurity element imparting n-type is selectively added to the island-shaped semiconductor layers 210 and 211. For this purpose, resist masks 213 to 216 are formed. Further, to confirm the alignment, the alignment marker 511 is used.
516 are also formed with a predetermined pattern of resist.

As the impurity element imparting n-type, phosphorus
(P) or arsenic (As) may be used.
Phosphine (PH) to add (P)_Three) Ion
The doping method is used. Impurity regions 217, 21 formed
8 has a phosphorus (P) concentration of 2 × 10 ¹⁶~ 5 × 10¹⁹atoms / c
m^ThreeShould be within the range. Included in impurity regions 223-230
The concentration of the impurity element imparting n-type^-)
Symbol. The impurity region 219 is used for the pixel matrix circuit.
This is the semiconductor layer for forming the storage capacitance of the circuit.
Phosphorus (P) is also added to the region at the same concentration. (Figure 1
(E))

Next, a step of removing the mask layer 208 with hydrofluoric acid or the like and activating the impurity element added in FIGS. 1D and 1E is performed. In this embodiment, a linear beam is formed by using a KrF excimer laser beam (wavelength: 248 nm) using a laser activation method, an oscillation frequency of 5 to 50 Hz, an energy density of 100 to 500 mJ / cm ^2, and a linear beam. Scanning is performed with a beam overlap ratio of 80 to 98%, and the entire surface of the substrate on which the semiconductor layer is formed is processed.

The gate insulating film 220 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm by using a plasma CVD method or a sputtering method. For example, a silicon oxynitride film is formed to a thickness of 120 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (Fig. 2 (A))

Next, a conductive film serving as a gate electrode and a gate wiring is formed. This conductive film may be formed of a single-layer conductive film, but preferably has a stacked structure of two or three layers as necessary. In this embodiment, a stacked film including the first conductive film 221 and the second conductive film 222 is formed. As the first conductive film 221 and the second conductive film 222, an element selected from Ta, Ti, Mo, W, and Cr, or a conductive film containing the above elements as a main component (typically, a tantalum nitride film, a tungsten nitride film, Film, a titanium nitride film), or an alloy film combining the above elements (typically, Mo-W
An alloy film, a Mo—Ta alloy film), or a silicide film of the above element (typically, a tungsten silicide film or a titanium silicide film) can be used.

The first conductive film 221 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the second conductive film 222 has a thickness of 200 to 50 nm.
The thickness may be 400 nm (preferably 250 to 350 nm). In this embodiment, a 30 nm thick tantalum nitride film is used for the first conductive film, and a 350 nm Ta film is used for the second conductive film.
All are formed by a sputtering method. In the film formation by this sputtering method, an appropriate amount of Xe or Kr is added to Ar of the sputtering gas.
Is added, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film under the first conductive film 221 with a thickness of about 2 to 20 nm. Thereby, it is possible to improve the adhesion of the conductive film formed thereon and prevent oxidation. (FIG. 2 (B))

Next, resist masks 223 to 227 are formed, and the first conductive film 221 and the second conductive film 222 are collectively etched to form gate electrodes 228 to 231, a gate wiring (wiring connected to the gate electrode), The capacitor wiring 232 is formed. The gate electrodes 234 and 235 formed in the control circuit are partially formed with the impurity regions 217 and 218 and the gate insulating film 22.
It is formed so as to overlap with 0. (Fig. 2 (C))

At the same time as the formation of the gate electrodes 228 to 231, as shown in FIG. 8, alignment markers 531 and 532 composed of the first conductive film 221 and the second conductive film 222 are formed.
Is formed. Further, a marker 534 overlapping with the alignment markers 521 and 522 by the conductive films 221 and 222 is also formed. FIG. 8A is a top view,
FIG. 8B is a cross-sectional view taken along line YY ′ in FIG.

As shown in FIG. 8A, the conductive film 221,
Each of the alignment markers 531 and 532 made of 222 is an alignment marker 5 made of a crystalline silicon film.
21 and 522, which are alternately arranged in one row.

Using the gate electrode and the capacitor wiring as a mask, the gate insulating film 220 is etched so that the gate insulating films 233 to 236 remain under the gate electrode to expose a part of the island-shaped semiconductor layer. At this time, the insulating film 237 is also formed below the capacitor wiring. This is performed in order to efficiently add an impurity element in a step of adding an impurity element for forming a source region or a drain region in a later step. This step is omitted, and the gate insulating film is omitted. May be left on the entire surface of the island-shaped semiconductor layer. (FIG. 2 (D))

By the etching process of the gate insulating film 220, the markers 531 and 532 are used as masks in the alignment marker portions 511 to 516, as shown in FIG.
The gate insulating film 220 is etched as shown in FIG.

Next, in order to form a source region and a drain region of the p-channel TFT of the control circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 228 as a mask. At this time, the region where the n-channel TFT is to be formed is covered with a resist mask 238. Then, an impurity region 239 is formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the impurity region 23 formed here is used.
The concentration of the impurity element imparting p-type contained in No. 9 is represented by (p ⁺ ). (FIG. 3 (A))

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 240 to 242 are formed so as to cover the gate electrode and a region to be a p-channel TFT. At this time, a pattern made of a resist is formed on the alignment marker portions 511 to 516 to confirm the alignment.

Using the resist masks 240 to 242,
The impurity region 243 is added by adding an impurity element imparting n-type.
To 247. This is a phosphine (PH_Three)
Of phosphorus (P) in this region
Concentration 1 × 10²⁰~ 1 × 10 ^{twenty one}atoms / cm^ThreeAnd Honcho
In the detailed description, the impurity regions 214 to 21 formed here are used.
8, the concentration of the impurity element imparting n-type
(N⁺). (FIG. 3 (B))

The impurity regions 243 to 247 contain phosphorus (P) or boron (B) already added in the previous step, but phosphorus (P) is added at a sufficiently high concentration. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step. Since the concentration of phosphorus (P) added to the impurity region 243 is １ ／ to １ ／ of the concentration of boron (B) added in FIG.
The conductivity of the mold was ensured, and the characteristics of the TFT were not affected at all.

Next, the resist mask is removed, and at least the gate electrodes 228 to 231 and the gate insulating films 233 to 231 are removed.
The cap layer 248 to cover the side surface of
It is formed to a thickness of 0 nm. The cap layer may be formed using a silicon nitride film or a silicon oxynitride film. In this embodiment,
A silicon oxynitride film is formed to a thickness of 100 nm by a plasma CVD method.

An n-channel TFT of a pixel matrix circuit
In order to form the LDD region of FIG. Here, an impurity element imparting n-type conductivity is added to the island-shaped semiconductor layer thereunder via the cap layer 248 by an ion doping method. The concentration of phosphorus (P) added here is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3, which is higher than the concentration of the impurity element added in FIGS. 1 (E), 3 (A) and 3 (B). Was also added at a low concentration, so that only the impurity regions 249 and 250 were formed. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 223 to 230 formed here is expressed as (n ⁻ ). (FIG. 3 (C))

The impurity regions 249 and 250 are formed outside the gate electrode by the thickness of the cap layer formed on the side walls of the gate electrode and the gate insulating film. That is, an offset area is formed. No impurity element is added to the offset region by the ion doping method, and the offset region is formed with the same composition as the channel formation region. The length of the offset region can be controlled by appropriately selecting the thickness of the cap layer.

After the doping step, a protective insulating film 251 to be a part of the first interlayer insulating film is formed. Protective insulating film 2
51 may be formed of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film combining these. Further, the film thickness may be 100 to 400 nm.

Thereafter, n added at each concentration
A heat treatment step is performed to activate the impurity element imparting the mold and the p-type. Here, activation is performed by a furnace annealing method. The heat treatment is performed in a nitrogen atmosphere at 300 to 55
Heat at 0 ° C, more preferably at 500-550 ° C. Here, heat treatment is performed at 500 ° C. for 4 hours. After a heat treatment in a nitrogen atmosphere, the heat treatment is performed in an atmosphere containing 3 to 100% hydrogen.
Heat treatment is performed at 00 to 450 ° C. for 1 to 12 hours to hydrogenate the island-shaped semiconductor layer. In this step, dangling bonds in the active layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When the island-like semiconductor layer is formed from an amorphous silicon film by a crystallization method using a catalyst element, a trace amount of the catalyst element remains in the island-like semiconductor layer. Of course, it is possible to complete the TFT in such a state,
It was more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalyst element is a method utilizing a gettering action by phosphorus (P). By selectively adding phosphorus to the semiconductor film,
When the heat treatment is performed at about 500 ° C. to 800 ° C., the catalyst element in the region where phosphorus is not added diffuses into the region where phosphorus is added and gettering is performed. Further, it has been found that a region to which both phosphorus and boron are added also functions as a gettering sink, and only when boron is added more than phosphorus does it function as a gettering sink.

The concentration of phosphorus (P) necessary for gettering is substantially the same as that of the impurity region (n ⁺ ) formed in FIG. 3B, and the temperature is 500 ° C. in the activation step performed here. By the heat treatment, the catalytic element is removed from the channel forming regions of the n-channel TFT and the p-channel TFT to the impurity region 2.
43 to 247.
(FIG. 3 (D))

In this embodiment, since the glass substrate was previously shrunk in the crystallization step, the amount of shrinkage of the substrate was suppressed to 20 ppm or less by heat treatment at 500 to 550 ° C. for thermal activation / gettering. Therefore, it is possible to prevent the occurrence of defects due to the shrinkage of the substrate. The amount of shrinkage can be confirmed by the alignment marker shown in FIG.

After completion of the activation step, an interlayer insulating film 252 having a thickness of 500 to 1500 nm is formed on the protective insulating film 251. A laminated film including the protective insulating film 251 and the interlayer insulating film 252 is referred to as a first interlayer insulating film. (FIG. 4 (A))

Thereafter, a resist mask having a predetermined pattern is formed to form a contact hole. At this time, to check the alignment,
A marker made of resist is formed. The interlayer insulating film is etched using a resist mask, and each TFT
A contact hole reaching the source region or the drain region is formed.

The source wirings 253 to 256 and the drain wirings 257 to 259 are formed. Although not shown, in the present embodiment, this electrode is a three-layer laminated film in which a Ti film is formed to a thickness of 100 nm, an aluminum film containing Ti is formed to a thickness of 300 nm, and a Ti film is formed to a thickness of 150 nm. (FIG. 4
(B))

Further, as shown in FIG.
At the same time as the formation of 59, the alignment marker portions 511-
516, an alignment marker 541 made of a Ti film;
542 are formed. Alignment markers 541, 54
Reference numeral 2 denotes markers 521 and 522 made of silicon formed in the same pattern and the same arrangement. In addition, the marker 544 made of a Ti film is replaced with the markers 521, 522, and the marker 53.
1, 532 are formed.

Next, as the passivation film 260,
A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed to a thickness of 50 to 500 nm (typically, 100 to 300 nm).
m). It is preferable to perform hydrogenation treatment in this state for improving the characteristics of the TFT. For example, 3-10
In an atmosphere containing 0% hydrogen at 300-450 ° C.
Heat treatment for 12 hours is preferably performed. Alternatively, the same effect can be obtained by using a plasma hydrogenation method. Here, at the position where a contact hole for connecting the pixel electrode and the drain wiring is formed later, the passivation film 2 is formed.
An opening may be formed in 60. (FIG. 5 (A))

Thereafter, a second interlayer insulating film 261 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, it is formed by baking at 300 ° C. using a type of polyimide which is thermally polymerized after being applied to the substrate. Then, a contact hole reaching the drain wiring 259 is formed in the second interlayer insulating film 261, and a pixel electrode 262 is formed. As the pixel electrode 262, a transparent conductive film may be used in the case of a transmissive liquid crystal display device, and a metal film may be used in the case of a reflective liquid crystal display device.
In this embodiment, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method to obtain a transmission type liquid crystal display device. (FIG. 5 (B))

Thus, an active matrix substrate having a control circuit and a pixel matrix circuit on the same substrate is completed. The control circuit includes a p-channel TFT 285 and a first
N-channel TFT 286, second n-channel TF
T287, n-channel TFT for pixel matrix circuit
A pixel TFT 288 is formed.

The p-channel TFT 285 of the control circuit has a channel formation region 263, a source region 264, and a drain region 265. First n-channel type TF
In T286, the channel formation region 266 and the Lov region 26
7, a source region 268 and a drain region 269.

The Lov region is an impurity region that overlaps the gate electrode with the gate insulating film interposed. TFT2
The length of the 85 Lov region in the channel length direction is 0.5-3.
0 μm, preferably 1.0 to 1.5 μm.

The second n-channel type TFT 287 has a channel forming region 270, LDD regions 271 and 272, a source region 273, and a drain region 274. This LDD region is divided into a Lov region and an Loff region.

The Loff region refers to an impurity region offset from the gate electrode with the gate insulating film interposed. TF
The length in the channel length direction of the Loff region of T287 is 0.3
To 2.0 μm, preferably 0.5 to 1.5 μm.

N-channel TFT of pixel matrix circuit
288 includes channel formation regions 275 and 276, Loff
Regions 277 to 280 are provided. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.
5 to 2.5 μm. The Loff region is offset with respect to the gate electrode, and the length of the offset region is 0.0
2 to 0.2 μm. Further, a capacitor wiring 232 formed at the same time as the gate electrode, an insulating film made of the same material as the gate insulating film, and a semiconductor layer doped with an impurity element imparting n-type and connected to the drain region 283 of the n-channel TFT 288. 284 form a storage capacitor 289. In this embodiment, the n-channel TFT 287 of the pixel matrix circuit has a double gate structure, but may have a single gate structure. A multi-gate structure including a plurality of gate electrodes can reduce current leakage in an off state.

[Embodiment 2] This embodiment will be described with reference to FIG. In the present embodiment, the pixel matrix circuit and the TF of the control circuit provided around the pixel matrix circuit are different from those in the first embodiment.
This is an example of manufacturing T at the same time.

First, FIG. 1A to FIG.
Steps up to FIG. 2C are performed. The cap layer 301 covers at least the side surfaces of the gate electrodes 228 to 231.
To form The cap layer may be formed of a silicon nitride film or a silicon oxynitride film with a thickness of 25 to 200 nm. In this embodiment, a silicon oxynitride film is formed to a thickness of 100 nm by a plasma CVD method. Then, the cap layer 301
Then, an impurity element imparting n-type is added to the island-shaped semiconductor layer therebelow by ion doping to form an impurity region 303 to be an LDD region of an n-channel TFT of the pixel matrix circuit. Here, the concentration of phosphorus (P) to be added is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . (Figure 1
0 (A))

Then, using the gate electrode and the capacitor wiring as a mask, the gate insulating film 220 is etched so that at least the gate insulating films 233 to 236 remain under the gate electrode to expose a part of the island-shaped semiconductor layer. I let it.
(At this time, the insulating film 237 is also formed below the capacitor wiring.) This is performed in order to efficiently perform a step of adding an impurity element to the source region or the drain region in a later step. This step may be omitted, and the gate insulating film may be left on the entire surface of the island-shaped semiconductor layer.
(FIG. 10B)

The subsequent steps may be performed in the same manner as in the first embodiment (the step of FIG. 3C is omitted), and the active matrix substrate shown in FIG. 5B can be manufactured.

[Embodiment 3] This embodiment will be described with reference to FIG. 11 using a pixel matrix circuit and T of a control circuit provided therearound.
Another configuration in the case where the FT is manufactured at the same time will be described.

First, the steps up to FIG. 3B were performed in the same manner as in Example 1. Here, in FIG. 11A, the first wirings 403 and 404 are formed simultaneously with the same material as the gate electrode. The insulating films 401 and 402 are the gate insulating film 2
It is formed of the same material as 20. Then, a cap layer 248 is formed to cover at least the side surface of the gate electrode. The cap layer may be formed of a silicon nitride film or a silicon oxynitride film with a thickness of 25 to 200 nm.

In this embodiment, a silicon oxynitride film is formed to a thickness of 100 nm by a plasma CVD method. Then, an impurity element imparting n-type conductivity is added to the island-like semiconductor layer thereunder via the cap layer 248 by an ion doping method, and the LDD of the n-channel TFT of the pixel matrix circuit is added.
An impurity region to be a region is formed. Here, the concentration of phosphorus (P) to be added is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . (FIG. 11A)

After that, the cap layer 248 is removed by etching using hydrofluoric acid or the like. Then, as shown in FIG. 11B, second wirings 405 and 406 made of a conductive film such as aluminum (Al) or copper (Cu) are
3, a pattern is formed on 404. Then, a first interlayer insulating film 407 made of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like is formed. Subsequent steps may be performed in the same manner as in Embodiment 1. A source or drain wiring, a passivation film, a second interlayer insulating film, and a pixel electrode are formed to complete the active matrix substrate shown in FIG.

The first wiring 403 and the second wiring 405 and the first wiring 404 and the second wiring 406 are integrally formed, and the wiring from the input / output terminal to the input / output end of each circuit and the pixel matrix circuit Provided as part of the gate wiring. A
The second wirings 405 and 406 are formed of a low resistance material such as l or Cu.
Is provided, the wiring resistance is reduced, and it is possible to cope with a large-screen direct-view display device (20-inch class or more).

[Embodiment 4] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 12, an alignment film 601 is formed on the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. A light-shielding film 603, a transparent conductive film 604, and an alignment film 605 are formed on the opposite substrate 602 on the opposite side. After forming the alignment film, a rubbing treatment is performed so that the liquid crystal molecules are aligned with a certain pretilt angle.

The pixel matrix circuit and the CMOS
The active matrix substrate on which the circuit is formed and the opposing substrate are attached to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. afterwards,
A liquid crystal material 606 is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 12 is completed.

The configuration of this active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 13 and the top view of FIG. 13 and 14 use the same reference numerals in order to correspond to the sectional structural views of FIGS. 1 to 5 and 12. The cross-sectional structure along AA ′ shown in FIG. 14 corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG.

The active matrix substrate includes a pixel matrix circuit 701 formed on the glass substrate 201,
It is composed of a scanning signal control circuit 702 and an image signal control circuit 703. N-channel type TF for pixel matrix circuit
T288 is provided, and a driver circuit provided in the periphery is configured based on a CMOS circuit. Each of the scanning signal control circuit 702 and the image signal control circuit 703 includes a gate wiring 231 (connected to a gate electrode and denoted by the same reference sign in the sense that it is formed to extend) and a source wiring 25.
6 is connected to the n-channel TFT 288 of the pixel matrix circuit. The FPC 731 is connected to the external input / output terminal 7
34.

FIG. 14 is a top view showing a part (almost one pixel) of the pixel matrix circuit 701. Gate wiring 2
Reference numeral 31 intersects an active layer therebelow via a gate insulating film (not shown). Although not shown, the active layer, a source region, a drain region, n ^- comprised in the region Lof
An f region is formed. 290 is the source wiring 2
Reference numeral 292 denotes a contact portion between the drain wiring 259 and the drain region 283, and reference numeral 292 denotes a contact portion between the drain wiring 259 and the pixel electrode 262. The storage capacitor 289 is an n-channel type T
It is formed in a region where the capacitor wiring 232 overlaps with the semiconductor layer 284 integrated with the drain region of the FT 288 and the gate insulating film.

Although the active matrix type liquid crystal display device of the present embodiment has been described with reference to the structure described in the first embodiment, the active matrix type liquid crystal display device can be freely combined with any of the configurations of the first to third embodiments. A display device can be manufactured.

[Embodiment 5] FIG. 15 shows Embodiments 1 to 3.
FIG. 2 is a diagram showing an example of a circuit configuration of an active matrix substrate shown in FIG. The active matrix substrate of this embodiment includes an image signal control circuit 1001, a scan signal control circuit (A) 1007, a scan signal control circuit (B) 1011, and a precharge circuit 101.
2. It has a pixel matrix circuit 1006. In addition,
The control circuit described in this specification is a general term including the image signal control circuit 1001 and the scanning signal control circuit (A) 1007.

The image signal control circuit 1001 includes a shift register circuit 1002, a level shifter circuit 1003, a buffer circuit 1004, and a sampling circuit 1005. The scan signal control circuit (A) 1007 includes a shift register circuit 1008, a level shifter circuit 1009, and a buffer circuit 1010. The scanning signal control circuit (B) 1011 has a similar configuration.

The shift register circuits 1002 and 1008 have a drive voltage of 5 to 16 V (typically 10 V). The n-channel TFT of the CMOS circuit forming this circuit has a structure indicated by 286 in FIG. 5B. Is suitable.

The level shifter circuits 1003 and 100
9 and the buffer circuits 1004 and 1010 have a drive voltage of 14
Up to 16V, but like the shift register circuit,
CMOS including n-channel TFT 286 in FIG.
Circuit is suitable. In these circuits, forming the gate in a multi-gate structure increases the withstand voltage, which is effective in improving the reliability of the circuit.

The driving voltage of the sampling circuit 1005 is 1
Although the voltage is 4 to 16 V, the polarity is alternately inverted, and the off-current value needs to be reduced.
The CMOS circuit including the n-channel TFT 287 in FIG. Although only an n-channel TFT is shown in FIG. 5B, in an actual sampling circuit, a p-channel TFT is also formed.
At this time, the structure shown in FIG. 185 is sufficient for the p-channel TFT.

The driving voltage of the pixel matrix circuit 1006 is 14 to 16 V, and it is required to further reduce the off-current value as compared with the sampling circuit from the viewpoint of low power consumption, and n shown in FIG. Channel type TFT28
It is desirable to have a structure having an LDD (Loff) region formed by providing an offset region with respect to the gate electrode as shown in FIG.

The structure of this embodiment can be easily realized by fabricating a TFT according to the steps shown in Embodiments 1 to 3. In the present embodiment, only the configurations of the pixel matrix circuit and the control circuit are shown. However, according to the steps of the first or second embodiment, the signal dividing circuit, the frequency dividing circuit, the D / A converter, the γ A correction circuit, an operational amplifier circuit, a signal processing circuit such as a memory circuit and an arithmetic processing circuit, or a logic circuit can be formed over the same substrate.

As described above, the present invention can realize a semiconductor device including a pixel matrix circuit and its control circuit on the same substrate, for example, a semiconductor device including a signal control circuit and a pixel matrix circuit.

[Embodiment 6] The present invention can be applied to an active matrix type EL display device. FIG.
1 is a circuit diagram of an active matrix EL display device. An X direction control circuit 12 and a Y direction control circuit 13 are provided around the pixel matrix circuit 11. Each pixel of the pixel matrix circuit 11 includes a switch TFT 14, a capacitor 15, a current control TFT 16, an organic EL element 1
7 and an X-direction signal line 18 is connected to the switching TFT 14.
a, a Y-direction signal line 20a is connected, and a current controlling TFT
Is connected to a power supply line 19a.

In the active matrix type EL display device of the present invention, the TFT used for the X-direction control circuit 12, the Y-direction control circuit 13 or the current control TFT 17 is shown in FIG.
(B) p-channel TFT 285, n-channel TF
It is formed by combining T286 or n-channel TFT 287. Also, the switching TFT 14 is replaced with the one shown in FIG.
It is formed by the n-channel TFT 288 of FIG.

The active matrix EL display device of this embodiment may be combined with any of the structures of the first to third embodiments.

[Embodiment 7] A CMOS circuit and a pixel matrix circuit formed by implementing the present invention are used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). be able to. That is, the present invention can be applied to all electronic devices in which these electro-optical devices are incorporated as display media.

Examples of such electronic equipment include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a personal computer, and a portable information terminal (mobile computer, mobile phone). Or an electronic book). One example of them is shown in FIG.

FIG. 17A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display device 2.
003 and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.

FIG. 17B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

FIG. 17C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 22.
05 and other signal control circuits.

FIG. 17D shows a goggle type display, which includes a main body 2301, a display device 2302, and an arm 23.
03. The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 17E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded.
03, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Digi) as a recording medium.
(tal Versatile Disc), CDs, etc., to enjoy music, movies, games and the Internet. The present invention can be applied to the display device 2402 and other signal control circuits.

FIG. 17F shows a digital camera, which comprises a main body 2501, a display device 2502, an eyepiece unit 2503, operation switches 2504, and an image receiving unit (not shown). The present invention can be applied to the display device 2502 and other signal control circuits.

[0095]

According to the present invention, since the glass substrate is shrunk in advance and an alignment marker is formed after that, the substrate is aligned using the alignment marker without considering the subsequent shrinkage of the substrate. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 6 is a top view of a substrate.

FIG. 7 is a top view and a cross-sectional view of an alignment marker.

FIG. 8 is a top view and a cross-sectional view of an alignment marker.

FIG. 9 is a top view and a cross-sectional view of an alignment marker.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 12 is a cross-sectional structural view of an active matrix liquid crystal display device.

FIG. 13 is a perspective view of an active matrix liquid crystal display device.

FIG. 14 is a top view of a pixel matrix circuit.

FIG. 15 is a circuit block diagram of an active matrix liquid crystal display device.

FIG. 16 illustrates a structure of an active matrix EL display device.

FIG. 17 illustrates an example of a semiconductor device.

[Explanation of symbols]

 Reference Signs List 201 glass substrate 202 base film 204 to 207 island-like semiconductor layer 208 gate insulating film 228 to 231 gate electrode 232 capacitance wiring 248 cap layer 251 protective insulating film 252 interlayer insulating film 253 to 259 source or drain electrode 260 passivation film 261 second Interlayer insulating film 262 Pixel electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) GG34 GG43 GG45 GG52 GG55 HJ01 HJ04 HJ13 HJ23 HL03 HL04 HM12 HM14 HM15 NN02 NN03 NN04 NN22 NN23 NN24 NN27 NN35 PP34 PP35 QQ11 QQ24 QQ25 QQ28

Claims (10)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: a step of forming an amorphous semiconductor film over a glass substrate; and a step of heat-treating the amorphous semiconductor film to form a crystalline semiconductor film. And a step of forming the crystalline semiconductor film and thereafter, wherein a temperature of the glass substrate is not higher than a substrate temperature of the heat treatment. 2. The heat treatment temperature according to claim 1, wherein
A method for manufacturing a semiconductor device, which is performed at 500 ° C. or higher. 3. The heat treatment temperature according to claim 1, wherein
550 ° C. or higher, a method for manufacturing a semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of the glass substrate is set to 550 ° C. or lower after the step of forming the crystalline semiconductor film. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of the glass substrate is set to 500 ° C. or lower after the step of forming the crystalline semiconductor film. 6. A step of forming an amorphous semiconductor film on a glass substrate, a step of heat treating the amorphous semiconductor film to form a crystalline semiconductor film, and a step of patterning the crystalline semiconductor film. Forming a semiconductor layer of a thin film transistor and an alignment marker, wherein after the step of forming the crystalline semiconductor film, the temperature of the glass substrate is set to a substrate temperature of the heat treatment. A method for manufacturing a semiconductor device, which is not higher than the above. 7. The heat treatment temperature according to claim 6, wherein the heat treatment temperature is 5 ° C.
A method for manufacturing a semiconductor device, which is performed at a temperature of 00 ° C. or higher. 8. The heat treatment temperature according to claim 6, wherein the heat treatment temperature is 5
A method for manufacturing a semiconductor device, which is at 50 ° C. or higher. 9. The method for manufacturing a semiconductor device according to claim 6, wherein the temperature of the glass substrate is set to 550 ° C. or lower after the step of forming the crystalline semiconductor film. 10. The method for manufacturing a semiconductor device according to claim 6, wherein the temperature of the glass substrate is set to 500 ° C. or lower after the step of forming the crystalline semiconductor film.