JP2001189459A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove or reduce impurity elements in the vicinity of the junction of a thin-film transistor. SOLUTION: The impurity element, such as a 3d transition metal, can be moved into a region far from the junction regions of a channel-forming region and a drain region by doping the element represented by P(phosphorus) in a region, in which source/drain are formed, and forming a gradient to the concentration distribution. That is, the impurity element in the vicinity of the junction regions can be gettered effectively, by lowering the concentration of the element represented by P in sections close to the junction regions and enhancing the concentration of the element represented by P in sections separated from the junction regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit including an active matrix type field effect thin film transistor (hereinafter, referred to as a TFT) on a substrate having an insulating surface, and a method for manufacturing the same. A semiconductor device in this specification refers to all devices that function by utilizing semiconductor characteristics. In particular, the present invention can be suitably used for an electro-optical device typified by a liquid crystal display device provided with an image display region and a driving circuit for displaying an image on the same substrate, and an electronic apparatus equipped with the electro-optical device. The semiconductor device includes the electro-optical device and an electronic device including the electro-optical device in its category.

[0002]

2. Description of the Related Art A TFT having a crystalline silicon semiconductor layer typified by polycrystalline silicon (polysilicon), microcrystalline silicon and single crystal silicon (hereinafter referred to as crystalline silicon T).
FT) has a higher field-effect mobility than a TFT having an amorphous silicon semiconductor layer (hereinafter, referred to as amorphous silicon TFT) and can operate at high speed. For this reason, it was inappropriate to use an amorphous silicon TFT for manufacturing a drive circuit for an image area requiring high-speed operation, but using a crystalline silicon TFT makes it possible to manufacture it on the same substrate as the image display area. became.

As a technique for obtaining a crystalline film, there is a technique described in Japanese Patent Application Laid-Open No. 10-303430. The technology disclosed in the publication discloses a method of performing crystal growth by introducing a metal that promotes crystallization, moving the metal that promotes crystallization to a region doped with an element represented by P, and performing gettering. It is. This technique lowers the crystallization temperature by the action of a metal that promotes crystallization, reduces the time required for crystallization, and reduces the electric power of the semiconductor device after crystallization is completed. The metal which promotes crystallization is removed from the crystalline film so as not to adversely affect the characteristics and reliability, or is reduced to such an extent that the metal is not adversely affected. By using this technique, a metal that promotes crystallization by low-temperature heat treatment can be gettered, and the characteristics of a low-temperature process can be utilized in manufacturing a semiconductor device.

As a further development of the above technology, there is a method of doping gettering by doping an element represented by P into the source / drain region of a transistor. In this method, the region for removing or reducing the metal that promotes crystallization by gettering may be only the region where the channel of the transistor is formed, so that the heat treatment time required for gettering can be reduced. By doping an element represented by P at the time of forming the source / drain, the process for gettering can be reduced. For a p-channel transistor, gettering is performed by doping the source / drain region with an element represented by P. At this time, the source / drain is formed by setting the concentration of an element typified by P doped in the active layer to be equal to or lower than the concentration of an impurity element imparting P-type. These are disclosed in JP-A-10-242.
475 and Japanese Patent Application Laid-Open No. 10-335672.

[0005]

When gettering a metal that promotes crystallization using an element represented by P, generally, the metal that promotes crystallization depends on the region to which the element represented by P is added. It is considered that a large amount of segregation occurs near the interface with the region where the metal that promotes crystallization is removed or reduced. Therefore, in the method of doping gettering by doping the element represented by P into the source / drain regions, the metal that promotes crystallization tends to segregate just near the junction region of the transistor. When a metal that promotes crystallization is present in the depletion layer region of a transistor, an unnecessary impurity level may be formed and the characteristics of the transistor may be adversely affected. It is preferable that the impurity element does not exist. It is an object of the present invention to remove or reduce an impurity element near a junction of a transistor.

[0006]

Means for Solving the Problems To solve the above problems, the present inventor of the present invention has proposed a method in which a source / drain doped with an element represented by P is formed in order to perform gettering. It was considered that a metal which promotes crystallization is moved by giving a gradient to a concentration distribution of a representative element. That is, for the concentration of the element represented by P in the region where the source / drain is formed and near the junction region, the concentration of P is represented by P in the source / drain region and away from the junction region. By increasing the concentration of the element, the metal that promotes crystallization in the vicinity of the source / drain can be moved to a region far from the junction region where a large amount of P exists.

However, for this purpose, when the concentration distribution of an element represented by P has a gradient in a region where a source / drain doped with an element represented by P is formed, a metal which promotes crystallization is used. We needed to make sure that would move or not. Fig. 2 shows the result of introducing 550 nm of metallic Ni into amorphous silicon film formed on a glass substrate.
C for 8 hours to crystallize, further ion-implant P with a gettering effect at an acceleration voltage of 10 kV, and heat-treat for gettering at 600 ° C for 12 hours. It is a SIMS analysis result showing a concentration. When P is ion-implanted, P takes a concentration distribution substantially described by a Gaussian function in the depth direction. Therefore, Ni in the polycrystalline silicon film in which the concentration gradient of P is formed in the depth direction.
Was able to find out the move. Also, the sample in the film of the sample that has not been subjected to the gettering process for reference
The Ni concentration distribution was almost uniform and was 3 × 10 ¹⁸ atoms / cm ³ .

FIG. 2 shows that Ni is abundant at a depth where the P concentration is high, and it can be seen from the comparison with the sample not subjected to the gettering process that Ni has moved to a depth where the P content is high. Ni moves a lot in the high-concentration region due to the heat treatment for gettering,
The Ni profile shape follows the P profile shape. That is, even in the region where the source / drain doped with P is formed,
It was found that Ni could be removed or reduced. Therefore P
It is possible to effectively remove or reduce the metal that promotes crystallization in the vicinity of the source / drain junction region using the concentration gradient of the element represented by This SIMS
The analysis examines the movement of Ni in the depth direction.If the element represented by P has a concentration gradient parallel to the semiconductor film, Ni moves in parallel to the semiconductor film. Can be concluded.

The configuration of the present invention will be described with reference to FIG. The substrate 103 is a glass substrate or a quartz substrate. Substrate 103
Above the channel forming region 107, the channel forming region 1
First impurity regions 101 and 111 are formed outside 07, and second impurity regions 102 and 112 are formed outside thereof. An impurity element of one conductivity type is introduced into the first impurity regions 101 and 111 at a first concentration, and an impurity element of the same type as the conductivity type is introduced into the second impurity regions 102 and 112 at a second concentration. It is assumed that the channel formation region has been crystallized using metal Ni for promoting crystallization. An insulating film 104 is formed on the channel forming region, and a gate electrode 105 is formed facing the channel forming region 107 via the insulating film 104. The first impurity regions 101 and 111
And the second impurity regions 102 and 112 together constitute the whole or a part of the source / drain regions. The insulating film 104 may be formed on the source / drain regions. When an LDD region or an offset region is formed, the first impurity regions 101 and 111 and the second impurity region are sandwiched between the channel forming region and the impurity region so that the LDD region or the offset region is interposed therebetween. 102 and 112 are formed.

The structure of the present invention is the same as that of the first impurity region 10 described above.
The second impurity concentration in the second impurity regions 102 and 112 is higher than the first concentration in the first impurity region 111. Specifically, the invention of the present application is characterized in that the first concentration is 1
× 10 ¹⁹ atoms / cm ^{3 to} 5 × 10 ²¹ atoms / cm ³ ,
Is from 1.2 to 1000 times the first concentration. The configuration of the present invention may be configured on both sides of the channel forming region as shown in FIG. 1, or may be configured on only one side. That is, for example, when it is desired to getter impurities near the junction of the drain region, the first impurity region and the second impurity region may be formed only on the drain side.

In another configuration of the present invention, an impurity element of one conductivity type is introduced at a first concentration into the first impurity regions 101 and 111, and the first impurity region is introduced into the second impurity region. And an impurity element imparting the same conductivity type as the impurity element introduced into the semiconductor element is introduced at the first concentration, and an impurity element having a conductivity type opposite to the one conductivity type is introduced at a second concentration. This configuration is characterized in that the first density is higher than the second density. The opposite conductivity type impurity element introduced into the second impurity region is introduced not for source / drain formation but for gettering. Specifically, the present invention is characterized in that the second concentration is 1 × 10 ¹⁹ atoms / cm ³ to 1 × 10 ²² atoms / cm ³ . As an example, in a P-type TFT, Ni can be effectively gettered from the vicinity of the junction region by introducing P having a large effect of gettering Ni into the second impurity region. As another example, in an N-type TFT, if B having a large effect of gettering Fe is introduced into the second impurity region, Fe can be effectively gettered from the vicinity of the junction region.

Another configuration of the present invention will be described with reference to FIG. The substrate 303 is a glass substrate or a quartz substrate. A channel formation region 307 is formed on the substrate 303, and third impurity regions 301 and 311 are formed outside the channel formation region 307. According to another configuration of the present invention, the third impurity region includes an impurity element of one conductivity type, and the concentration of the impurity element included in the third impurity region increases as the distance from the channel region increases. To a fourth concentration continuously. It is assumed that the channel forming region is crystallized by using metal Ni for promoting crystallization, and an insulating film 304 is formed on the channel forming region. Further, the channel forming region is formed through the insulating film 304. A gate electrode 305 is formed facing region 307. The insulating film 304 may be formed on the source / drain regions. Further, an LDD region or an offset region may be formed between the channel formation region and the third impurity region.

Another configuration of the present invention is, specifically,
3 is 1 × 10 ¹⁹ atoms / cm ^{3 to} 5 × 10 ²¹ atoms / cm ³ , and the fourth concentration is 1.2 to 1000 times the third concentration.
It is characterized by being twice. The configuration of the present invention may be configured on both sides of the channel forming region as shown in FIG. 3, or may be configured on only one side. That is, when it is desired to getter impurities near the junction of the drain region, for example,
Third impurity regions may be formed.

A strict description will be given of the concentration. Generally, when impurities are introduced by thermal diffusion or ion implantation of impurities, the impurity concentration in the active layer varies depending on the depth in the active layer, and has an uneven concentration distribution. The concentration here is a value obtained by averaging the concentration distribution in the depth direction in the active layer.

The above three structures describe a method of removing or reducing Ni near the junction by performing crystallization of the channel forming region using metal Ni that promotes crystallization. The method is also applied in the gettering of other metals that promote crystallization, and also does not use a metal that promotes crystallization, a normal polycrystalline film,
The present invention is also applied to gettering of an impurity element forming a deep level in a transistor using an amorphous film or a single crystal silicon film as an active layer. That is, 3d transition metals and the like (FE, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au) can be removed or reduced from the vicinity of the junction region of the transistor.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention can be applied to an element forming technique of a semiconductor thin film device.

The present invention can be implemented by introducing an impurity element imparting one conductivity type into the source / drain regions and forming a concentration distribution thereof. This concentration distribution may change continuously or may change discontinuously. Hereinafter, a method of forming this concentration distribution will be described.

First, a method is conceivable in which a doping step is performed a plurality of times using a resist mask, an oxide film mask, or the like, or a gate metal mask. Although this method requires more manufacturing steps, if the source / drain regions are doped with the impurity element imparting the one conductivity type after forming the contact holes, gettering near the junction can be performed without increasing the number of manufacturing steps.

As another method, there is a method in which an oxide film mask having a step or a gradient is formed on the source / drain, and the impurity element imparting one conductivity type is ion-implanted. This utilizes the difference in the concentration distribution of the implanted ions in the depth direction, and only one doping process is required. This method will be described later in an embodiment.

[Embodiment 1]

An embodiment of the present invention will be described with reference to FIGS. Here, the case where the TFTs of the pixel matrix circuit and the control circuit provided around the pixel matrix circuit are manufactured at the same time is taken as an example.
A method for removing metal Ni for promoting crystallization from the vicinity of the junction by using the present invention will be described in the order of steps. However, for the sake of simplicity, the control circuit shows a CMOS circuit as a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

In FIG. 4A, as the substrate 201, a low alkali glass substrate or a quartz substrate can be used. In this embodiment, a low alkali glass substrate is used. However, when glass is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Alternatively, a substrate obtained by forming an insulating film on a surface of a silicon substrate, a metal substrate, or a stainless steel substrate may be used as the substrate. If heat resistance permits, a plastic substrate can be used. On the surface of the substrate 201 where a TFT is to be formed, a base film 20 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed to prevent diffusion of impurities from the substrate 201.
2, a silicon oxynitride film made of, for example, SiH ₄ , NH ₃ , and N ₂ O,
Similarly, a silicon oxynitride film made of SiH ₄ and N ₂ O is formed to a thickness of 200 nm.

Next, a semiconductor film 203 having an amorphous structure
a is 20 to 150 nm, preferably 30 to 80 nm, by a known method such as a plasma CVD method or a sputtering method.
Formed to a thickness of In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. Further, the base film 202 and the amorphous silicon film 203a
Can be formed by the same film forming method, and therefore both may be formed continuously. This makes it possible to prevent the surface from being contaminated by not exposing it to an air atmosphere after the formation of the base film, and to reduce the variation in the characteristics of the TFT to be manufactured and the change in the threshold voltage. (Fig. 2 (A))

Then, using a known crystallization technique, the amorphous silicon film 203a is crystallized to form a crystallized silicon film 203b. As a crystallization technique, for example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied. Here, crystallization is promoted according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652. A crystalline silicon film 203b is formed by a crystallization method using metallic Ni to be formed. Prior to the crystallization step, depending on the amount of hydrogen contained in the amorphous silicon film, heat treatment may be performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen to 5 atom% or less before crystallization. desirable. When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the film becomes denser. Therefore, the thickness of the formed crystalline silicon film is determined by the thickness of the amorphous silicon film before crystallization (this embodiment). Is reduced by about 1 to 15%. (FIG. 2 (B))

Then, the crystalline silicon film 203b is divided into islands to form island-like semiconductor layers 204 to 207.
After that, the plasma CVD method or the sputtering method
Mask layer 2 of a silicon oxide film having a thickness of 100 nm
08 is formed. (Fig. 4 (C))

Thereafter, a resist mask 209 is provided, and island-shaped semiconductor layers 205 to 207 forming an n-channel TFT are formed.
1 × 10 ¹⁶ to control the threshold voltage
B, which is an impurity forming the p-type semiconductor layer, is added at a concentration of about 5 × 10 ¹⁷ atoms / cm ³ . B may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Although the addition of B here is not always necessary, the semiconductor layers 210 to 2 to which B has been added are added.
12 is preferably formed to keep the threshold voltage of the n-channel TFT within a predetermined range. (Figure 4
(D))

In order to form an LDD region of an n-channel TFT of a driving circuit, an impurity element forming an n-type semiconductor layer is selectively added to the island-like semiconductor layers 210 and 211. Therefore, resist masks 213 to 216 were formed in advance. P or As may be used as the n-type impurity element. Here, in order to add P, an ion doping method using phosphine (PH ₃ ) is applied. The P concentration of the formed impurity regions 217 to 219 is 2 × 10 ^{16 to} 5
It may be in the range of × 10 ¹⁹ atoms / cm ³ . In this specification, the concentration of the n-type impurity element contained in the impurity regions 217 to 218 formed here is expressed as (n ⁻ ). The impurity region 219 is a semiconductor layer for forming a holding point of the pixel matrix circuit, and P is added to this region at the same concentration. (Fig. 4 (E))

Next, a step of activating the impurity element added in FIG. 4E by removing the mask layer 208 with hydrofluoric acid or the like is performed. Activation is performed in a nitrogen atmosphere at 50
It can be performed by a heat treatment at 0 to 600 ° C. for 1 to 4 hours or a laser activation method. Further, both may be performed in combination. (Fig. 5 (A))

Then, the gate insulating film 220 is plasma C
The insulating film containing silicon is formed with a thickness of 10 to 150 nm by a VD method or a sputtering method. For example, 120
A silicon oxynitride film is formed with a thickness of nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (Fig. 5 (A))

Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, or may be formed as a two-layer or three-layer structure as necessary. In this embodiment, a conductive layer (A) 221 made of a conductive metal nitride film and a conductive layer (B) 222 made of a metal film are stacked. The conductive layer (B) 222 includes tantalum (Ta), titanium (Ti), molybdenum (Mo),
An element selected from tungsten (W), an alloy containing the above element as a main component, or an alloy film combining the above elements (typically, a Mo—W alloy film or a Mo—Ta alloy film) may be used. The conductive layer (A) 221 is made of tantalum nitride (T
aN), tungsten nitride (WN), titanium nitride (Ti
N) and molybdenum nitride (MoN). Alternatively, the conductive layer (A) 221 may be formed using tungsten silicide, titanium silicide, or molybdenum silicide as an alternative material. The conductive layer (B) preferably has a low impurity concentration in order to reduce the resistance, and particularly preferably has an oxygen concentration of 30 ppm or less. For example, tungsten (W) can realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.

The conductive layer (A) 221 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 222 has a thickness of 200 to 400 nm (preferably 250 to 350 nm).
It is good. In the film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to Ar of the gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a P-doped silicon film with a thickness of about 2 to 20 nm below the conductive layer (A) 221. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 120. Can be prevented. (Fig. 5 (B))

Next, resist masks 223 to 227 are formed, and the conductive layer (A) 221 and the conductive layer (B) 222 are collectively etched to form gate electrodes 228 to 231 and a capacitor wiring 232. In the gate electrodes 228 to 231 and the capacitor wiring 232, the conductive layer (A) and the conductive layer (B) are formed integrally. At this time, the gate electrodes 229 and 230 formed in the driver circuit overlap with part of the impurity regions 217 and 218 with the gate insulating film 220 interposed therebetween. (Fig. 5 (C))

Then, the gate insulating film 220 is etched using the gate electrode and the capacitor wiring as a mask so that at least the gate insulating films 233 to 236 remain under the gate electrode to expose a part of the island-shaped semiconductor layer. Let it.
(At this time, the insulating film 237 is also formed below the capacitor wiring.) This is because the impurity element is efficiently added in a step of adding an impurity element for forming a source region or a drain region in a later step. This step may be omitted, and the gate insulating film may be left on the entire surface of the island-shaped semiconductor layer. (Figure 5
(D))

Next, in order to form a source region and a drain region of the p-channel TFT of the control circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity regions are formed in a self-aligned manner using the gate electrode 228 as a mask. At this time, the region where the n-channel TFT is to be formed is covered with a resist mask 238. Then, an impurity region 239 is formed by an ion doping method using diborane (B ₂ H ₆ ). The B concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 239 formed here is expressed as (p +). (Fig. 6 (A))

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region is formed. Resist masks 240 to 242 are formed so as to cover the gate electrode and the region to be a p-channel TFT.
43 to 247 are formed. This is a phosphine (PH
The P concentration in this region is set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ by the ion doping method using ₃ ). In this specification, n included in the impurity regions 217 to 218 formed here.
The concentration of the impurity element giving the mold is represented by (n +). (Figure 6
(B))

The impurity regions 243 to 247 contain P or B already added in the previous step, but P is added in a sufficiently high concentration compared to that, so that It is not necessary to consider the effect of P or boron B. Further, since the P concentration added to the impurity region 243 is ２〜 to ３ of the B concentration added in FIG. 6A, p-type conductivity is ensured and there is no influence on the characteristics of the TFT. There is no. The P doping here is a metal that promotes crystallization, which is present in the source / drain formation and channel formation region.
Performed to getter Ni. In the impurity region 243,
Although the B concentration is higher, the inventors of the present application have clarified that it is possible to getter metal Ni that promotes crystallization of the channel formation region.

Next, the resist mask is removed, and an impurity doping process for imparting n-type is performed to form an LDD region of the n-channel TFT of the pixel matrix circuit. The concentration of P added here is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3.
The impurity regions 249 and 250 are formed by being added at a lower concentration than the concentration of the impurity element added in FIGS. 4E and 6A and 6B. In this specification,
The concentration of the impurity element imparting n-type contained in the impurity region formed here is represented by (n--). (Fig. 6 (C))

Then, a protective insulating film 251 to be a part of the first interlayer insulating film is formed. The protective insulating film 251 may be formed using a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. Also,
The thickness may be 100 to 400 nm.

Further, 500 to 1 is formed on the protective insulating film 251.
An interlayer insulating film 252 having a thickness of 500 nm is formed. A laminated film including the protective insulating film 251 and the interlayer insulating film 252 is referred to as a first interlayer insulating film. Thereafter, a contact hole reaching the source region or the drain region of each TFT is formed. (Figure 7)

Next, a first contact hole is formed.
P is added to the source region or the drain region from which the interlayer insulating film has been removed. Phosphate (PH ₃ )
Performed by ion doping method using
10 ²⁰ to 1 × 10 ²² atoms / cm ³ . P ion doping is performed in order to reduce or reduce the amount of metal Ni that promotes crystallization from near the junction. In order to perform gettering efficiently, it is better that the position of the contact hole is closer to the junction and that the area of the contact hole is larger. (Figure
7)

Thereafter, to activate the n-type or p-type impurity element added at each concentration,
The heat treatment step is performed at a temperature of 50C to 600C. A metal that promotes crystallization of the channel formation region by this heat treatment
Ni moves to the source or drain region, and further moves to a P-doped region having a higher P concentration through a contact hole. Also, Ni in the junction region moves to the P-doped region through the contact hole, and Ni in the vicinity of the junction region.
Can be reduced or reduced. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method).

Further, a heat treatment is performed in an atmosphere containing 3 to 100% of hydrogen at 300 to 450 ° C. for 1 to 12 hours to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the active layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

After the activation step, each TFT
The source wirings 253 to 256 and the drain wiring 2
57 to 259 are formed.

Next, as the passivation film 260,
A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is 50 to 500 nm (typically, 100 to 300 nm).
(nm). Hydrogenation treatment or plasma hydrogenation may be performed in this state. (Fig. 8 (A))

After that, a second interlayer insulating film 261 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Then, a contact hole reaching the drain wiring 259 is formed in the second interlayer insulating film 261, and a pixel electrode 262 is formed. For a pixel electrode 262, a transparent conductive film may be used for a transmissive liquid crystal display device.
In the case of a reflective liquid crystal display device, a metal film may be used. (Fig. 8 (B))

Thus, an active matrix substrate having a control circuit and a pixel matrix circuit on the same substrate can be completed. The control circuit includes a p-channel TFT 285, a first n-channel TFT 286, and a second n-channel TFT
FT287, n-channel TF for pixel matrix circuit
A pixel TFT made of T288 can be formed.

The p-channel TFT 285 of the control circuit has a channel forming region 263, a source region 264, and a drain region 265. First n-channel type TF
In T286, the channel formation region 266 and the Lov region 26
7, a source region 268 and a drain region 269. The second n-channel TFT 287 has a channel formation region 270, LDD regions 271 and 272, a source region 273, and a drain region 274. The n-channel TFT 288 of the pixel matrix circuit has channel formation regions 275 and 276 and Loff regions 277 to 280. The Loff region is formed offset with respect to the gate electrode, and the length of the offset region is 0.02 to 0.2 μm. Further, the capacitance wiring 2 formed simultaneously with the gate electrode
32, an insulating film made of the same material as the gate insulating film, and n
Semiconductor layer 28 doped with an impurity element imparting n-type, which is connected to drain region 283 of channel type TFT 288
4 form a storage capacitor 289. FIG. 8 (B)
In the above, the n-channel TFT 287 of the pixel matrix circuit has a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

In the following, only the method of forming an impurity element imparting one conductivity type in a non-uniform concentration distribution in a region where a source / drain is formed will be described in Examples 1 to 3. Further, the formation of the LDD and the like has been described in detail in Embodiment 1 and will not be described in the following examples.

[0049]

[Embodiment 1] In Embodiment 1, a method of performing a doping process a plurality of times using a resist mask, an oxide film mask, or the like, or a gate metal mask will be described.

In FIG. 9A, a substrate 903 is a glass substrate or a quartz substrate, and a base film 908 is made of an insulating film containing silicon (silicon). An island-shaped semiconductor layer is formed on the base film. This semiconductor layer is obtained by forming an amorphous silicon film using plasma CVD, as disclosed in Japanese Patent Laid-Open No. 7-13065.
According to the technique disclosed in Japanese Patent Publication No. 2 (KOKAI), crystallization is performed. Further, on the island-like semiconductor layer, by a known method,
Gate insulating films 901 and 904 and gate electrodes 902 and 905 are formed.

Next, a resist mask 922 is formed so as to cover a region to be an n-channel TFT, and impurity regions 909 and 910 are formed by adding an impurity element B imparting p-type. The B concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . (Fig. 9 (A))

Next, a resist mask 919 is formed so as to cover a region to be a p-channel TFT, and impurity regions 912 and 913 are formed by adding an impurity element P imparting n-type. The P concentration in this region is set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (FIG. 9
(B))

Next, a resist mask 920 and a resist mask 920 are formed in a part of the region where the gate electrode and the source / drain are to be formed.
921 is formed, and an impurity element P for imparting n-type is added to form impurity regions 915 to 918. The P concentration in this area is 4 × 10
²⁰ to 1 × 10 ²² atoms / cm ³ (Fig. 9 (C))

By performing a heat treatment for both thermal activation and gettering later, the impurity element Ni existing in the channel formation regions 911 and 914 can be moved to the source / drain regions, and furthermore, can be formed near the junction. Impurity element Ni
Can be moved to the impurity regions 915 to 918 most doped with P.

According to this method, the impurity regions 915 to 918 heavily doped with P can be brought close to the vicinity of the junction. Further, in this method, P doping using a contact hole may be further performed, and gettering in which the concentration difference is made in three stages may be performed.

[Embodiment 2] In Embodiment 2, a method of controlling the amount of impurities to be doped by partially leaving a gate oxide film in an island-shaped semiconductor layer will be described. This utilizes the concentration profile in the depth direction in the impurity implantation using ion doping, and a source / drain region having a non-uniform concentration distribution can be formed by a single doping process.

In FIG. 10A, a substrate 1003 is a glass substrate or a quartz substrate, and a base film 1008 is made of silicon (silicon).
Made of an insulating film containing An island-shaped semiconductor layer is formed on the base film. This semiconductor layer is obtained by forming an amorphous silicon film by using plasma CVD, as disclosed in
According to the technique disclosed in Japanese Patent Publication No. 52-52, crystallization is performed. Further, a gate insulating film 1004 is formed on the entire surface of the island-shaped semiconductor layer by a known method, and the gate electrodes 1002 and 1005 are etched thereon by a known method.
Are formed. Here, a resist mask 1023 is formed so as to cover the entire gate electrode of the n-channel TFT and leave a part of the island-shaped semiconductor layer, and the gate insulating film is etched. (Fig. 10 (A))

Next, a resist mask 1014 is formed so as to cover a region to be an n-channel TFT, and an impurity element B for imparting p-type is added to form impurity regions 1011 and 1012. The B concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . (Fig. 10 (B))

Next, a resist mask 1022 is formed so as to cover the entire gate electrode of the p-channel TFT and leave a part of the island-shaped semiconductor layer, and add an impurity element P for imparting n-type to the impurity region 1015. Form ~ 1020. The P concentration in this region is set to 1 × 10 ¹⁹ to 1 × 10 ²² atoms / cm ³ (FIG. 10C).

Therefore, the impurity regions 1015, 1016, 1019, 10
20 is heavily doped with P, and 1017 and 1018 are lightly doped. Therefore, after the heat treatment, the impurity element Ni in the channel formation regions 1013 and 1021 moves to the P-doped region, and Ni near the junction also moves to the heavily P-doped impurity regions 1015, 1016, 1019, and 1020. Therefore, Ni can be effectively removed or reduced from the vicinity of the junction. Here, the low concentration and the high concentration are expressed by comparing the concentrations of the two regions, and the region doped at a low concentration is approximately the same as the amount of impurities commonly doped into the source / drain. I do.

In this method, P doping using a contact hole may be further performed to perform gettering.

[Embodiment 3] In Embodiment 3, a method of controlling the amount of impurities to be doped by forming a slope in a gate insulating film by using wet etching and performing doping will be described. This method also utilizes the concentration profile in the depth direction in the impurity implantation using ion doping as in the second embodiment. In this example, the concentration distribution of P to be doped changes continuously.

In FIG. 11A, a substrate 1103 is a glass substrate or a quartz substrate, and a base film 1108 is made of silicon (silicon).
Made of an insulating film containing An island-shaped semiconductor layer is formed on the base film. This semiconductor layer is obtained by forming an amorphous silicon film by using plasma CVD, as disclosed in
According to the technique disclosed in Japanese Patent Publication No. 52-52, crystallization is performed. Further, a gate insulating film 1104 is formed on the entire surface of the island-shaped semiconductor layer by a known method, and the gate electrodes 1102 and 1105 are etched thereon by a known method.
Are formed. Here, the resist masks 1111, 1112 are formed so as to cover the entire gate electrodes of the n-channel TFT and the p-channel TFT and leave all or part of the island-shaped semiconductor layer.
Is formed, and the gate insulating film is wet-etched.
(Fig. 11 (A))

Next, a resist mask 1115 is formed so as to cover a region to be an n-channel TFT, and an impurity element B for imparting p-type is added. The B concentration in this area is 3 × 10 ^{20 to} 3 ×
It should be 10 ²¹ atoms / cm ³ . (Fig. 11 (B))

Next, a resist mask 1124 is formed so as to cover the entire gate electrode of the p-channel TFT and leave a part of the island-shaped semiconductor layer. ~ 1119 are formed. P in this area is
In consideration of the thickness due to the inclination of the gate insulating film, ion implantation may be performed so that the doping amount increases as the distance from the gate increases. (Fig. 11 (C))

Therefore, the impurity regions 1116 to 1119 have a higher P concentration as the distance from the gate electrode increases. Therefore, after the heat treatment, the impurity elements in the channel formation regions 1122 and 1123 are
Ni moves to the P-doped region, and more Ni near the junction also moves to a portion farther from the gate in the heavily P-doped impurity region. Therefore, Ni can be effectively removed or reduced from the vicinity of the junction. Here, the low concentration and the high concentration are expressed by comparing the concentrations of the two regions, and the region doped at a low concentration is approximately the same as the amount of impurities commonly doped into the source / drain. I do.

[Embodiment 4] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 12, an alignment film 601 is formed on the active matrix substrate in the state of FIG. 8B which can be manufactured in Embodiment Mode 1. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. The light-shielding film 603, the transparent conductive film 604, and the alignment film 605 were formed on the opposite substrate 602 on the opposite side. After forming the alignment film, a rubbing treatment is performed so that the liquid crystal molecules are aligned with a certain pretilt angle. And
The pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are attached to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. Thereafter, a liquid crystal material 606 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material.
Thus, an active matrix liquid crystal display device is completed.

Next, the structure of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 13 and the top view of FIG. 13 and FIG. 14 are denoted by the same reference numerals in order to correspond to the sectional structural views of FIG. 4 to FIG. 8 and FIG. The cross-sectional structure along 1 'shown in FIG. 14 corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG.

The active matrix substrate includes a pixel matrix circuit 701 formed on the glass substrate 201,
It is composed of a scanning signal control circuit 702 and an image signal control circuit 703. N-channel type TF for pixel matrix circuit
T288 is provided, and a driver circuit provided in the periphery is configured based on a CMOS circuit. Each of the scanning signal control circuit 702 and the image signal control circuit 703 includes a gate wiring 231 (connected to a gate electrode and denoted by the same reference sign in the sense that it is formed to extend) and a source wiring 25.
6 is connected to the n-channel TFT 288 of the pixel matrix circuit. The FPC 731 is connected to the external input / output terminal 7
34.

FIG. 14 is a top view showing a part (almost one pixel) of the pixel matrix circuit 701. Gate wiring 23
Reference numeral 1 intersects an active layer therebelow via a gate insulating film (not shown). Although not shown, the active layer includes a source region, a drain region, and an L-
A region is formed. 290 is the source wiring 25
6, a contact portion between the drain line 259 and the drain region 283; a contact portion 292 between the drain line 259 and the pixel electrode 262; The storage capacitor 289 is an n-channel type T
Semiconductor layer 284 extending from drain region of FT288
Is formed in a region where the capacitor wiring 232 overlaps with the gate insulating film.

The active matrix type liquid crystal display device of this embodiment can be manufactured by freely combining any of the following embodiments.

Embodiment 5 The present invention can be applied to an active matrix type EL display device. FIG. 15 is a circuit diagram of an active matrix EL display device. An X-direction control circuit 12 is provided around the pixel matrix circuit 11,
A Y-direction control circuit 13 is provided. Each pixel of the pixel matrix circuit 11 includes a switching TFT 14, a capacitor 15, a current controlling TFT 16, and an organic EL element 17,
The X-direction signal line 18a and the Y-direction signal line 20a are connected to the switching TFT 14, and the power supply line 1 is connected to the current controlling TFT.
9a is connected.

In the active matrix type EL display device of the present invention, the TFT used for the X direction control circuit 12, the Y direction control circuit 13 or the current control TFT 17 is shown in FIG.
(B) p-channel TFT 285, n-channel TF
It is formed by combining T286 or n-channel TFT 287. Also, the switching TFT 14 is replaced with the one shown in FIG.
It is formed by the n-channel TFT 288 of FIG.

The active matrix type E of the present embodiment
First Embodiment, First Embodiment to First Embodiment for an L display device
Any of the three configurations may be combined.

[Embodiment 6] An active matrix substrate in which a pixel matrix circuit and a control circuit manufactured by carrying out the present invention are integrally formed on the same substrate has various electro-optical devices (active matrix type liquid crystal display devices, Active matrix type EL display device, active matrix type EC display device). That is, the present invention can be applied to all electronic devices incorporating these electro-optical devices as display units.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation system, a personal computer, a mobile phone, and an electronic book. Can be FIG. 16 shows an example of them.

FIG. 16A shows a portable telephone, and a main body 900.
1, an audio output unit 9002, an audio input unit 9003, a display unit 9004, an operation switch 9005, and an antenna 9006. The present invention can be applied to the display portion 9004 including an active matrix substrate.

FIG. 16B shows a video camera,
101, display unit 9102, audio input unit 9103, operation switch 9104, battery 9105, image receiving unit 9106
Consists of The present invention can be applied to the display portion 9102 provided with an active matrix substrate.

FIG. 16C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display unit 9205. The present invention can be applied to the display portion 9205 provided with an active matrix substrate.

FIG. 16D shows a goggle type display having a main body 9301, a display portion 9302, and an arm portion 9303.
It consists of. The present invention can be applied to the display portion 9302. Although not shown, it can be used for other signal control circuits.

FIG. 16E shows a rear type projector, which includes a main body 9401, a light source 9402, a display device 9403,
Polarizing beam splitter 9404, reflector 940
5, 9406 and a screen 9407. The invention can be applied to the display device 9403.

FIG. 16F shows a portable book, which has a main body 950.
1. It comprises display units 9502 and 9503, a storage medium 9504, operation switches 9505, and an antenna 9506, and displays data stored on a mini disk (MD) or a DVD or data received by the antenna. In the present invention, the display portions 9502 and 9503 can be applied to a direct-view display device.

Although not shown here, the present invention can also be applied to a car navigation system or a display unit of an image sensor personal computer. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to fifth embodiments.

By using the present invention, impurities near the boundary between the channel formation region and the source and drain regions of the transistor can be removed or reduced, and the operating performance and reliability of the semiconductor device (specifically, the electro-optical device here) can be reduced. Performance can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a means for solving a problem.

FIG. 2 is a diagram showing a SIMS analysis result.

FIG. 3 is a diagram schematically showing a means for solving the problem.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.

FIG. 9 is a diagram showing a TFT creation process according to the first embodiment.

FIG. 10 is a diagram illustrating a TFT creation process according to the second embodiment.

FIG. 11 is a diagram illustrating a TFT creation process according to the third embodiment.

FIG. 12 is a cross-sectional structure diagram of an active matrix liquid crystal display device.

FIG. 13 is a perspective view of an active matrix liquid crystal display device.

FIG. 14 is a top view of a pixel matrix circuit.

FIG. 15 is a circuit diagram of an active matrix EL display device.

FIG. 16 illustrates an example of a semiconductor device.

[Explanation of symbols]

210 ~ 212,284,301,311 Semiconductor layer 204 ~ 207,210,211 Island semiconductor layer 209,213 ~ 216,223 ~ 227,238,240 ~ 242,919 ~ 922 Resist mask 1014,1022,1023,1111,1112,1115,1124 Resist mask 105,305,228 ~ 231,902,905,1002,1005,1102,1105 gate Electrode 104,304,220,233-236,901,904,1004,1104 Gate insulating film 107,263,266,270,275,276,911,914,1013,1021,1122,112
3 channel formation region 264,268,273 source region 265,269,274,283 drain region 101,111 first impurity region 102,112 second impurity region 301,311 third impurity region 203a amorphous silicon film 203b crystallized silicon film 208 mask layer 221 conductive layer (A) 222 conductive Layer (B) 232 Capacitance wiring 237 Insulating film 251 Protective insulating film 252 Interlayer insulating film 260 Passivation film 261 Second interlayer insulating film 262 Pixel electrode 267 Lov region 277-280 Loff region 603 Light shielding film 604 Transparent conductive film 606 Liquid crystal material 290,292 Contact part 232 Capacity wiring

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/78 617A 627G F term (Reference) 2H092 GA59 JA25 JA29 JA33 JA35 JA38 JA39 JA42 JA43 JA44 JA46 JA47 JB13 JB23 JB27 JB32 JB33 JB36 JB38 JB43 JB51 JB57 JB63 JB69 KA04 KA07 KA12 MA05 MA07 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA28 MA32 MA35 MA37 MA41 NA22 NA25 PA06 PA13 RA05 5F052 AA02 AA17 CA00 DA02 DB03 DB07 FA24 HA03 HA06 JA01 5F110 DD03 DD03 DD02 DD DD15 EE01 EE04 EE05 EE06 EE14 EE44 FF02 FF03 FF04 FF12 FF28 FF30 GG02 GG04 GG13 GG25 GG32 GG34 GG43 GG45 HJ01 HJ07 HJ13 HJ23 HM15 NN03 NN04 NN22 NN23 Q25 Q25 Q25 Q03 PP03

Claims (16)

[Claims] A first impurity region formed outside the channel forming region; a first impurity region formed outside the channel forming region;
A second impurity region formed outside of the first impurity region, the first impurity region includes an impurity element of one conductivity type at the first concentration, and the second impurity region includes the second impurity region. A semiconductor device comprising an impurity element having the same conductivity type as the second concentration, wherein the second concentration is higher than the first concentration. 2. A semiconductor device comprising: a channel forming region; a first impurity region formed outside the channel forming region; and a second impurity region formed outside the first impurity region. The first impurity region includes an impurity element of one conductivity type at the first concentration, the second impurity region includes the impurity element of one conductivity type at the first concentration, and A semiconductor device comprising an impurity element having a conductivity type opposite to that of a mold at the second concentration, wherein the first concentration is higher than the second concentration. 3. The semiconductor device according to claim 1, wherein an LDD region is formed between said channel forming region and said first impurity region. 4. The semiconductor device according to claim 1, wherein an offset region is formed between the channel formation region and the first impurity region. 5. A semiconductor device comprising: a channel formation region; and a third impurity region formed outside the channel formation region, wherein the third impurity region includes an impurity element of one conductivity type and a concentration of the impurity element. The semiconductor device according to claim 1, wherein the concentration increases continuously from a third concentration to a fourth concentration as the distance from the channel formation region increases. 6. The semiconductor device according to claim 3, wherein an LDD region is formed between said channel forming region and said third impurity region. 7. The semiconductor device according to claim 3, wherein an offset region is formed between said channel forming region and said third impurity region. 8. The method according to claim 1, wherein the first concentration is 1 × 10 ¹⁹ atoms / cm ^{3 to} 5 ×
5. The method according to claim 1, wherein the second concentration is 10 ²¹ atoms / cm ³ , and the second concentration is 1.2 to 1000 times the first concentration. 6. Semiconductor device. 9. The method according to claim 1, wherein the second concentration is 1 × 10 ¹⁹ atoms / cm ³ to 1 × 1
5. The semiconductor device according to claim 2, wherein the concentration is 0 ²² atoms / cm ³ . 10. The method according to claim 1, wherein the third concentration is 1 × 10 ¹⁹ atoms / cm ^{3 to} 5 ×
10 ²¹ atoms / cm ³ , in the third impurity region,
The fourth concentration of the impurity element is 1.
8. The semiconductor device according to claim 5, wherein the ratio is 2 to 1000 times. 11. The semiconductor device according to claim 11, wherein said channel forming region is formed using a metal which promotes crystallization.
8. The semiconductor device according to any one of 1 to 7. 12. The semiconductor device according to claim 10, wherein said channel forming region is formed using Ni as a metal for promoting crystallization. 13. The semiconductor device according to claim 1, wherein P is introduced as said impurity element. 14. A semiconductor device comprising: a first step of forming a first impurity region outside a channel forming region; and a second step of forming a second impurity region outside the first impurity region. Then, an impurity element of one conductivity type is introduced into the first impurity region at a first concentration, and an impurity element of the same type as the one conductivity type is introduced into the second impurity region at a second concentration. A method for manufacturing a semiconductor device, wherein the second concentration is introduced higher than the first concentration. 15. A semiconductor device comprising: a first step of forming a first impurity region outside a channel forming region; and a second step of forming a second impurity region outside the first impurity region. In the first impurity region, an element of one conductivity type is added to the first impurity region.
To the second impurity region, the one conductivity type element is introduced at the first concentration, and the conductivity type impurity element opposite to the one conductivity type is introduced into the second impurity region. The method for manufacturing a semiconductor device, wherein the first concentration is introduced at a higher concentration than the second concentration. 16. A first step of forming a third impurity region outside a channel forming region, wherein an impurity element of one conductivity type is introduced into the third impurity region. The impurity element included in the region continuously increases from a third concentration to a fourth concentration in a direction away from the channel formation region, and the fourth concentration is higher than the third concentration. A method for manufacturing a semiconductor device, which is introduced.