JP2000223575A - 半導体装置の設計方法、半導体装置および半導体装置の製造方法 - Google Patents
半導体装置の設計方法、半導体装置および半導体装置の製造方法Info
- Publication number
- JP2000223575A JP2000223575A JP11020277A JP2027799A JP2000223575A JP 2000223575 A JP2000223575 A JP 2000223575A JP 11020277 A JP11020277 A JP 11020277A JP 2027799 A JP2027799 A JP 2027799A JP 2000223575 A JP2000223575 A JP 2000223575A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- wiring
- semiconductor device
- layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11020277A JP2000223575A (ja) | 1999-01-28 | 1999-01-28 | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11020277A JP2000223575A (ja) | 1999-01-28 | 1999-01-28 | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000223575A true JP2000223575A (ja) | 2000-08-11 |
| JP2000223575A5 JP2000223575A5 (https=) | 2006-01-26 |
Family
ID=12022687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11020277A Pending JP2000223575A (ja) | 1999-01-28 | 1999-01-28 | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000223575A (https=) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100667597B1 (ko) | 2005-02-07 | 2007-01-11 | 삼성전자주식회사 | 매크로 셀의 전원 라인 배치 구조 및 매크로 셀과 파워매시의 결합 구조 |
| JP2007165670A (ja) * | 2005-12-15 | 2007-06-28 | Matsushita Electric Ind Co Ltd | 半導体回路装置およびその設計方法 |
| US8063415B2 (en) | 2007-07-25 | 2011-11-22 | Renesas Electronics Corporation | Semiconductor device |
| CN112567507A (zh) * | 2018-08-28 | 2021-03-26 | 株式会社索思未来 | 半导体集成电路装置 |
| JPWO2021111604A1 (https=) * | 2019-12-05 | 2021-06-10 | ||
| CN114492283A (zh) * | 2020-11-11 | 2022-05-13 | Oppo广东移动通信有限公司 | 配置芯片的方法及装置、设备、存储介质 |
| CN114898790A (zh) * | 2016-01-29 | 2022-08-12 | 三星电子株式会社 | 用于选择性地执行隔离功能的半导体器件及其布局替代方法 |
| WO2024116853A1 (ja) * | 2022-11-29 | 2024-06-06 | 株式会社ソシオネクスト | 半導体集積回路装置 |
-
1999
- 1999-01-28 JP JP11020277A patent/JP2000223575A/ja active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100667597B1 (ko) | 2005-02-07 | 2007-01-11 | 삼성전자주식회사 | 매크로 셀의 전원 라인 배치 구조 및 매크로 셀과 파워매시의 결합 구조 |
| JP2007165670A (ja) * | 2005-12-15 | 2007-06-28 | Matsushita Electric Ind Co Ltd | 半導体回路装置およびその設計方法 |
| US8063415B2 (en) | 2007-07-25 | 2011-11-22 | Renesas Electronics Corporation | Semiconductor device |
| US8264011B2 (en) | 2007-07-25 | 2012-09-11 | Renesas Electronics Corporation | Semiconductor device |
| CN114898790A (zh) * | 2016-01-29 | 2022-08-12 | 三星电子株式会社 | 用于选择性地执行隔离功能的半导体器件及其布局替代方法 |
| CN112567507A (zh) * | 2018-08-28 | 2021-03-26 | 株式会社索思未来 | 半导体集成电路装置 |
| CN112567507B (zh) * | 2018-08-28 | 2024-07-05 | 株式会社索思未来 | 半导体集成电路装置 |
| JPWO2021111604A1 (https=) * | 2019-12-05 | 2021-06-10 | ||
| JP7363921B2 (ja) | 2019-12-05 | 2023-10-18 | 株式会社ソシオネクスト | 半導体装置 |
| CN114492283A (zh) * | 2020-11-11 | 2022-05-13 | Oppo广东移动通信有限公司 | 配置芯片的方法及装置、设备、存储介质 |
| WO2024116853A1 (ja) * | 2022-11-29 | 2024-06-06 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6489641B1 (en) | Sea-of-cells array of transistors | |
| JPH10335612A (ja) | 高密度ゲートアレイセル構造およびその製造方法 | |
| US7207025B2 (en) | Sea-of-cells array of transistors | |
| WO2022224847A1 (ja) | 出力回路 | |
| JP3074003B2 (ja) | 半導体集積回路装置 | |
| JPH09283632A (ja) | 半導体集積回路装置 | |
| JP3917683B2 (ja) | 半導体集積回路装置 | |
| EP0249988A2 (en) | A master-slice integrated circuit having an improved arrangement of transistor elements for simplified wirings | |
| JPH0434309B2 (https=) | ||
| US12376384B2 (en) | Semiconductor integrated circuit device | |
| JP2000223575A (ja) | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 | |
| JP3181000B2 (ja) | 半導体集積回路装置 | |
| JPH10173055A (ja) | セルベース半導体装置及びスタンダードセル | |
| US7154133B1 (en) | Semiconductor device and method of manufacture | |
| WO2000005764A1 (en) | Master-slice system semiconductor integrated circuit and design method thereof | |
| JP2002083933A (ja) | 半導体装置 | |
| EP0344055B1 (en) | Semiconductor integrated circuit device | |
| JPH10229164A (ja) | 半導体集積回路装置 | |
| JPWO2000065650A1 (ja) | 半導体装置およびその製造方法 | |
| EP1009031B1 (en) | Semiconductor integrated circuit device and method of producing the same | |
| JP2002009176A (ja) | Sramセル及びそれを内蔵した半導体集積回路 | |
| JP2001156178A (ja) | 半導体装置および半導体装置の自動レイアウト方法 | |
| JPH0563944B2 (https=) | ||
| JP3140750B2 (ja) | 半導体集積回路装置 | |
| JPH04306863A (ja) | 半導体集積回路装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20051205 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20051205 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090324 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090326 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20090714 |