JP2000216402A - Thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a manufacture method in which a thin film transistor(TFT) having an crystal silicon active layer with a reliability and a superior performance is manufactured and the TFT is manufactured at an inexpensive cost. SOLUTION: A thin film transistor has two lightly doped regions 215 and 216 at least and a source/drain which is adjacent to a channel forming region 202 and the source/drain regions 213 and 214 contain catalyst elements which crystallize amorphous silicon. Activation for the source/drain regions can be made at a low temperature and in a short time by operation of the catalyst elements. Also a concentration of the catalyst elements at the boundary of the channel forming region and the lightly doped regions is made less than one of the source/drain regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a thin film transistor (TFT) used for a liquid crystal display device and the like, and a method for manufacturing the same. Further, the present invention relates to a method for manufacturing a thin film transistor having a step of activating a source / drain region by thermal annealing. The thin film transistor according to the present invention is formed on an insulating surface. In the present invention, the term “on an insulating surface” includes not only on an insulating substrate such as glass, but also on an insulating film provided on a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Recently, studies have been made on an insulating gate type semiconductor device having a thin-film semiconductor layer (also referred to as an active layer or an active region) provided on an insulating surface. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. The TFT is used for controlling a pixel of a display device such as a liquid crystal having a matrix structure formed on an insulating substrate, a driving circuit of a matrix circuit, or a three-dimensional integrated circuit in which a semiconductor integrated circuit is formed in multiple layers. It is used for TFTs are classified into amorphous silicon TFTs and crystalline silicon TFTs according to the material and crystalline state of the semiconductor used.

In general, the electric field mobility of a semiconductor in an amorphous state is small, and therefore, a TFT requiring high-speed operation is required.
Not available to Also, in amorphous silicon,
Since the P-type electric field mobility is extremely small, a P-channel TFT (PMOS TFT) cannot be manufactured.
Therefore, N-channel type TFT (NMOS TFT)
Complementary MOS circuit (CMOS circuit)
Cannot be formed.

On the other hand, a crystalline semiconductor has a higher electric field mobility than an amorphous semiconductor and can operate at high speed. Furthermore, crystalline silicon is not limited to NMOS TFTs,
Since a PMOS TFT can also be manufactured, a CMO
An S circuit can be manufactured. For example, in an active matrix type liquid crystal display device, not only an active matrix circuit but also a peripheral circuit (a driver and the like) for driving the active matrix circuit can be formed on the same substrate by a CMOS circuit of a crystalline TFT on a single substrate. Obtainable.

Recently, for the purpose of reducing deterioration due to hot carriers, it is also required to provide a low-concentration impurity region having an N-type or P-type impurity concentration lower than the source / drain regions adjacent to the source / drain regions. ing. In order to form source / drain regions and low-concentration impurity regions, an ion implantation method or an ion doping method is employed. Usually, impurity ions imparting N-type or P-type conductivity are accelerated to form a silicon film. Have been injected.

[0006]

However, since the impurity ions are accelerated and implanted into the silicon film, the silicon film becomes amorphous due to the ion bombardment at that time. In such an amorphous state, the sheet resistance of the source / drain region becomes very large.

A TFT whose semiconductor active layer is in an amorphous state
In the first place, since the field effect mobility is small, the source /
Sheet resistance of drain region is 10 kΩ / □ to 1 MΩ / □
If it is on the order, it can be put to practical use. However, since the field effect mobility is high in the crystalline TFT, if the sheet resistance is not less than 10 kΩ / □, sufficient characteristics as the crystalline TFT cannot be utilized. Therefore, it is necessary to enhance (activate) the crystallinity of the amorphous source / drain regions. In the activation step, since many parts of the TFT element including the gate electrode are formed, it is required that they are not damaged.

For activation, a method by thermal annealing can be used. The thermal annealing method has an advantage that there is little variation between batches. The temperature and time required for activation depend on the concentration of the implanted impurities. Therefore, the low-concentration impurity region can be activated by thermal annealing at a relatively low temperature and for a short time, whereas a region having a high impurity concentration such as the source / drain region is activated at a high temperature. Requires long-time thermal annealing.

Usually, to activate a region into which an impurity having a concentration of 1 × 10 ²⁰ atoms / cm ³ or more (1 × 10 ¹⁴ atoms / cm ³ or more in terms of a dose) is implanted, it is necessary to activate the region at about 600 ° C. Prolonged thermal anneal at a temperature of 1000 or 1000
It is necessary to perform thermal annealing for a short time at a high temperature of not less than ℃. 1
If a thermal annealing method at 000 ° C. or higher is used, the substrate that can be used is limited to quartz, and the cost of the substrate becomes extremely high. On the other hand, in the thermal annealing method at a temperature of about 600 ° C., there is more room for selection of usable substrates, but a long time is required, which causes a decrease in productivity. In addition, high-temperature or long-time thermal annealing may greatly affect the gate electrode, the substrate, and the like. Therefore, thermal effects on other parts of the element (for example, pattern displacement due to contraction or deformation of the substrate)
In order to minimize this, activation by thermal annealing at a lower temperature and for a shorter time is required.

An object of the present invention is to solve the above problems and to provide a crystalline thin film transistor having excellent characteristics. Another object of the present invention is to solve the above-mentioned problems and to perform a low-temperature, short-time thermal annealing process.
It is an object of the present invention to provide a method for manufacturing a thin film transistor which can activate a source / drain region.

[0011]

As a result of the research by the present inventors,
It has been found that the crystallization can be promoted by adding a small amount of a catalyst material to the silicon film in a substantially amorphous state, the crystallization temperature can be reduced, and the crystallization time can be shortened.

The present inventor has paid attention to the effect of the catalytic element, and has found that the use of the catalytic element can improve the crystallinity of the amorphous source / drain regions. In the present invention, thermal annealing is performed after the above-described catalyst element is implanted into the source / drain region by a method such as an ion implantation method. Alternatively, a film of a catalyst element alone or a compound thereof is deposited on the source / drain region and thermally annealed to diffuse the catalyst element into the source / drain region and improve crystallinity.

As a method of adding a catalytic element to an amorphous silicon film, specifically, a method of forming a film, a particle, a cluster, or the like having a catalytic element substantially in contact with or below the amorphous silicon film. Can be adopted. Alternatively, a method of introducing these catalytic elements into the amorphous silicon film by a method such as an ion implantation method can be adopted. As the catalytic element, a simple substance of nickel (Ni), iron (Fe), cobalt (Co), platinum (Pt), palladium (Pd), or a compound thereof is suitable.

Thereafter, the amorphous silicon film is thermally annealed at an appropriate temperature (typically, 580 ° C. or lower), so that the amorphous silicon film can be crystallized by the action of a catalytic element. As a matter of course, the higher the annealing temperature, the shorter the time required for crystallization. Further, the higher the concentration of the catalytic element such as nickel, iron, cobalt, and platinum, the lower the temperature required for crystallization and the shorter the time required for crystallization. According to the study of the present inventors, in order to promote crystallization of amorphous silicon, it is necessary that the concentration of at least one of the above catalyst elements exceeds 1 × 10 ¹⁷ atoms / cm ³ in the amorphous silicon film. It became clear that it was. However, since all of the above-mentioned catalyst elements are unfavorable materials for silicon, it is desirable that their concentrations be as low as possible. In the present inventors' research, it is desired that the total concentration of these catalyst materials does not exceed 10 ²⁰ atoms / cm ³ .

In order to manufacture a crystalline thin film transistor according to the present invention, the following steps may be provided. Forming a low-concentration impurity region (in a crystalline silicon film having a catalytic element concentration of less than 1 × 10 ¹⁷ atoms / cm ³ ); Step of forming source / drain regions (by ion implantation or ion doping). A step of depositing a substance having a catalytic element on a region substantially the same as the source / drain region. A step of activating the source / drain regions by thermal annealing (400 to 580 ° C.);

Alternatively, a step of forming a low-concentration impurity region (in a crystalline silicon film having a catalytic element concentration of less than 1 × 10 ¹⁷ atoms / cm ³ ). Step of forming source / drain regions (by ion implantation or ion doping). A step of introducing a catalytic element into a region substantially the same as the source / drain region (by ion implantation or ion doping). A step of activating the source / drain regions by thermal annealing (400 to 580 ° C.);

In these steps, the order of the steps can be changed. For example, the source / drain regions may be formed first, and then the low-concentration impurity regions may be formed. Alternatively, the source / drain regions may be formed after introducing a catalytic element first. In the present invention, in the above step, the catalyst element or the substance containing the catalyst element is intentionally introduced into a portion of the active layer other than the source / drain region, for example, into a channel formation region or a low-concentration impurity region. It is characterized in that it is not formed or formed.

The structure of the TFT obtained through the above steps is as shown in FIG. FIG. 1A shows an example of a coplanar type, and FIG. 1B shows an example of an inverted stagger type. FIG.
(A) will be described. A crystalline silicon active layer is provided on the insulating surface 101, and the silicon active layer includes a channel formation region 104, a source region 105, and a drain region 1.
08, low-concentration impurity regions 106 and 107 between source / drain regions 105 and 108 and channel formation region 104
And is constituted by. A gate insulating film 102 and a gate electrode 103 are formed on the active layer. An interlayer insulator 109 is provided to cover the gate electrode 103.
The electrodes 110 and 111 of the source / drain regions 105 and 108 are formed in the contact holes of the interlayer insulator 109.

In the present invention, the catalytic element is mainly introduced into the source / drain regions 105 and 108 to improve the crystallinity of the portions. Source / drain region 10
The concentration of the catalyst element at 5 and 108 was 1 × 10 ¹⁷ atoms /
It is characterized by exceeding cm ³ . Some of the catalytic elements thermally diffuse to the low-concentration impurity regions 106 and 107,
The concentration is sufficiently low.
At the boundaries 112 and 113, 1 × 10 ¹⁷ atoms / cm ³
The concentration is less than. Naturally, the concentration of the catalyst element in the channel formation region 104 is less than 1 × 10 ¹⁷ atoms / cm ³ . Here, the concentration of the catalyst element in the source / drain regions 105 and 108 is a value when the silicon film is measured by secondary ion mass spectroscopy (SIMS), and the catalyst element is distributed in the film thickness direction. Is the minimum value. The concentration of the catalyst element in the channel formation region 104 and the boundaries 112 and 113 is an average value in the thickness direction of the silicon film.

FIG. 1B will be described. Insulating surface 1
A gate electrode 122 and a gate insulating film 123 are provided thereon, and a crystalline silicon active layer is provided thereon. In the silicon active layer, a channel forming region 124, a source region 125, a drain region 128,
Then, the low-concentration impurity regions 126 and 12 between the source / drain regions 125 and 128 and the channel formation region 124.
7 are formed. And source / drain region 1
Electrodes 129 and 130 are formed on 25 and 128, respectively. An interlayer insulator may be provided on the active layer.

Also in this case, the catalyst element is mainly a source /
Introduced into the drain regions 125 and 128,
Improve crystallinity. Source / drain regions 125, 128
Is 1 × 10¹⁷Atom / cm^ThreeOver
It is characterized by Some of the catalytic elements are low concentration impurities
Thermal diffusion also occurs in the regions 126 and 127, but the concentration is
Sufficiently low, especially at the boundary 131 with the channel formation region,
In 132, 1 × 10 ¹⁷Atom / cm^ThreeConcentration less than
It is characterized by the following.

[0022]

In the present invention, the catalyst element mainly introduced into the source and drain regions by the above-mentioned steps significantly promotes crystallization while diffusing into the regions. for that reason,
Upon activation, 400-580 ° C, typically 450
A sufficient effect can be obtained by heating at a temperature of ５550 ° C. Also, an annealing time of 8 hours or less, typically 4 hours or less is sufficient. In particular, when a catalytic element is introduced by an ion implantation method or an ion doping method as in a later step, crystallization proceeds very easily since the catalytic element is uniformly distributed from the beginning.

In the low-concentration impurity region, the concentration of the catalytic element is remarkably low. Therefore, the improvement in the crystallinity by the catalytic element except for the portion adjacent to the source / drain regions is performed.
Although it is hardly expected, the concentration of the introduced impurity is sufficiently low, so that the impurity is activated even at the low temperature as described above. An excellent point of the present invention is that, although a catalytic element harmful to silicon is added to the TFT, the concentration is extremely low at the boundary between the channel formation region and the channel formation region and the low concentration impurity region as described above (1 × 10 4 ¹⁷ atoms / c
m ³ ). In particular, it is preferable for the TFT characteristics that the concentration of the catalyst element at the boundary between the channel formation region and the low concentration impurity region is sufficiently low.

At the boundary, in the case of N-channel type, N^-
I-junction, P for P-channel type ^-I junction is formed
And the current is originally N^-To I or I to P^-Who
Current flows only in the opposite direction, and the current flowing in the opposite direction is sufficiently small. I
However, there are many catalytic elements etc. near such a joint
The energy level generated by the element
As a result, a reverse leakage current is generated. This means that TFT
Is in a non-selected state (that is, when the N-channel type
When a negative voltage is applied to the
In the opposite case), the leakage current (off-current)
It means big.

[0025] As in the present invention, N ^- I junction, or,
When the concentration of the catalyst element near the P ^- I junction is sufficiently low, the leakage current in the reverse direction (that is, off current) can be sufficiently reduced. This is extremely effective when the TFT of the present invention is used for a switching transistor or the like of an active matrix circuit.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in FIGS. [Embodiment 1] This embodiment relates to the fabrication of a coplanar N-channel TFT used as a switching transistor in an active matrix circuit of a liquid crystal display device. In the switching transistor of the active matrix circuit, the source / drain region is inverted at any time depending on the use environment. For convenience, however, in the following description, the source / drain region is connected to the data line of the matrix in the source / drain region. The one connected to the pixel electrode is called a source, and the one connected to the pixel electrode is called a drain.

FIG. 2 is a sectional view showing a manufacturing process of this embodiment. An intrinsic (I-type) amorphous silicon film having a thickness of 300 to 2000 Å, for example, 1000 Å is deposited on a substrate (quartz) 201 by a plasma CVD method. The concentration of nickel, platinum, cobalt, iron, and palladium in the amorphous silicon film is set to 1 × 10 ¹⁷ atoms / cm ³ . Next, the amorphous silicon film was crystallized by thermal annealing in a nitrogen atmosphere at 600 ° C. for 48 hours. After the thermal annealing, the crystallized silicon film is etched to form island-shaped silicon regions.

Then, a thickness of 1
A silicon oxide film 205 of 2000 Å is deposited as a gate insulating film. For sputtering, silicon oxide was used as a target, and the substrate temperature during sputtering was 200 to 400.
° C, for example, 350 ° C, the sputtering atmosphere is a mixed atmosphere of oxygen and argon, and the argon / oxygen ratio is 0 to 0.
5, for example, 0.1 or less. Subsequently, reduced pressure CVD
Depending on the method, the thickness is 3000-8000Å, for example, 600
A 0 ° silicon film (containing 0.1-2% phosphorus) was deposited. Then, the gate electrode 206 is formed by etching the silicon film. Note that it is preferable that the step of forming the silicon oxide film 205 and the silicon film be performed continuously.

Next, a low-concentration N-type impurity (phosphorus) is implanted into the island-shaped silicon region by ion doping using the gate electrode 206 as a mask. The ion doping method is a method of doping an impurity by generating plasma in a reduced-pressure atmosphere containing an impurity element to generate ions, accelerating the ions at a high voltage, and irradiating an object to be irradiated.

In this embodiment, phosphine (PH ₃ ) diluted with hydrogen (for example, 1% PH ₃ -99% H ₂ ) is used as the doping gas. Acceleration voltage of 6
0 to 90 kV, for example, 80 kV, and the dose amount is 1 × 1
0 ¹² to 8 × 10 ¹³ atoms / cm ² , for example, 5 × 10 ¹² atoms / cm ² . As a result, N-type low-concentration impurity regions 203 and 204 were formed. Also, the gate electrode 206
No impurity was introduced into a portion immediately below the channel forming region 202, and the channel forming region 202 remained. After that, the thickness is 4000 to 12000
The silicon oxide film 207 is formed by the plasma CVD method.
In this embodiment, the thickness of the silicon oxide film 207 is set to 6000 ° which is the same as that of the gate electrode. (Fig. 2 (A))

Next, the silicon oxide films 207 and 205 are etched by an anisotropic dry etching method.
Side wall (side wall) 20 on the side surface of gate electrode 206
8 is formed. The width of the side wall 208 is determined by the height of the gate electrode 206 and the thickness of the silicon oxide film 207. In the present embodiment, it was approximately 6000 °. Then, nickel ions are implanted by ion implantation at a rate of 1 × 10 ¹² to 1 × 10 ^14.
Introduced at a dose of atoms / cm ² . The accelerating voltage is 10
20 kV was appropriate. At this time, even in the same low-concentration impurity regions 203 and 204, the region 21 under the side wall 208 is formed.
Nickel is not implanted in 1, 212, but is mainly implanted in the exposed portions 209, 210 (these are the portions where the source / drain regions will be formed later). (FIG. 2 (B))

Thereafter, a high concentration N-type impurity (phosphorus) is implanted by ion doping using the gate electrode 206 and the side wall 208 as a mask. In this embodiment, doping gas is hydrogen-diluted phosphine (for example, 5% PH ₃ -9).
Using 5% H ₂ ), the acceleration voltage is set to 10 to 30 kV, for example, 20 kV, and the dose is set to 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² , for example, 2 × 10 ¹⁴ atoms / cm ² .
As a result, an N-type impurity is implanted at a high concentration in a region not covered by the gate electrode 206 and the side wall 208, so that a source region 213 and a drain region 214 are formed. In addition, since impurity ions are not implanted into the region immediately below the gate electrode 206 and the side wall 208, the region remains as the channel formation region 202 and the low-concentration impurity regions 215 and 216. The regions where the source / drain regions 213 and 214 were formed were almost the same as the regions 209 and 210 into which nickel had been implanted in the previous step. The regions where the low-concentration impurity regions 215 and 216 are formed are regions 211 and 21 where nickel was not implanted in the previous step.
It is almost the same as 2. Then, by thermal annealing at 400 to 580 ° C., the source / drain regions 213,
214, the impurities in the low concentration impurity regions 215 and 216 are activated. In this embodiment, the thermal annealing condition is 550.
C. for 2 hours. (Fig. 2 (C))

Thereafter, a silicon nitride film 217 having a thickness of 4000 to 8000 ° is deposited by a plasma CVD method. A contact hole with the source region 213 is formed in the silicon nitride film 217. Then, an aluminum film having a thickness of 6000 mm is deposited on the contact holes by a sputtering method,
This is etched to form a source electrode 218.
(FIG. 2 (D))

Further, a silicon oxide film 219 having a thickness of 2000 to 4000 ° is deposited by a plasma CVD method.
The silicon oxide film 219 and the silicon nitride film 217 are each etched to form a contact hole with the drain region 214. Then, a thickness of 5
A transparent conductive film (for example, indium tin oxide film) having a thickness of 00 to 1000 ° is deposited in the contact hole and etched to form the pixel electrode 220. Through the above steps, a thin film transistor of an active matrix circuit is manufactured. (FIG. 2 (E))

The source / drain of the obtained thin film transistor
In regions 213 and 214 and channel formation region 202
Ion mass spectrometry (SIMS) method
Was measured by Source / drain regions 213, 21
4 × 1 × 10¹⁸~ 5 × 10 ¹⁸Atom / cm^ThreeDegree, cha
The measurement limit (1 × 10¹⁶Atom / c
m^Three) In particular, the source / drain regions 21
In Nos. 3 and 214, the nickel concentration was
Was observed, and the lowest value was 1 × 10 ¹⁸atom/
cm^ThreeMet.

[Embodiment 2] This embodiment also relates to the fabrication of a coplanar N-channel TFT used for a switching transistor of an active matrix circuit of a liquid crystal display device. Same as 1. FIG. 3 shows a cross-sectional view of the manufacturing process of this embodiment.

First, the substrate (Corning 7059) 301
A 2000-nm-thick silicon oxide base film 302 is formed thereon by sputtering. Furthermore, plasma CVD
Depending on the method, a thickness of 300 to 1000 mm, for example, 500 mm
An intrinsic (I-type) amorphous silicon film is deposited.
Then, this amorphous silicon film is placed in a nitrogen atmosphere,
Thermal annealing is performed at 400 ° C. for 1 hour to release hydrogen contained in the film.

Then, it was crystallized by irradiating a laser beam. As a laser, a KrF excimer laser (wavelength 248 nm), an ArF excimer laser (wavelength 193n)
m), XeCl excimer laser (wavelength 308 nm),
Excimer laser such as XeF excimer laser (wavelength 353 nm), or Nd: YAG laser (wavelength 1064 nm) or its second harmonic (wavelength 532 nm)
Alternatively, a pulsed laser such as a third harmonic (wavelength: 355 nm) or a continuous wave laser such as an Ar ion laser is preferable. In this embodiment, a KrF excimer laser is used. Energy density is 320-450mJ
/ Cm ² is appropriate, but since the optimum energy density varies depending on the formed silicon film, conditions are determined in advance to determine the optimum energy density.

After that, the crystallized silicon film is etched to form an island-shaped silicon region 303. Further, monosilane (SiH ₄ ) and dinitrogen monoxide (N ₂ O)
Is used as a raw material, and a thickness of 10
A silicon oxide film 304 of 00 ° is deposited as a gate insulating film. In this embodiment, monosilane is introduced into the reaction chamber at 10 SCCM and nitrous oxide is introduced at 100 SCCM, the substrate temperature is 430 ° C., the reaction pressure is 0.3 Torr, and the input power (13.
(56 MHz) 250 W. These conditions vary depending on the reactor used. The film formation rate of the silicon oxide film 304 manufactured under the above conditions was about 1000 ° / min, and the etching rate in a mixed solution of hydrofluoric acid 1, acetic acid 50, and ammonium fluoride 50 (20 ° C.) was about 1000 ° / min. Was.

Subsequently, by a sputtering method,
An aluminum film having a thickness of 2000 to 8000, for example, 4000, is deposited. Then, a photoresist is applied, and a photoresist mask 306 is formed by a known photolithography method. In order to improve the adhesiveness of the photoresist, an extremely thin (50-200 °) anodic oxide film (not shown) is previously formed on the surface of the aluminum film. The gate electrode 305 is formed by etching the aluminum film using a photoresist mask 306. In addition, in order to suppress the occurrence of abnormal crystal growth (hillock) in the heating or subsequent anodic oxidation step, 0.1 to 0.5% by weight of scandium (Sc) or yttrium (Y) is mixed with aluminum. ing. (FIG. 3 (A))

Next, while leaving the photoresist mask 306 used as an etching mask thereon, the gate electrode 305 is anodized by passing a current in an electrolytic solution to a thickness of 1 μm.
An anodic oxide 307 having a thickness of 5 μm, for example, 2 μm is formed. A constant current of 10 to 30 V is applied to the electrolytic solution using a 3 to 20% acidic aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like. In this embodiment, p
H = 0.9-1.0 in oxalic acid solution (30 ° C.)
A current of V was applied to the gate electrode 305 to perform anodic oxidation. The thickness of the anodic oxide 307 is controlled by the anodic oxidation time. The anodic oxide 307 thus obtained was porous. In this anodic oxidation step, a thin anodic oxide film existing between the gate electrode 305 and the photoresist mask 306 can prevent a current from leaking from the photoresist mask 306, and Only the anodic oxide 307 can be formed. (FIG. 3 (B))

Next, the photoresist mask 306 is peeled off, and a current is applied to the gate electrode 305 again in the electrolytic solution. Thus, anodic oxide 308 is formed on the upper surface and side surfaces of gate electrode 305. The anodic oxide 308 is dense and hard, and is effective in protecting the gate electrode 305 in a subsequent heating step. As the electrolytic solution, an ethylene glycol ammonia solution having a pH of 6.9 to 7.1 containing at least one of tartaric acid, boric acid, and nitric acid of 3 to 10% is used. If the temperature of the solution is lower than room temperature of about 10 ° C., a favorable oxide film can be obtained. Anodic oxide 3
08 is almost proportional to the applied voltage, and the applied voltage is 150
An anodic oxide 308 of 2000 ° at V is formed.

Thereafter, the silicon oxide film 304 is etched by a dry etching method. Porous anodic oxide 3
07 is not etched, so that the silicon oxide film 3
04 remains as a gate insulating film 309 without being etched. (FIG. 3 (C))

Thereafter, the anodic oxide 307 is etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxide 307 was etched, and the etching rate was about 600 ° / min. The gate insulating film 309 of silicon oxide remains as it is.

Next, impurities (phosphorus) are implanted into the island-shaped silicon region 303 by using the gate electrode 305 and the gate insulating film 309 as a mask by a plasma doping method. Two-stage doping is performed using phosphine (PH ₃ ) as a doping gas. The first doping is
The acceleration voltage is 80 kV and the dose is 5 × 10 ¹² atoms /
cm ² . In this doping, the acceleration is large, so that phosphorus ions pass through the gate insulating film 309 and are also implanted into the island-shaped silicon region 303 therebelow. However, since the dose at this time is small, the low-concentration impurity region 311 31
2 are formed.

In the second doping, the acceleration voltage is made smaller and the dose is made larger than in the first doping. Here, the acceleration voltage is 30 kV, and the dose is 5 × 10 ¹⁴
Atoms / cm ² . In this doping, phosphorus ions cannot pass through the gate insulating film 309 due to a small acceleration, and are mainly implanted into the exposed portions of the island-shaped silicon regions 303 to form the source region 310 and the drain region 313. Impurities are implanted into the source / drain regions 310 and 313 in both dopings, and the second dose is larger than that in the first doping, so that the source / drain regions 310 and 313 are high-concentration impurity regions. On the other hand, the impurities are not implanted immediately below the gate insulating film 309 in the second doping, so that they remain as the low-concentration impurity regions 311 and 312. , A channel forming region.

Thereafter, by spin coating,
An extremely thin coating 314 of nickel acetate is formed. Here, a 10 ppm aqueous solution of nickel acetate is used, spin-coated and spin-dried to form an extremely thin nickel acetate coating 314 over the entire surface of the substrate. Prior to the spin coating, a thin silicon oxide film is formed on the surfaces of the source / drain regions 310 and 313 by treating with a hydrogen peroxide solution (or a mixed solution thereof and ammonia) or the like. Prevent flipping. (FIG. 3 (D))

Thereafter, thermal annealing is performed at 450 ° C. for 4 hours in a nitrogen atmosphere to form source / drain regions 310 and 31.
3, and the impurities in the low concentration impurity regions 311 and 312 are activated. At this time, the source / drain regions 31
At 0 and 313, a nickel acetate coating 314 is substantially adhered (strictly, a thin silicon oxide film is present therebetween, but does not hinder the diffusion of nickel at the time of thermal annealing). However, nickel acetate is easily decomposed at a temperature of 400 ° C. or more to become metallic nickel, and the source region 3
10. Diffusion into the drain region 313. Because of the catalytic action of this nickel, the source / drain regions 310, 313
Recrystallization proceeds easily. Further, the low-concentration impurity regions 311 and 312 are simultaneously activated by this thermal annealing.

Subsequently, as an interlayer insulating material, a thickness of 4000
Of silicon oxide film 315 of TEOS
It is deposited by the VD method. The silicon oxide film 315 has a source /
Contact holes with the drain regions 310 and 313 are formed respectively, and a source electrode / wiring 316 is formed by a multilayer film of titanium and aluminum. Drain region 3
No electrode is formed in the contact hole 13 at this stage. Subsequently, a thickness of 2
A silicon nitride film 315 is deposited to a thickness of 2,000 mm, and again inside the contact hole with the drain region 313 formed previously.
A contact hole is formed and a pixel electrode 31 of a transparent conductive film is formed.
8 is formed and connected to the drain region 313. Through the above steps, a thin film transistor of an active matrix circuit is manufactured. (FIG. 3 (E))

[Embodiment 3] FIG. 4 shows a process of manufacturing an N-channel TFT shown in this embodiment. First, a 2000-nm-thick silicon oxide base film 402 is formed on a substrate (Corning 7059) 401 by a sputtering method. Next, by plasma CVD, an intrinsic (I type) having a thickness of 500 mm is formed.
Is deposited. This amorphous silicon film is thermally annealed in a nitrogen atmosphere at 400 ° C. for 1 hour to release hydrogen contained in the film. Next, the amorphous silicon film was irradiated with laser light to be crystallized. As a laser, a KrF excimer laser (wavelength: 248 nm) is used. The irradiation energy density is 350 mJ / cm ² . After that, the crystallized silicon film is etched to form the island-shaped silicon region 403.
To form

Further, a silicon oxide film 404 having a thickness of 1000 ° serving as a gate insulating film is deposited by a plasma CVD method. Subsequently, by sputtering, 400
A 0 ° thick aluminum film is deposited. On the surface of the aluminum film, an anodic oxide film (not shown) is formed to a very thin thickness of 50 to 200 ° in order to improve the adhesion of the photoresist. Then, a photoresist mask 406
Is formed, and an aluminum film is etched to form a gate electrode 405. In order to suppress the occurrence of abnormal growth of crystals (hillocks) in the heating and subsequent anodic oxidation steps, aluminum is added to aluminum. 1 to 0.5% by weight of scandium (Sc) or yttrium (Y) is mixed. (FIG. 4 (A))

With the photoresist mask 406 used as an etching mask left on the gate electrode 405, a current is passed through the gate electrode 405 in an electrolytic solution, and the gate electrode 405 is anodized to a thickness of 1 to 5 μm, for example. Then, an anodic oxide 407 having a thickness of 2 μm is formed. A constant current of 10 to 30 V is applied to the electrolytic solution using a 3 to 20% acidic aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like. In this embodiment, the oxalic acid solution (30
C)) to a voltage of 10V. In addition, anodic oxide 407
Is controlled by the anodizing time. The anodic oxide 407 thus obtained was porous.
In this anodic oxidation step, current leakage from the photoresist mask 406 can be suppressed by a thin anodic oxide film present between the gate electrode 405 and the photoresist mask 406, and the side surface of the gate electrode 405 Anodization can be selectively advanced. (FIG. 4 (B))

Next, the photoresist mask 406 was peeled off, and a current was applied to the gate electrode 405 again in the electrolytic solution. Therefore, an anodic oxide 408 was formed on the upper surface and side surfaces of the gate electrode. 3 ~
An ethylene glycol ammonia solution containing at least one of 10% tartaric acid, boric acid and nitric acid and having a pH of 6.9 to 7.1 is used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. The thickness of the anodic oxide 408 is almost proportional to the applied voltage.
An anodic oxide 408 of 00 ° is formed. The anodic oxide 408 is dense and hard, and is effective in protecting the gate electrode 405 in a subsequent heating step.

Then, the silicon oxide film 404 is etched by a dry etching method. As a result, a part of the island-shaped silicon region 403 was exposed. Also, in this etching, the porous anodic oxide 407 is not etched, so the underlying silicon oxide film 409 is not etched,
The gate insulating film 409 remains. Then, after forming an extremely thin oxide film (not shown),
An extremely thin coating 410 of nickel acetate is formed. At this time, nickel comes into contact with the exposed surface of the island-shaped silicon region 403, and the island-shaped silicon region 403 below the gate insulating film 409 does not come into contact with nickel.
(FIG. 4 (C))

In this state, a heat treatment at 350 ° C.
A nickel silicide layer is formed on the exposed surface of the island-shaped silicon region 403. Next, the porous anodic oxide 407 is removed by etching. Thus, the state shown in FIG. 4D is obtained.

Next, an impurity (phosphorus) is implanted into the island-shaped silicon region 403 using the gate electrode 405 and the gate insulating film 409 as a mask by a plasma doping method. Phosphine (PH ₃ ) is used as a doping gas to perform two-step doping. The first doping is performed at an acceleration voltage of 80 kV and a dose of 5 × 10 ¹² atoms / cm 2.
^{Assume 2} . In this doping, the acceleration is large, so that the phosphorus ions pass through the gate insulating film 409 and are also implanted into the island-like silicon region 403 thereunder. However, since the dose at this time is small, the low-concentration impurity regions 412, 413 are respectively formed.

Subsequently, a second doping is performed. In the second doping, the acceleration voltage is made smaller and the dose is made larger than in the first doping. here,
The acceleration voltage is 30 kV and the dose is 5 × 10 ¹⁴ atoms /
cm ² . In this doping, since the acceleration is small, phosphorus ions cannot pass through the gate insulating film 409 and are mainly implanted into the exposed portions of the island-shaped silicon region 403, so that the source region 411 and the drain region 414 are formed. Impurities are implanted into the source / drain regions 411 and 414 in both of the two dopings, and the second dose is larger than that in the first stage doping, so that the regions are high-concentration impurity regions. On the other hand, immediately below the gate insulating film 409, 2
Since no impurity is implanted in the second doping, the impurity remains as low-concentration impurity regions 412 and 413. In particular, immediately below the gate electrode 405, no impurity is implanted in both of the two dopings, so that a channel forming region is formed.

After that, thermal annealing is performed at 450 ° C. for 4 hours in a nitrogen atmosphere to thereby form the source / drain regions 4.
11 and 414, the impurities in the low concentration impurity regions 412 and 413 are activated. Source / drain regions 411, 4
14 has a nickel acetate film 415 substantially adhered thereto (strictly, a thin silicon oxide film exists between them,
This does not hinder the diffusion of nickel during thermal annealing), but nickel acetate is easily decomposed at a temperature of 400 ° C. or higher to become metallic nickel, and the source region 411,
Diffusion into the drain region 414. Due to the catalytic action of nickel, the source / drain regions 411 and 414 are easily recrystallized. Further, the low-concentration impurity regions 412 and 413 are simultaneously activated by the thermal annealing.

Then, as an interlayer insulator, a thickness of 4000
Of silicon oxide film 416 of plasma C
The source / drain regions 4 are deposited by the VD method.
Contact holes 11 and 414 are formed. Then, a source electrode / wiring 417 is formed by a multilayer film of titanium and aluminum. At this stage, no electrode is formed in the contact hole of the drain region 414.

Subsequently, the thickness 2 was formed by the plasma CVD method.
A silicon nitride film 418 is deposited to a thickness of 2,000 °, a contact hole is further formed inside the contact hole of the drain region 414 formed earlier, and a pixel electrode 419 of a transparent conductive film is formed.
Is formed and connected to the drain region 414. Through the above steps, a thin film transistor is manufactured. (FIG. 4
(E))

[0061]

According to the present invention, since the source / drain regions can be favorably activated by the catalytic element, a crystalline thin film transistor having excellent characteristics can be obtained.

Further, in the present invention, since the catalyst element is added to the source / drain region at a predetermined concentration, the source / drain region is doped at a low temperature such as 450 ° C. for 4 hours and in a short time. It is possible to activate the impurity imparting the conductivity type. For this reason, the throughput can be improved. In addition, 6
When a process at a temperature of 00 ° C. or higher is employed, shrinkage of the glass substrate has been a problem as a cause of a decrease in yield. However, such a problem can be solved at a stretch by using the present invention. When applied to the manufacturing process of a thin film transistor of a liquid crystal display device, improvement in mass productivity and improvement in characteristics are achieved.

The fact that the treatment can be performed at a low temperature in a short time is as follows.
This means that a large area substrate can be processed at a time. Therefore, by forming a large number of thin film transistors over a large substrate, a large number of semiconductor circuits (such as a matrix circuit) can be cut out from one substrate, so that the cost of circuits and devices can be significantly reduced. Can be. As described above, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows a conceptual diagram of a TFT of the present invention.

FIG. 2 shows a cross-sectional view of a manufacturing process in Example 1.

FIG. 3 shows a cross-sectional view of a manufacturing process in Example 2.

FIG. 4 shows a cross-sectional view of a manufacturing process in Example 3.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 ... Substrate 102 ... Gate insulating film 103 ... Gate electrode 104 ... Channel formation region 105 ... Source 106, 107 ... Low-concentration impurity region 108 ... Drain 109 ... Interlayer Insulator 110 ・ ・ ・ Source electrode 111 ・ ・ ・ Drain electrode 112,113 ・ ・ ・ Boundary between low concentration impurity region and channel formation region 121 ・ ・ ・ Substrate 122 ・ ・ ・ Gate electrode 123 ・ ・ ・ Gate insulating film 124 ・..Channel forming region 125 ... Source 126, 127 ... Low concentration impurity region 128 ... Drain 129 ... Source electrode 130 ... Drain electrode 131,132 ... Low concentration impurity region and channel formation Area boundaries

Claims (6)

[Claims] 1. A thin film transistor having a crystalline silicon film formed on an insulating surface and a gate electrode formed above the channel formation region via a gate insulating film, wherein the crystalline silicon film has a channel A formation region, a source region, a drain region, a low-concentration impurity region between the channel formation region and the source region, and a low-concentration impurity region between the channel formation region and the drain region; The source region and the drain region include a catalyst element that promotes crystallization of the amorphous silicon film at a concentration exceeding 1 × 10 ¹⁷ atoms / cm ³ ,
The concentration of the catalyst element in the channel forming region is 1 × 1
A thin film transistor, which is less than 0 ¹⁷ atoms / cm ³ , wherein the source region and the drain region contain phosphorus. 2. A thin film transistor having a crystalline silicon film formed on an insulating surface and a gate electrode formed below the channel formation region via a gate insulating film, wherein the crystalline silicon film has a channel A formation region, a source region, a drain region, a low-concentration impurity region between the channel formation region and the source region, and a low-concentration impurity region between the channel formation region and the drain region; The source region and the drain region include a catalyst element that promotes crystallization of the amorphous silicon film at a concentration exceeding 1 × 10 ¹⁷ atoms / cm ³ ,
The concentration of the catalyst element in the channel forming region is 1 × 1
A thin film transistor, which is less than 0 ¹⁷ atoms / cm ³ , wherein the source region and the drain region contain phosphorus. 3. The thin film transistor according to claim 1, wherein the catalyst element contains nickel, iron, cobalt, palladium or platinum. 4. The method according to claim 1, wherein
A thin film transistor, wherein the source region and the drain region have a sheet resistance of 10 kΩ / □ or less. 5. The method according to claim 1, wherein
The thin film transistor according to claim 1, wherein the concentration of the catalyst element is determined by a minimum value of a secondary ion mass spectrometry. 6. The method according to claim 1, wherein
The thin film transistor is used for a display device.