JP2000214483A - Electro-optic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device which is capable of increasing the aperture ratio of the electro-optic device having plural pixel parts. SOLUTION: Drain regions D of TFTs 30 for driving liquid crystals are connected via contact holes 11 to metal electrodes 15. These metal electrodes 15 are connected via contact holes 8 to pixel electrodes 9. At this time, the metal electrodes 15 are extended and formed to the peripheral side of the pixel parts with respect to the positions where the contact holes 11 are formed. The contact holes 8 are formed in the portions of the extended metal electrodes 15. Since the contact holes 8 which affect the alignment characteristic of liquid crystals are formed in the positions distant from the centers of the pixels, the disclination at which the alignment indicates continuous regions can be formed on the more outside and the aperture ratio as the pixel parts is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of electro-optical devices, and more particularly, to the structure of each pixel portion included in an electro-optical device for displaying an image or the like using a liquid crystal element as an electro-optical element. Belongs to the technical field.

[0002]

2. Description of the Related Art Conventionally, as an electro-optical device formed by arranging pixel portions including electro-optical elements in a matrix,
For example, an active matrix type liquid crystal display device including a liquid crystal layer driven by applying a voltage by a pixel electrode formed for each pixel portion is generally widely known.

This liquid crystal display device includes a switching element for driving a liquid crystal element for each pixel portion by applying a drive voltage to the pixel electrode for each of a plurality of pixel portions included in the liquid crystal display device. In addition, as the switching element, a so-called thin film transistor (hereinafter simply referred to as TFT (Thin Film Transistor)
r). ) Is often used.

Here, a typical configuration of the thin film transistor includes, for example, a drain region and a source region in the thin film semiconductor layer by implanting donor ions or acceptor ions into a thin film semiconductor layer such as a polysilicon layer. And a channel region. The drain region is connected to the pixel electrode via a drain electrode, while the source region is connected to a data line to which a data signal is supplied via a source electrode. Some are formed so that a scanning signal is applied from a gate electrode (scanning line) formed immediately above via a gate insulating film.

Then, a channel for passing electrons or holes is formed in the channel region by the scanning signal,
The data signal supplied to the source region by the channel is transmitted to the drain region, and the data signal is applied to the pixel electrode via the drain electrode to drive the liquid crystal element.

Here, since the drain region, the drain electrode and the pixel electrode are thinned with an interlayer insulating film interposed therebetween, the drain region and the drain electrode and the drain electrode and the pixel electrode are electrically connected to each other. In order to make it conductive, a so-called interlayer contact is required to connect between the respective regions or layers on which the electrodes are formed.

In this case, in the conventional liquid crystal display device, after the drain region and the drain electrode are connected by the first interlayer contact, the drain electrode is extended toward the center of the pixel portion, and the drain electrode is located at the extended position. In general, a second interlayer contact for connecting a drain electrode and a pixel electrode is formed.

[0008] This is because, when a second interlayer contact is formed directly above the first interlayer contact, an etchant for the wet etching is formed at the time of wet etching when the interlayer contact is formed by photolithography. Is permeated to the drain region and the drain region may be eroded.

[0009]

However, according to the conventional arrangement of the interlayer contacts, the first interlayer contact is formed in the pixel portion at a position close to the area related to the actual display. There is a problem that the alignment of the liquid crystal may be adversely affected.

That is, the first interlayer contact is:
Since this is for applying a data signal to the pixel electrode, it is inevitably at the same potential as the pixel electrode when driving the liquid crystal. In this case, however, as a result, the liquid crystal near the first interlayer contact is laterally moved. A voltage is applied from the direction, which disturbs the orientation of the liquid crystal in the vicinity.

[0011] This means that a so-called disclination line indicating a discontinuous plane of the liquid crystal alignment is formed in the center of the pixel portion, and as a result, the aperture ratio of the pixel portion decreases. That leads to the problem.

Further, a decrease in the aperture ratio of the pixel portion leads to a decrease in luminance of the liquid crystal display device. In such a case, it is necessary to increase the aperture ratio as much as possible.

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an electro-optical device capable of increasing an aperture ratio in an electro-optical device having a plurality of pixel portions. To provide.

[0014]

In order to solve the above-mentioned problems, the present invention provides a plurality of scanning lines, a plurality of data lines,
An electro-optical device, comprising: a switching element connected to each of the scanning lines and the data lines; and a pixel electrode electrically connected to the switching element, wherein the switching element is formed on the switching element. Connected to a first electrode such as a metal electrode formed on the first insulating film via a first contact hole formed in the first insulating film such as a first interlayer insulating film. The first electrode is formed on a second insulating film formed on the first insulating film and a second insulating film such as a second interlayer insulating film formed on the first electrode.
It is connected to the pixel electrode formed on the second insulating film via a contact hole, and the second contact hole is arranged closer to the pixel electrode than the first contact hole. .

According to the present invention, the second contact hole connecting the pixel electrode and the first electrode is arranged closer to the periphery of the pixel electrode than the first contact hole connecting the first electrode and the switching element. Since the second contact hole affecting the driving characteristics of the electro-optical element is formed at a position distant from the center of the pixel portion, the influence of the presence of the second contact hole on the driving characteristics of the electro-optical element is affected. Can be reduced.

Further, according to the present invention, in addition to the configuration of the above-mentioned invention, the second contact hole is formed on a flat portion of the first electrode.

Therefore, even if the second contact hole is miniaturized, sufficient electrical continuity can be obtained with the first electrode, and the influence of the presence of the second contact hole on the driving characteristics of the electro-optical element is further reduced. Can be reduced.

Further, according to the present invention, in addition to the above-mentioned constitutions, the electro-optical element is a liquid crystal element, the switching element is a thin-film transistor element, and the drain region of the transistor element has a drain region. It is configured to be connected to the first electrode through the first contact hole.

Therefore, in the electro-optical element using the liquid crystal element, the effect of the second contact hole on the continuity of the alignment of the liquid crystal can be reduced, and the aperture ratio in the pixel portion can be improved.

Further, according to the present invention, in addition to the constitution of each of the above-mentioned inventions, a plurality of transistors are formed by a semiconductor layer included in the transistor element being insulated from the scanning line and intersecting the scanning line a plurality of times. Are connected in series to form the transistor element.

Therefore, the drain voltage which needs to be applied to the drain region of the switching element for driving the liquid crystal element can be reduced, and the so-called off current of the transistor element can be reduced.

Further, even in a transistor element having a plurality of channel regions formed by the semiconductor layer intersecting a scanning line a plurality of times, the influence of the second contact hole on the continuity of the alignment of the liquid crystal element is reduced. Thus, the aperture ratio can be improved.

Further, according to the present invention, in addition to the constitution of the invention described above, at least the scanning line, the data line, the switching element, the first contact hole and the second contact hole are formed of an opaque material. In addition, the respective opaque bodies form a light-blocking region for blocking light incident on the electro-optical device from the outside. It is formed and configured within.

Therefore, since the light-shielding film for shielding the non-continuous plane line is formed by each opaque body, the light-shielding film is formed on the opposing substrate which faces the substrate on which the switching elements and the like are formed with the liquid crystal interposed therebetween. There is no need, and a higher aperture ratio can be achieved.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described.

Each embodiment described below is an embodiment in which the present invention is applied to a liquid crystal panel in a liquid crystal display device that displays an image or the like by electrically changing the orientation of liquid crystal. It is a form.

(I) First Embodiment First, a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows an equivalent circuit such as various elements and wirings in a plurality of pixels formed in a matrix forming an image display area of a liquid crystal panel, and FIG. 2 shows a data line and a data line according to the first embodiment. T on which scanning lines, pixel electrodes, etc. are formed
FIG. 3 is a plan view schematically showing a configuration of one pixel portion and its vicinity in the FT array substrate. FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. 2 (FIG. 3A) and a cross-sectional view taken along line BB ′. (FIG. 3 (b)) and C
3C is a cross-sectional view schematically showing each of the cross-sectional views (FIG. 3C), and FIG. 4 is a plan view showing a two-dimensional wiring layout and the like on a TFT array substrate together with peripheral circuits. 5 is a plan view of the TFT array substrate together with the components formed thereon viewed from the counter substrate side, and FIG. 6 is a cross-sectional view taken along the line HH ′ of FIG. 5 including the counter substrate.

Here, in FIG. 3, in order to make each layer and each member have a size recognizable in the drawing, the scale of each layer and each member is shown differently.

First, the schematic configuration of the plurality of pixel units will be described with reference to FIG.

As shown in FIG. 1, a TFT 30 for controlling the pixel electrode 9 is formed in a plurality of pixel portions formed in a matrix constituting an image display area of the liquid crystal panel in the first embodiment. The data line 6 for supplying an image signal is electrically connected to the source electrode of the TFT 30.

At this time, the image signals S1, S2,..., Sn written to the data lines 6 may be supplied line-sequentially in this order, or a plurality of adjacent data lines 6 may be grouped. It can be supplied every time.

On the other hand, the scanning line 3 is electrically connected to the gate electrode of the TFT 30, and the scanning signals G1 and G are pulsed to the scanning line 3 at a predetermined timing.
, Gm are applied line-sequentially in this order.

Further, the pixel electrode 9 is electrically connected to the drain electrode of the TFT 30, and by turning on the TFT 30 as a thin film switching element for a certain period, the image signal S1 supplied from the data line 6 is turned on. , S
,..., Sn are supplied to the pixel electrode 9 at a predetermined timing.

Then, the image signals S1, S2,.
By n, the image signal S is transmitted between a counter electrode (details will be described later) formed on a counter substrate (details will be described later).
The voltages corresponding to 1, S2,..., Sn are held for a certain period, and this voltage is applied to the liquid crystal.

The image signals S1, S2,..., S
The liquid crystal to which the voltage corresponding to n is applied modulates light by changing the orientation and order of the molecular assembly according to the level of the applied voltage, thereby enabling gray scale display.

At this time, in a normally white mode, incident light cannot pass through the liquid crystal portion according to the applied voltage. On the other hand, in a normally black mode, the incident light does not pass according to the applied voltage. The incident light can pass through the liquid crystal portion, and light having a contrast corresponding to the image signal is emitted from the liquid crystal panel as a whole.

Here, the stored image signals S1, S
In order to prevent Sn from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9 and the counter electrode. The voltage corresponding to the image signals S1, S2,..., Sn applied to the pixel electrode 9 is about 3 times longer than the time when the voltage of the source electrode is applied.
It is held by the storage capacitor 70 for a time that is about an order of magnitude longer.

With this configuration, the image signals S1, S
2,..., Sn retention characteristics are further improved, and a liquid crystal panel having a high contrast ratio can be realized.

As a method of forming the storage capacitor 70, a capacitor line (not shown), which is a wiring for forming a capacitor, may be used. Alternatively, the storage capacitor 70 may be connected to the preceding scanning line 3 as in the first embodiment. May form a capacitor.

Next, a specific configuration of one pixel portion and its vicinity according to the present invention will be described in detail with reference to FIGS.

First, as shown in FIG.
A plurality of transparent pixel electrodes 9 are provided in a matrix on the FT array substrate, and data lines 6 and scanning lines 3 are provided along vertical and horizontal boundaries of the pixel electrodes 9.

The data line 6 is formed of a polysilicon film and a TFT 3 through a contact hole 5.
0 is electrically connected to a source region described later in the semiconductor layer 1 forming 0.

On the other hand, the pixel electrode 9 has a contact hole 8 serving as a second contact hole and a first contact hole 8 formed in an island shape.
The semiconductor layer 1 is electrically connected to a drain region to be described later in the semiconductor layer 1 via a metal electrode 15 as an electrode and a contact hole 11 as a first contact hole.

In the semiconductor layer 1, channel regions C1 and C2 described later (regions indicated by oblique lines at the lower right in FIG. 2). In the first embodiment, a so-called dual gate type TFT 30 is formed as the TFT 30. The scanning line 3 (gate electrode) is disposed so as to face the scanning line 3).

Here, the pixel electrode 9, the metal electrode 15, and the drain region are formed in mutually different layers, and are each insulated by an interlayer insulating film described later.
Further, the pixel electrode 9 and the metal electrode 15 are in contact with the contact hole 8.
, And the metal electrode 15 and the drain region are connected using the contact hole 11.

Then, in the pixel portion of the first embodiment, from the portion where the contact hole 11 is formed,
The metal electrode 15 is oriented in the direction opposite to the center of the pixel electrode 9 (that is, the center of the pixel portion) with respect to the contact hole 11 (that is, the direction of the peripheral portion far from the center of the pixel electrode 9).
In FIG. 2, the contact hole 8 is formed to extend in the left direction (left direction), and the contact hole 8 is formed on the extended metal electrode 15.

According to this configuration, since the contact hole 8 which comes into contact with the liquid crystal is located at a position away from the center of the pixel portion, the disclination line DL in the pixel portion of the first embodiment is separated from the opening R. 2 is formed at the position shown by the dotted line in FIG.

A portion other than the opening R in the counter substrate 20 is formed with a so-called black matrix (BM) to prevent leakage of external light.

Further, in the pixel portion of the first embodiment,
By forming a part of the preceding scanning line 3 so as to extend below the corresponding data line 6 (downward in FIG. 2),
One capacitor electrode 70a constituting the storage capacitor 70 is used.

Similarly, a part of the semiconductor layer 1 is formed to extend below (upward and to the left in FIG. 2) below the data line 6 and below the scanning line 3 at the preceding stage, so that the storage capacitor 70 is formed.
Is formed as another capacitance electrode 70b.

Next, the sectional structure of each part shown in FIG. 2 will be described with reference to FIG. 3. First, as shown in FIG. , A transparent TFT array substrate 10 and a transparent counter substrate 20 disposed opposite to the TFT array substrate.

At this time, the TFT array substrate 10 is made of, for example, a quartz substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.

The pixel electrode 9 is provided on the TFT array substrate 10, and an alignment film (not shown) on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9.

Here, as the pixel electrode 9, for example, I
A transparent conductive thin film such as a TO film (indium tin oxide film) is used. As the alignment film,
For example, an organic thin film such as a polyimide thin film is used.

On the other hand, a counter electrode (common electrode) 21 is provided on the entire surface of the counter substrate 20, and the lower side of the counter electrode 20 is provided with a predetermined alignment process such as a rubbing process. A membrane is provided.

At this time, as the counter electrode 21, for example, a transparent conductive thin film such as an ITO film is used similarly to the pixel electrode 9, and the alignment film is similarly formed using an organic thin film such as a polyimide thin film. I have.

The above-described black matrix (light-shielding film) having a predetermined size and thickness is formed on the counter substrate 20.

Further, on the TFT array substrate 10, as shown in FIG. 3, the above-mentioned TFT 30 for controlling the switching of the pixel electrode 9 is provided at a position corresponding to each pixel electrode 9.

The drain region D and the source region S are formed in the TFT 30 by, for example, implanting ions as donors or acceptors into the semiconductor layer 1.

The drain region D is connected to the pixel electrode 9 via the contact hole 11, the metal electrode 15, and the contact hole 8.

The source region S is connected to the data line 6 via the contact hole 5.

Further, on the drain region D and the source region S, a gate insulating film 12 for insulating between the channel regions C1 and C2 and the scanning line 3 (gate electrode) is formed.

Further, a first interlayer insulating film 13 is formed between the metal electrode 15 or the data line 6 and the gate insulating film 12, and the contact holes 5 and 11 are formed between the gate insulating film 12 and the first insulating film 12. It is configured to penetrate through the interlayer insulating film 13 to reach the drain region D or the source region S, respectively.

Further, on the first interlayer insulating film 13,
A second interlayer insulating film 14 for insulating the pixel electrode 9 from the metal electrode 15 or the data line 6 is formed. And
The contact hole 8 is formed so as to penetrate the second interlayer insulating film 14 and reach the metal electrode 15.

Here, the second interlayer insulating film 14 insulates the pixel electrode 9 from the metal electrode 15 or the data line 6 and flattens the region where the TFT 30 is formed to form the pixel electrode 9 flat. It also has the function of a planarizing film to be formed.

The material of the first interlayer insulating film 13 or the second interlayer insulating film 14 is, for example, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG
Highly insulating glass such as (boron phosphorus silicate glass), a silicon oxide film, a silicon nitride film, or the like is used.

In FIG. 3A, as described above, the metal electrode 15 is formed to extend in the direction opposite to the center direction of the pixel portion, and the contact hole 8 is formed in the extended portion. ing.

On the other hand, the space between the TFT array substrate 10 and the opposing substrate 20 in which the pixel electrode 9 and the opposing electrode 21 face each other is surrounded by a sealing material 52 (see FIGS. 5 and 6) described later. The liquid crystal is sealed in the space, and the liquid crystal layer 50 is formed.
Is formed.

The liquid crystal layer 50 is sealed by an alignment film in a state where no electric field is applied from the pixel electrode 9 so as to take a predetermined alignment state. More specifically, the liquid crystal layer 50
Is composed of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed.

The sealing material 52 is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the counter substrate 20 around them, and a distance between the two substrates. Is set to a predetermined value, and spacers such as glass fibers or glass beads are mixed.

Next, regarding the sectional view taken along the line BB 'in FIG.
As shown in FIG. 3B, a channel region C1 made of polysilicon is formed in a part of the semiconductor layer 1 formed on the TFT array substrate 10, and a gate is formed above the channel region C1. The scanning lines 3 are arranged with the insulating film 12 interposed therebetween.

With this configuration, when the TFT 30 operates, electrons or holes are induced in the channel region C1 (and C2) at the timing when the scanning signals G1, G2,..., Gm are applied (that is, the TFT 30 is turned on). State), and the image signals S1, S supplied from the data line 6
,..., Sn to the drain region D.

On the other hand, the above-mentioned metal electrode 15 is formed on the first interlayer insulating film 13 formed on the scanning line 3, and the contact hole 8 is formed in the second interlayer insulating film 14 thereon. Further, a pixel electrode 9 is formed on the second interlayer insulating film 14 at a position corresponding to the pixel portion.

In FIG. 3B, the counter substrate 2
Since the configuration of 0 is the same as that shown in FIG. 3A, the description is omitted.

Next, regarding the sectional view taken along the line CC ′ in FIG.
As shown in FIG. 3C, a part of the semiconductor layer 1 extends below the data line 6, and serves as one capacitance electrode 70 b constituting the storage capacitor 70.

On the other hand, a capacitor electrode 70a formed by extending the preceding scanning line 3 is laminated on the capacitor electrode 70b with the gate insulating film 12 interposed therebetween.

By interposing the gate insulating film 12 between these capacitance electrodes 70a and 70b, the gate insulating film 1
Thus, a storage capacitor 70 having a dielectric film 2 is formed.

The capacitance electrode 70b is connected to the scanning line 3 in the previous stage.
The storage capacitor 70 is formed by the capacitor electrode 70b and the scanning line 3 with the gate insulating film 12 interposed therebetween.

The storage capacitor 70 having such a large area
, It is possible to hold the voltages corresponding to the image signals S1, S2,..., Sn applied from the data line 6 for a time approximately three digits longer than the application time, as described above. Becomes

Note that, also in FIG.
Since the configuration of 0 is the same as that shown in FIG. 3A, the description is omitted.

Next, referring to FIG. 4, an example of a two-dimensional layout on the TFT array substrate 10 in the liquid crystal panel of the first embodiment is shown together with peripheral circuits provided on the TFT array substrate 10.

As shown in FIG. 4, a data line driving circuit 101 for driving data lines 6 and a scanning line 3 Scanning line drive circuit 10 for driving
4, a precharge circuit 108 for supplying a precharge signal to the wiring 105 and the data line 6,
It is provided as a peripheral circuit inside.

The data line driving circuit 101 and the scanning line driving circuit 104 include a plurality of data lines 6 and scanning lines 3.
Are electrically connected to each other. The image signal converted into a format that can be displayed immediately is input to the data line driving circuit 101 from a control circuit (not shown).

Then, in response to the scanning line driving circuit 104 sequentially sending the scanning signals to the scanning lines 3 in a pulsed manner, the data line driving circuit 101 applies a signal voltage corresponding to the image signal to the data line. Send to 6.

At this time, in addition to the data line driving circuit 101, a sampling circuit (not shown) for sampling an image signal from an image signal line according to a driving signal from the data line driving circuit is provided. Is also good.

On the other hand, the precharge circuit 108 applies a precharge signal of a predetermined voltage level to the data line 6 so as to perform precharge, that is, to write the voltage of the image signal to the data line 6 with a small load. , Respectively.

Further, a peripheral partition 53 for shading is formed around an image display area including a plurality of pixel portions.
The peripheral partition 53 is a light shielding film for separating a display region on the TFT array substrate 10 from a non-display region around the display region.

Note that, of the plurality of pixel portions constituting the image display area, the storage capacitor 70 constituting one row at the top in FIG.
The other end not connected to the drain region D is connected to the scanning line drive circuit 104 via the constant potential line 71,
It is always kept at a constant potential.

Next, the actual overall configuration of the liquid crystal panel configured as described above will be described with reference to FIGS.

FIG. 5 is a plan view of the TFT array substrate 10 together with the components formed thereon as viewed from the counter substrate 20, and FIG. It is -H 'sectional drawing.

As shown in FIG. 5, the TFT array substrate 10
A sealing material 52 is provided along the edge thereof, and a light-shielding peripheral partition 53 is provided in parallel with the inside thereof.

On the other hand, in a region outside the sealing material 52, a data line driving circuit 101 and mounting terminals 102 are provided along one side of the TFT array substrate 10, and a scanning line driving circuit 104 is adjacent to this side. It is provided along the two sides of

At this time, if the delay of the scanning signal supplied to the scanning line 3 does not matter, the scanning line driving circuit 10
It goes without saying that 4 may be on one side only.

The data line driving circuits 101 may be arranged on both sides along the sides of the image display area. More specifically, for example, an image signal is supplied to the odd-numbered data lines 6 from a data line driving circuit disposed along one side of the image display area, and the even-numbered data lines 6 are supplied to the odd-numbered data lines 6. An image signal may be supplied from a data line driving circuit disposed along the opposite side of the image display area.

By driving the data lines 6 in a comb-tooth shape as described above, the area occupied by the data line driving circuit 101 can be expanded, so that a complicated circuit can be formed.

Further, the remaining one side of the TFT array substrate 10 is provided with the scanning line driving circuits 1 provided on both sides of the image display area.
A plurality of wirings 105 are provided to connect the areas 04, and a precharge circuit 108 (see FIG. 4) is provided below the peripheral partition 53.

Further, at least one corner of the counter substrate 20 is provided with a conductive material 106 for establishing electrical connection between the TFT array substrate 10 and the counter substrate 20.

As shown in FIG. 6, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 5 is fixed to the TFT array substrate 10 by the sealing material 52.

As described above, according to the liquid crystal panel of the first embodiment, the metal electrode 15 connecting the pixel electrode 9 and the drain region D and the contact hole 8 connecting the pixel electrode 9 are formed as the contact hole. Since the liquid crystal layer 5 is formed in a region to be a peripheral portion in the pixel portion with respect to
Since the contact hole 8 affecting the orientation of the pixel portion 0 is formed at a position away from the center of the pixel portion, the disclination line DL is formed at a portion near the periphery of the pixel portion, and the liquid crystal layer It is possible to improve the aperture ratio of the pixel portion by minimizing the region where the orientation of 50 is disturbed.

The contact hole 8 is formed in the metal electrode 15.
Is formed on the flat portion of the contact hole 8, sufficient electrical conduction with the metal electrode 15 can be obtained even if the contact hole 8 is miniaturized. Therefore, the contact hole 8 is miniaturized and the disclination line is formed. DL
Can be further shifted to the outside of the pixel portion, and the aperture ratio of the pixel portion can be further improved.

Further, the TFT 30 has two channel regions C
1 and C2, the drain region D is used to drive the liquid crystal layer 50 as compared with the case where the number of channel regions is one.
Can be reduced, and so-called off current of the TFT 30 can be reduced.

Further, a plurality of channel regions C1 and C1
Even in the case of the TFT 30 having two, the effect of the contact hole 8 on the uniformity of the orientation of the liquid crystal layer 50 can be reduced, and the aperture ratio can be improved.

Further, since the plurality of channel regions C1 and C2 are formed by bending and arranging the semiconductor layer 1 in a plane, the plurality of channel regions C1 and C2,
Since the drain region D and the source region S are formed close to each other, the area in the pixel portion occupied by the TFT 30 can be minimized, so that the aperture ratio in the pixel portion can be further improved.

(II) Second Embodiment Next, a second embodiment which is another embodiment of the present invention will be described with reference to FIGS.

FIG. 7 is a plan view schematically showing the structure of one pixel portion and its vicinity in a TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed according to the second embodiment. 8 is a sectional view taken along the line AA ′ of FIG.
(A)), BB 'sectional view (FIG. 8 (b)) and CC'
It is sectional drawing which shows sectional drawing (FIG.8 (c)) each typically.

In the first embodiment, the TFT 3
Although an example of the arrangement of each element when a dual-gate TFT is used as 0 has been described, in the second embodiment,
A so-called triple-gate TFT having three channel regions is used as the TFT.

In FIGS. 7 and 8, the same members as those in the first embodiment are denoted by the same reference numerals, and the detailed description is omitted.

Further, in the second embodiment, the configuration (such as a two-dimensional arrangement as a liquid crystal panel) and the operation other than the arrangement of the elements in the pixel portion are the same as those in the first embodiment.
The detailed description is also omitted.

First, as shown in FIG. 7, the TFT 30 ′ of the second embodiment is formed by bending the semiconductor layer 1 so as to traverse the scanning line 3 three times so that the three channel regions C 1, C 2 And C3 (the hatched area in the lower right part of FIG. 7).

Therefore, in the TFT 30 ′, the drain region D, the channel regions C 1, C 2 and C 3 and the source region S are connected to each other by the semiconductor layer 1.

The drain region D is connected to the island-shaped metal electrode 15 via the contact hole 11, and the metal electrode 15 is connected to the pixel electrode 9 via the contact hole 8.

At this time, in the pixel portion of the second embodiment, as in the first embodiment, the metal electrode 15 is moved from the portion where the contact hole 11 is formed to the pixel electrode 9 with respect to the contact hole 11. The contact hole 8 is formed on the extended portion of the metal electrode 15 in the direction opposite to the center of FIG. In this case, the contact hole 8 is formed above the semiconductor layer 1 connecting the channel region C2 and the channel region C3.

With this configuration, similar to the first embodiment,
Since the contact hole 8 that comes into contact with the liquid crystal is formed at a position distant from the center of the pixel portion, the disclination line DL in the pixel portion of the second embodiment is shown in FIG. It is formed at the position indicated by the dotted line.

Further, in the pixel section of the second embodiment,
As in the first embodiment, a part of the scanning line 3 in the former stage is formed so as to be correspondingly extended, thereby forming one capacitor electrode 70a constituting the storage capacitor 70, and further extending a part of the semiconductor layer 1. This forms another capacitor electrode 70b that forms the storage capacitor 70.

Next, the sectional structure of each part shown in FIG. 7 will be described with reference to FIG. 8. First, in the sectional view taken along the line AA ′ in FIG. 7, as shown in FIG.
Are connected to the pixel electrode 9 via the contact hole 11, the metal electrode 15 and the contact hole 8.

The source region S is formed in the contact hole 5
Is connected to the data line 6 via the.

In FIG. 8A, an island-shaped metal electrode 15 is formed extending in a direction opposite to the center direction of the pixel portion, and a contact hole 8 is formed in the extended portion. I have.

In FIG. 8A, the opposite substrate 2
The configuration of 0 is the same as the case shown in the first embodiment, and thus the description is omitted.

Next, regarding the sectional view taken along the line BB ′ in FIG.
As shown in FIG. 8B, a channel region C2 is formed in a part of the semiconductor layer 1 formed on the TFT array substrate 10, and a gate insulating film 12 is sandwiched above the channel region C2. , The scanning line 3 is arranged.

On the other hand, the above-mentioned metal electrode 15 is formed on the first interlayer insulating film 13 formed on the scanning line 3, and the contact hole 8 is formed in the second interlayer insulating film 14 thereon. Further, a pixel electrode 9 is formed on the second interlayer insulating film 14 at a position corresponding to the pixel portion.

In FIG. 8B, the opposite substrate 2
The configuration of 0 is the same as the case shown in the first embodiment, and thus the description is omitted.

Next, regarding the cross-sectional view taken along the line CC ′ in FIG.
As shown in FIG. 8C, a part of the semiconductor layer 1 is extended below the data line 6, and this is one capacitor electrode 70b constituting the storage capacitor 70.

On the other hand, a capacitor electrode 70a formed by extending the preceding scanning line 3 is laminated on the capacitor electrode 70b with the gate insulating film 12 interposed therebetween.

Then, by sandwiching the gate insulating film 12 between the capacitance electrodes 70a and 70b, the gate insulating film 1
A storage capacitor 70 having a dielectric film 2 is formed.

The capacitance electrode 70b is connected to the scanning line 3 in the preceding stage.
The storage capacitor 70 is formed under the capacitor electrode 70b and the scanning line 3 with the gate insulating film 12 interposed therebetween.

Note that, also in FIG.
The configuration of 0 is the same as the case shown in the first embodiment, and thus the description is omitted.

As described above, according to the liquid crystal panel of the second embodiment, the same effects as those of the liquid crystal panel of the first embodiment can be obtained, and in addition, the channel region has one channel. Since three TFTs 30 'are formed, the drain voltage required to be applied to the drain region D to drive the liquid crystal layer 50 can be further reduced as compared with the case where one or two channel regions are provided. Can,
The so-called off current of the TFT 30 can be further reduced.

Further, three channel regions C1 to C
Contact hole 8 even if TFT 30 'having
Of the liquid crystal layer 50 can be reduced, and the aperture ratio can be improved.

Further, since the plurality of channel regions C1 to C3 are formed by bending and arranging the semiconductor layer 1 in a plane, the plurality of channel regions C1 to C3,
Since the drain region S and the source region S are formed close to each other, the area in the pixel portion occupied by the TFT 30 can be minimized, so that the aperture ratio in the pixel portion can be further improved.

(III) Third Embodiment Next, a third embodiment according to the present invention will be described with reference to FIGS. 9 and 10. FIG.

FIG. 9 is a plan view schematically showing a configuration of one pixel portion and its vicinity in a TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed according to the third embodiment. 9 is a sectional view taken along the line AA ′ of FIG.
(A)), BB ′ cross-sectional view (FIG. 9 (b)) and CC ′
It is sectional drawing which shows sectional drawing (FIG.9 (c)), respectively.

In the second embodiment, the TFT 3
Although an example of the arrangement of each element when a triple gate type TFT 30 'is used as 0 has been described, in the third embodiment, a dual gate type TFT having two channel regions similar to the first embodiment is used as a TFT. A so-called light-shielding film is formed on the TFT array substrate 10 using the data lines, the scanning lines, the TFTs, and the respective contact holes (each of which is formed of an opaque material). This is an example of an element arrangement for shielding a region that has an adverse effect on image quality including the disclination line.

Also, in FIGS. 9 and 10, the first
The same members as those in the embodiment or the second embodiment are denoted by the same reference numerals, and the detailed description is omitted.

Further, in the third embodiment, the configuration (such as a two-dimensional arrangement as a liquid crystal panel) and the operation other than the arrangement of the elements in the pixel portion are the same as those in the first or second embodiment. Also, detailed description is omitted.

First, as shown in FIG. 9, the TFT 30 ″ of the third embodiment extends a part of the scanning line 3 below the contact hole 8 and also extends the extended part and the other scanning line 3 part. The semiconductor layer 1 is bent at a right angle so that the semiconductor layer 1 is disposed below the semiconductor layer 1, thereby forming two channel regions C1 and C2 (hatched regions falling rightward in FIG. 9).

Accordingly, the TFT 30 ″ has a configuration in which the drain region D, the channel regions C 1 and C 2 and the source region S are connected to each other by the semiconductor layer 1.

The drain region D is connected to the island-shaped metal electrode 15 via the contact hole 11, and the metal electrode 15 is connected to the pixel electrode 9 via the contact hole 8.

At this time, in the pixel portion according to the third embodiment, as in the first embodiment or the third embodiment, the metal electrode 15 extends from the portion where the contact hole 11 is formed.
Is formed in the direction opposite to the center of the pixel electrode 9 with respect to the contact hole 11 (to the left in FIG. 9), and the contact hole 8 is formed on the extended metal electrode 15. I have. In this case, contact hole 8 is formed above channel region C2.

Accordingly, the extension of the scanning line 3 exists below the contact hole 8 of the third embodiment, and as a result, the depth of the contact hole 8 becomes smaller than that of the first embodiment or the second embodiment. Therefore, the planar size of the contact hole 8 itself is also reduced.

With this configuration, as in the first embodiment or the second embodiment, the contact hole 8 that comes into contact with the liquid crystal is formed at a position away from the center of the pixel portion. The disclination line DL in the pixel portion is formed at a position shown by a dotted line in FIG. 9 away from the opening.

In the structure shown in FIG. 9, the size of the contact hole 8 can be reduced as described above, and the contact hole 8 can be further formed at the left position in FIG. 9, so that the disclination line DL is formed at the further left position. Thus, a higher aperture ratio can be achieved.

Further, in the pixel section of the third embodiment,
As in the first embodiment or the second embodiment, a part of the scanning line 3 in the preceding stage is formed to be correspondingly extended, thereby forming one capacitance electrode 70a constituting the storage capacitor 70, and furthermore, the semiconductor layer 1 Is formed as an extension of a part of the capacitor electrode 70b to form another capacitor electrode 70b constituting the storage capacitor 70.

Next, the sectional structure of each part shown in FIG. 9 will be described with reference to FIG. 10. First, in the sectional view taken along the line AA ′ in FIG. 9, as shown in FIG. Are connected to the pixel electrode 9 via the contact hole 11, the metal electrode 15 and the contact hole 8.

The source region S is formed in the contact hole 5
Is connected to the data line 6 via the.

In FIG. 10A, an island-shaped metal electrode 15 is formed extending in a direction opposite to the center direction of the pixel portion, and a contact hole 8 is formed in the extended portion. I have.

Further, in the TFT 30 ″, unlike the first or second embodiment, a lightly doped doping region C 1 ′ is formed between the channel region C 1 and the drain region D. Therefore, the TFT 30 ″ of the third embodiment is a so-called LDD (Lightly
Doped Drain) structure.

In FIG. 10A, the configuration of the counter substrate 20 is the same as that of the first embodiment or the second embodiment, so that the description is omitted.

Next, regarding the sectional view taken along the line BB ′ in FIG.
As shown in FIG. 10B, a channel region C1 is formed immediately below the contact hole 8, and a layer between the channel region C1 and the contact hole 8 has a gate insulating film 12 with respect to the channel region C1. And the metal electrode 15 is formed.

In the same layer as the layer in which the channel region C1 is formed, the storage capacitor 70 in the next-stage pixel portion is provided.
And a semiconductor layer 1 connected to the capacitor electrode 70b formed below the data line 6 is formed.

In FIG. 10B, the configuration of the opposing substrate 20 is the same as that of the first embodiment or the second embodiment, so that the description is omitted.

Next, with respect to the sectional view taken along the line CC ′ in FIG.
As shown in FIG. 10C, a part of the semiconductor layer 1 is extended below the data line 6 and serves as one capacitor electrode 70b constituting the storage capacitor 70.

On the other hand, a capacitor electrode 70a formed by extending the preceding scanning line 3 is laminated on the capacitor electrode 70b with the gate insulating film 12 interposed therebetween.

By interposing the gate insulating film 12 between these capacitance electrodes 70a and 70b, the gate insulating film 1
A storage capacitor 70 having a dielectric film 2 is formed.

The capacitance electrode 70b is connected to the scanning line 3 in the preceding stage.
The storage capacitor 70 is formed under the capacitor electrode 70b and the scanning line 3 with the gate insulating film 12 interposed therebetween.

In FIG. 10C, the configuration of the counter substrate 20 is the same as that of the first embodiment or the second embodiment, so that the description is omitted.

As described above, according to the liquid crystal panel of the third embodiment, the same effects as those of the liquid crystal panel of the first or second embodiment can be obtained, and the data lines, A light-shielding film is formed on the TFT array substrate 10 using the scanning lines, the TFTs, and the respective contact holes, and the light-shielding film shields the area including the disclination line DL that has an adverse effect on image quality. Since the DL is further formed on the peripheral portion in the pixel portion, it is not necessary to form a light-shielding film on the counter substrate side, and a higher aperture ratio can be achieved.

Note that an inspection circuit or the like for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or shipping may be further formed on the TFT array substrate 10 of each of the above-described embodiments.

Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a driving LSI mounted on a TAB (tape automated bonding substrate) is mounted on the TFT array substrate. The connection may be made electrically and mechanically via an anisotropic conductive film provided on the periphery of the device 10.

Furthermore, the TN (twisted nematic) mode, the STN (super TN) mode, the D-STN mode, and the like are provided on the side of the opposite substrate 20 on which the projected light is incident and on the side of the TFT array substrate 10 on which the emitted light is emitted, respectively. (Double-STN) mode, and normally white mode / normally black mode.
A polarizing film, a retardation film, a polarizing plate and the like can be arranged in a predetermined direction.

Here, since the liquid crystal panel in each of the embodiments described above is applied to a color liquid crystal projector, three liquid crystal panels are used as RGB light valves, and each panel has an RGB color separation. The light of each color decomposed via the dichroic mirror for light is incident as projection light.

Therefore, in each embodiment, no color filter is provided on the counter substrate 20.

However, an RGB color filter may be formed on the counter substrate 20 together with the protective film in a region where the opening R faces the pixel electrode 9. In this way, the liquid crystal panel in each embodiment can be applied to a color liquid crystal device such as a direct-view or reflection type color liquid crystal television other than the liquid crystal projector.

Further, a micro lens may be formed on the counter substrate 20 so as to correspond to one pixel. In this case, a bright liquid crystal device can be realized by improving the efficiency of collecting incident light.

Furthermore, a dichroic filter that produces RGB colors by utilizing light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color liquid crystal display device can be realized.

The TFT provided for each pixel has been described as being a polysilicon TFT, but other types of TFT such as an amorphous silicon TFT may be used.
The present invention is also effective for T.

Furthermore, a so-called self-aligned TFT
The present invention is also effective for an offset type TFT and an offset type TFT.

[0168]

As described above, according to the present invention,
Since the second contact hole affecting the driving characteristics of the electro-optical element is formed at a position away from the center of the pixel portion, the influence of the presence of the second contact hole on the driving characteristics of the electro-optical element is reduced. can do.

More specifically, since the second contact hole which affects the continuity of the alignment of the liquid crystal element is formed away from the center of the pixel portion, the effect is reduced to reduce the aperture ratio in the pixel portion. Can be improved.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of various elements, wirings, and the like provided in a plurality of pixel units in a matrix forming an image forming area according to a first embodiment.

FIG. 2 is a plan view schematically showing a configuration of one pixel portion in a TFT array substrate on which a data line, a scanning line, a pixel electrode, and the like according to the first embodiment are formed, and the vicinity thereof.

FIG. 3 is a cross-sectional view of each part of FIG. 2;
FIG. 2B is a cross-sectional view schematically showing a section taken along the line −A ′, and FIG.
3 is a cross-sectional view schematically showing a BB ′ cross section of FIG. 2, and FIG. 3C is a cross-sectional view schematically showing a CC ′ cross section of FIG.

FIG. 4 is a plan view showing a two-dimensional wiring layout and the like on a TFT array substrate together with peripheral circuits.

FIG. 5 is a plan view of a TFT array substrate together with components formed thereon viewed from a counter substrate side.

FIG. 6 is a cross-sectional view taken along the line HH ′ of FIG. 5 including a counter substrate.

FIG. 7 is a plan view schematically showing a configuration of one pixel portion and its vicinity in a TFT array substrate on which a data line, a scanning line, a pixel electrode, and the like according to a second embodiment are formed.

FIG. 8 is a cross-sectional view of each part of FIG. 7;
FIG. 8B is a cross-sectional view schematically showing a section taken along the line −A ′, and FIG.
8 is a cross-sectional view schematically showing a BB ′ cross section of FIG. 7, and FIG. 8C is a cross-sectional view schematically showing a CC ′ cross section of FIG.

FIG. 9 is a plan view schematically showing a configuration of one pixel portion and its vicinity in a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like according to a third embodiment are formed.

10A and 10B are cross-sectional views of respective parts in FIG. 9; FIG. 10A is a cross-sectional view schematically showing an AA ′ cross-section in FIG. 9; It is sectional drawing shown typically, (c)
FIG. 10 is a cross-sectional view schematically showing a CC ′ cross section of FIG. 9.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor layer 3 ... Scanning line (gate electrode) 5, 8, 11 ... Contact hole 6 ... Data line (source electrode) 9 ... Pixel electrode 10 ... TFT array substrate 12 ... Gate insulating film 13 ... First interlayer insulating film 14 ... second interlayer insulating film 15 ... metal electrode 20 ... counter substrate 21 ... counter electrode 30, 30 ', 30' '... TFT 50 ... liquid crystal layer 52 ... seal material 53 ... partition 70 ... storage capacitance 71 ... constant potential line 70a 70b Capacitance electrode 101 Data line drive circuit 104 Scan line drive circuit 108 Precharge circuit C1, C2, C3 Channel region C1 'Doping region DL Disclination line R Opening D Drain region S Source area

Claims (5)

[Claims] 1. An electric device comprising: a plurality of scanning lines; a plurality of data lines; a switching element connected to each of the scanning lines and each of the data lines; and a pixel electrode electrically connected to the switching element. An optical device, wherein the switching element is connected to a first electrode formed on the first insulating film via a first contact hole formed in a first insulating film formed on the switching element. Being connected, the first electrode is formed on the second insulating film via a second contact hole formed in the first insulating film and a second insulating film formed on the first electrode. An electro-optical device, wherein the second contact hole is arranged closer to the periphery of the pixel electrode than the first contact hole. 2. The electro-optical device according to claim 1, wherein the second contact hole is formed on a flat portion of the first electrode. 3. The electro-optical device according to claim 1, wherein the electro-optical element is a liquid crystal element, the switching element is a thin-film transistor element, and the drain region of the transistor element is the thin-film transistor element. An electro-optical device, wherein the electro-optical device is connected to the first electrode via a first contact hole. 4. The electro-optical device according to claim 3, wherein a semiconductor layer included in the transistor element is insulated from the scan line and crosses the scan line a plurality of times to connect a plurality of transistors in series. An electro-optical device, wherein the transistor element is formed. 5. The electro-optical device according to claim 3, wherein at least the scanning line, the data line, the switching element, the first contact hole, and the second contact hole are opaque. A light-blocking region for blocking light incident on the electro-optical device from the outside by the respective opaque bodies; and a discontinuous surface line indicating a discontinuous surface of liquid crystal in the liquid crystal element. Is formed in the light shielding area.