JP3733769B2 - Liquid crystal device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention belongs to the technical field of electro-optical devices, and more specifically, to the technical field of the configuration of each pixel unit included in an electro-optical device that displays an image or the like using a liquid crystal element as an electro-optical element.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as an electro-optical device formed by arranging pixel units including electro-optical elements in a matrix, for example, a liquid crystal layer that is driven by applying a voltage by a pixel electrode formed for each pixel unit is provided. An active matrix liquid crystal display device is generally widely known.
[0003]
The liquid crystal display device includes a switching element that drives a liquid crystal element for each pixel portion by applying a driving voltage to the pixel electrode for each of the plurality of pixel portions included in the liquid crystal display device. As the switching element, a so-called thin film transistor (hereinafter simply referred to as a TFT (Thin Film Transistor)) is often used due to the necessity of downsizing and the like.
[0004]
Here, a typical configuration of the thin film transistor includes, for example, a drain region, a source region, and a channel region in the thin film semiconductor layer by implanting donor ions or acceptor ions into the thin film semiconductor layer such as a polysilicon layer. The drain region is connected to the pixel electrode via a drain electrode, while the source region is connected to a data line to which a data signal is supplied via a source electrode, and the channel region includes a gate. Some are formed such that a scanning signal is applied from a gate electrode (scanning line) formed immediately above the insulating film.
[0005]
Then, a channel for allowing electrons or holes to pass through the channel region is formed by the scanning signal, a data signal supplied to the source region by the channel is transmitted to the drain region, and the pixel electrode is further passed through the drain electrode. The data signal is applied to the liquid crystal element to drive the liquid crystal element.
[0006]
Here, since the drain region, the drain electrode, and the pixel electrode are formed to be thinned with an interlayer insulating film interposed therebetween, the drain region, the drain electrode, the drain electrode, and the pixel electrode are electrically connected to each other. Requires so-called interlayer contacts that connect the layers in which the respective regions or electrodes are formed.
[0007]
In this case, in the conventional liquid crystal display device, after the drain region and the drain electrode are connected by the first interlayer contact, the drain electrode is extended in the center direction of the pixel portion, and the drain electrode and the drain electrode are connected to the extended position. A configuration in which a second interlayer contact connecting the pixel electrode is generally used.
[0008]
This is because, when the second interlayer contact is formed immediately above the first interlayer contact, the etchant for the wet etching is drain region when the interlayer contact is formed by photolithography. This is because the drain region may be eroded and the drain region may be eroded.
[0009]
[Problems to be solved by the invention]
However, according to the arrangement of the conventional interlayer contacts, the first interlayer contact is formed in the pixel portion at a position close to the area related to the actual display, and therefore the liquid crystal orientation is adversely affected. There was a problem that there was.
[0010]
That is, since the first interlayer contact is for applying a data signal to the pixel electrode, it is inevitably at the same potential as the pixel electrode when the liquid crystal is driven. A voltage is applied from the lateral direction to the liquid crystal in the vicinity of the interlayer contact, and this disturbs the orientation of the liquid crystal in the vicinity.
[0011]
And this means that a so-called disclination line indicating a discontinuous surface of liquid crystal orientation is formed in a more central direction in the pixel portion, resulting in a decrease in aperture ratio as the pixel portion. It leads to.
[0012]
Furthermore, this decrease in the aperture ratio of the pixel portion leads to a decrease in luminance as a liquid crystal display device. In such a case, it is necessary to increase the aperture ratio as much as possible.
[0013]
SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device capable of increasing the aperture ratio in an electro-optical device having a plurality of pixel portions. It is in.
[0014]
[Means for Solving the Problems]
The present invention provides a plurality of scanning lines disposed on a first substrate, a plurality of data lines, and each scanning line and each data line connected to the vicinity of the intersection of the scanning line and the data line. A switching element disposed on the second substrate, a pixel electrode electrically connected to the switching element, a counter electrode disposed on the second substrate and facing the pixel electrode, and between the first and second substrates A liquid crystal device having a liquid crystal arranged in
  The switching element is connected to a first electrode formed on the first insulating film through a first contact hole formed in the first insulating film disposed on the switching element,
  The first electrode is connected to the pixel electrode formed on the second insulating film through a second contact hole formed in the first insulating film and the second insulating film disposed on the first electrode. Connected,
  The second contact hole is disposed in the vicinity of the intersection, on the peripheral side farther from the center of the pixel electrode than the first contact hole, and a data line connected to the switching element; The first contact hole is disposed between the first contact hole and the first contact hole.
[0015]
  According to the present invention, since the second contact hole connecting the pixel electrode and the first electrode is arranged on the peripheral side of the pixel electrode rather than the first contact hole connecting the first electrode and the switching element, the liquid crystal Since the second contact hole that affects the driving characteristics is formed at a position away from the center of the pixel portion, the influence of the presence of the second contact holes on the driving characteristics of the liquid crystal can be reduced.
[0016]
According to the present invention, in addition to the configuration of the above invention, the second contact hole is formed on a flat portion of the first electrode.
[0017]
  Therefore, even if the second contact hole is reduced in size, sufficient electrical continuity can be obtained between the first electrode and the influence of the presence of the second contact hole on the driving characteristics of the liquid crystal can be further reduced. .
[0018]
  Furthermore, in addition to the configuration of each of the inventions described above, the present invention provides that the switching element is a thinned transistor element, and the drain region of the transistor element is connected to the first electrode through the first contact hole. Has been configured.
[0019]
Therefore, in an electro-optic element using a liquid crystal element, the influence of the second contact hole on the alignment continuity of the liquid crystal can be reduced, and the aperture ratio in the pixel portion can be improved.
[0020]
Furthermore, in addition to the structures of the respective inventions described above, the present invention provides a plurality of transistors connected in series by a semiconductor layer included in the transistor element being insulated from the scanning line and intersecting the scanning line a plurality of times. Thus, the transistor element is formed.
[0021]
Therefore, the drain voltage required to be applied to the drain region of the switching element in order to drive the liquid crystal element can be reduced, and so-called off current of the transistor element can be reduced.
[0022]
Further, even in a transistor element having a plurality of channel regions formed by the semiconductor layer intersecting the scanning line a plurality of times, the influence of the second contact hole on the continuity of the alignment of the liquid crystal element is reduced and the aperture ratio is reduced. Can be improved.
[0023]
Further, according to the present invention, in addition to the configuration of each of the above inventions, at least the scanning line, the data line, the switching element, the first contact hole, and the second contact hole are formed of an opaque body. Each opaque body forms a light shielding region for shielding light incident on the electro-optical device from the outside, and further, a discontinuous surface line indicating a liquid crystal discontinuous surface in the liquid crystal element is formed in the light shielding region. Configured.
[0024]
Therefore, since each opaque body forms a light-shielding film that shields the discontinuous surface line, there is no need to form a light-shielding film on the opposing substrate that faces the substrate on which the switching elements are formed with the liquid crystal sandwiched therebetween. , Higher aperture ratio can be achieved.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Next, preferred embodiments of the present invention will be described.
[0026]
In addition, each embodiment described below is an embodiment when the present invention is applied to a liquid crystal panel in a liquid crystal display device that displays an image or the like by electrically changing the orientation of the liquid crystal. .
[0027]
(I)First embodiment
First, a first embodiment of the present invention will be described with reference to FIGS.
[0028]
1 shows an equivalent circuit of various elements, wirings, etc. in a plurality of pixels formed in a matrix forming the image display area of the liquid crystal panel, and FIG. 2 shows data lines, scanning lines, and the like according to the first embodiment. FIG. 3 is a plan view schematically showing a configuration of one pixel portion in the TFT array substrate on which a pixel electrode or the like is formed and its vicinity, and FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. 2 (FIG. 3A). , BB ′ cross-sectional view (FIG. 3B) and CC ′ cross-sectional view (FIG. 3C) are schematic cross-sectional views, respectively, and FIG. 4 is a two-dimensional view on the TFT array substrate. FIG. 5 is a plan view of the TFT array substrate as viewed from the counter substrate side together with the components formed thereon, and FIG. 6 includes the counter substrate. It is HH 'sectional drawing of FIG.
[0029]
Here, in FIG. 3, in order to make each layer and each member large enough to be recognized on the drawing, the scale is different for each layer and each member.
[0030]
First, a schematic configuration of the plurality of pixel portions will be described with reference to FIG.
[0031]
As shown in FIG. 1, TFTs 30 for controlling the pixel electrodes 9 are formed in a plurality of pixel portions formed in a matrix that constitutes the image display area of the liquid crystal panel in the first embodiment. A data line 6 for supplying a signal is electrically connected to the source electrode of the TFT 30.
[0032]
At this time, the image signals S1, S2,..., Sn written to the data lines 6 may be supplied line-sequentially in this order, or supplied to each of a plurality of adjacent data lines 6 for each group. You can also do it.
[0033]
On the other hand, the scanning line 3 is electrically connected to the gate electrode of the TFT 30, and the scanning signals G1, G2,..., Gm are pulsed to the scanning line 3 in this order at a predetermined timing set in advance. It is configured to apply line-sequentially.
[0034]
Further, the pixel electrode 9 is electrically connected to the drain electrode of the TFT 30. By turning on the TFT 30 as a thin film switching element only for a certain period, the image signals S1, S2,. ..., Sn is supplied to the pixel electrode 9 at a predetermined timing.
[0035]
Then, the image signals S1, S2,..., Sn with the counter electrodes (details will be described later) formed on the counter substrate (details will be described later) by the image signals S1, S2,. A voltage corresponding to is held for a certain period, and this voltage is applied to the liquid crystal.
[0036]
Then, the liquid crystal to which the voltage corresponding to the image signals S1, S2,..., Sn is applied modulates the light by changing the orientation and order of the molecular assembly according to the level of the applied voltage. Enable key display.
[0037]
At this time, in the normally white mode, incident light cannot pass through the liquid crystal portion according to the applied voltage. On the other hand, in the normally black mode, the incident light is incident according to the applied voltage. The liquid crystal part is allowed to pass through, and light having a contrast corresponding to the image signal is emitted from the liquid crystal panel as a whole.
[0038]
Here, in order to prevent the held image signals S1, S2,..., Sn from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the counter electrode. Yes. The voltages corresponding to the image signals S1, S2,..., Sn applied to the pixel electrode 9 are held by the storage capacitor 70 for a period of about three orders of magnitude longer than the time when the source electrode voltage is applied. .
[0039]
With this configuration, the holding characteristics of the image signals S1, S2,..., Sn are further improved, and a liquid crystal panel with a high contrast ratio can be realized.
[0040]
As a method of forming the storage capacitor 70, a capacitor line (not shown) that is a wiring for forming a capacitor may be used, or the capacitor may be connected to the preceding scanning line 3 as in the first embodiment. It may be formed.
[0041]
Next, a specific configuration of one pixel portion and its vicinity according to the present invention will be described in detail with reference to FIGS.
[0042]
First, as shown in FIG. 2, a plurality of transparent pixel electrodes 9 are provided in a matrix on the TFT array substrate of the liquid crystal panel, and the data lines 6 and 6 are arranged along the vertical and horizontal boundaries of the pixel electrodes 9, respectively. A scanning line 3 is provided.
[0043]
Among these, the data line 6 is electrically connected to a source region, which will be described later, of the semiconductor layer 1 formed of a polysilicon film and forming the TFT 30 via the contact hole 5.
[0044]
On the other hand, the pixel electrode 9 includes a contact hole 8 as a second contact hole, a metal electrode 15 as a first electrode formed in an island shape, and a contact hole 11 as a first contact hole. It is electrically connected to a drain region described later.
[0045]
In addition, channel regions C1 and C2 described later in the semiconductor layer 1 (shaded regions in the right-downward direction in FIG. 2. In the first embodiment, a so-called dual gate TFT 30 is formed as the TFT 30). The scanning line 3 (gate electrode) is arranged so as to face the electrode.
[0046]
Here, the pixel electrode 9, the metal electrode 15 and the drain region are formed in mutually different layers, and each is insulated by an interlayer insulating film which will be described later, and the pixel electrode 9 and the metal electrode 15 are in contact with each other. The hole 8 is used for connection, and the metal electrode 15 and the drain region are connected using the contact hole 11.
[0047]
In the pixel portion of the first embodiment, the metal electrode 15 is opposite to the center of the pixel electrode 9 (that is, the center of the pixel portion) with respect to the contact hole 11 from the portion where the contact hole 11 is formed. The contact hole 8 is formed extending in the direction (that is, the direction of the peripheral part far from the center of the pixel electrode 9, and the left direction in FIG. 2).
[0048]
With this configuration, since the contact hole 8 that comes into contact with the liquid crystal is located away from the center of the pixel portion, the disclination line DL in the pixel portion of the first embodiment is separated from the opening R as shown in FIG. Are formed at positions indicated by dotted lines.
[0049]
A portion other than the opening R in the counter substrate 20 is formed with a so-called black matrix (BM) in order to prevent leakage of external light and the like.
[0050]
Furthermore, in the pixel portion of the first embodiment, a storage capacitor 70 is configured by extending a part of the scanning line 3 in the previous stage to extend below the corresponding data line 6 (downward in FIG. 2). One capacitive electrode 70a is used.
[0051]
Similarly, by forming a part of the semiconductor layer 1 below the data line 6 and below the scanning line 3 in the previous stage (upward and leftward in FIG. 2), other components constituting the storage capacitor 70 are formed. The capacitor electrode 70b is used.
[0052]
Next, the cross-sectional structure of each part shown in FIG. 2 will be described with reference to FIG. 3. First, as shown in FIG. 3A, the liquid crystal panel is transparent with respect to the AA cast f surface in FIG. A TFT array substrate 10 and a transparent counter substrate 20 disposed to face the TFT array substrate 10 are provided.
[0053]
At this time, the TFT array substrate 10 is made of, for example, a quartz substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.
[0054]
The TFT array substrate 10 is provided with a pixel electrode 9, and an alignment film (not shown) on which a predetermined alignment process such as a rubbing process has been performed is provided above the pixel electrode 9.
[0055]
Here, as the pixel electrode 9, for example, a transparent conductive thin film such as an ITO film (indium tin oxide film) is used. As the alignment film, for example, an organic thin film such as a polyimide thin film is used.
[0056]
On the other hand, the counter substrate 20 is provided with a counter electrode (common electrode) 21 over the entire surface thereof, and an alignment film (not shown) subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 20. It has been.
[0057]
At this time, as the counter electrode 21, for example, a transparent conductive thin film such as an ITO film is used similarly to the pixel electrode 9, and an organic thin film such as a polyimide thin film is similarly used as the alignment film.
[0058]
The counter substrate 20 is formed with the black matrix (light shielding film) having a predetermined size and film thickness.
[0059]
Further, on the TFT array substrate 10, as shown in FIG. 3, the TFT 30 for switching control of the pixel electrode 9 is provided at a position corresponding to each pixel electrode 9.
[0060]
Here, the drain region D and the source region S are formed in the TFT 30 by a method such as implanting ions as donors or acceptors into the semiconductor layer 1.
[0061]
The drain region D is connected to the pixel electrode 9 through the contact hole 11, the metal electrode 15, and the contact hole 8.
[0062]
The source region S is connected to the data line 6 through the contact hole 5.
[0063]
Further, on the drain region D and the source region S, a gate insulating film 12 that insulates between the channel regions C1 and C2 and the scanning line 3 (gate electrode) is formed.
[0064]
Furthermore, a first interlayer insulating film 13 is formed between the metal electrode 15 or the data line 6 and the gate insulating film 12, and the contact holes 5 and 11 are formed in the gate insulating film 12 and the first interlayer insulating film. 13 to reach the drain region D or the source region S, respectively.
[0065]
A second interlayer insulating film 14 for insulating the pixel electrode 9 from the metal electrode 15 or the data line 6 is formed on the first interlayer insulating film 13. The contact hole 8 is formed so as to penetrate the second interlayer insulating film 14 and reach the metal electrode 15.
[0066]
Here, the second interlayer insulating film 14 insulates the pixel electrode 9 from the metal electrode 15 or the data line 6 and flattens the region where the TFT 30 is formed in order to form the pixel electrode 9 flat. It also has the function of a chemical film.
[0067]
In addition, as a material of the 1st interlayer insulation film 13 or the 2nd interlayer insulation film 14, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), for example Or the like, or a silicon oxide film, a silicon nitride film, or the like is used.
[0068]
In FIG. 3A, as described above, the metal electrode 15 is formed extending in the direction opposite to the center direction of the pixel portion, and the contact hole 8 is formed in the extended portion.
[0069]
On the other hand, a space surrounded by a sealing material 52 (see FIGS. 5 and 6), which will be described later, between the TFT array substrate 10 and the counter substrate 20 disposed so that the pixel electrode 9 and the counter electrode 21 face each other. The liquid crystal is sealed in and the liquid crystal layer 50 is formed.
[0070]
The liquid crystal layer 50 is sealed so as to take a predetermined alignment state by an alignment film in a state where an electric field from the pixel electrode 9 is not applied. More specifically, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed.
[0071]
The sealing material 52 is an adhesive made of, for example, a photocurable resin or a thermosetting resin for bonding the TFT array substrate 10 and the counter substrate 20 around them, and the distance between the substrates is set to a predetermined value. For example, spacers such as glass fiber or glass beads are mixed.
[0072]
Next, regarding the BB ′ cross-sectional view in FIG. 2, as shown in FIG. 3B, a channel region C1 made of polysilicon is formed in a part of the semiconductor layer 1 formed on the TFT array substrate 10. The scanning line 3 is disposed above the channel region C1 with the gate insulating film 12 interposed therebetween.
[0073]
With this configuration, when the TFT 30 operates, electrons or holes are induced in the channel region C1 (and C2) at the timing when the scanning signals G1, G2,..., Gm are applied (that is, the TFT 30 is turned on). The image signals S1, S2,..., Sn supplied from the data line 6 are transmitted to the drain region D.
[0074]
On the other hand, the above-described metal electrode 15 is formed on the first interlayer insulating film 13 formed on the scanning line 3, and the contact hole 8 is formed in the second interlayer insulating film 14 thereon, and further, A pixel electrode 9 is formed at a position corresponding to the pixel portion on the second interlayer insulating film 14.
[0075]
In FIG. 3B, the configuration of the counter substrate 20 is the same as that shown in FIG.
[0076]
2, a part of the semiconductor layer 1 is extended under the data line 6 as shown in FIG. 3C, and this constitutes the storage capacitor 70. Capacitance electrode 70b.
[0077]
On the other hand, a capacitor electrode 70a formed by extending the scanning line 3 in the previous stage is stacked on the capacitor electrode 70b with the gate insulating film 12 interposed therebetween.
[0078]
Then, the storage capacitor 70 using the gate insulating film 12 as a dielectric film is formed by sandwiching the gate insulating film 12 between the capacitor electrodes 70a and 70b.
[0079]
Note that the capacitor electrode 70b extends below the preceding scanning line 3 itself, and in this part also, the storage capacitor 70 is formed by the capacitor electrode 70b and the scanning line 3 with the gate insulating film 12 interposed therebetween. ing.
[0080]
By forming the storage capacitor 70 having such a large area, as described above, the voltage corresponding to the image signals S1, S2,..., Sn applied from the data line 6 is about 3 times longer than the application time. It is possible to hold only about a digit longer time.
[0081]
In FIG. 3C as well, the configuration of the counter substrate 20 is the same as that shown in FIG.
[0082]
Next, an example of a two-dimensional layout on the TFT array substrate 10 in the liquid crystal panel of the first embodiment will be shown together with peripheral circuits provided on the TFT array substrate 10 with reference to FIG.
[0083]
As shown in FIG. 4, a data line driving circuit 101 for driving the data lines 6 and a scanning line 3 are driven on the TFT array substrate 10 in the periphery of the image display region including a plurality of the pixel portions described above on a matrix. A precharge circuit 108 that supplies a precharge signal to the scanning line driving circuit 104, the wiring 105, and the data line 6 is provided as a peripheral circuit in the TFT array substrate 10.
[0084]
Among these, the data line driving circuit 101 and the scanning line driving circuit 104 are electrically connected to the plurality of data lines 6 and the scanning lines 3, respectively. The image signal converted into a format that can be immediately displayed is input to the data line driving circuit 101 from a control circuit (not shown).
[0085]
Thereafter, the data line driving circuit 101 sends a signal voltage corresponding to the image signal to the data line 6 in response to the scanning line driving circuit 104 sequentially sending the scanning signal to the scanning line 3 in a pulse manner. .
[0086]
At this time, in addition to the data line driving circuit 101, a sampling circuit (not shown) for sampling the image signal from the image signal line in accordance with the driving signal from the data line driving circuit may be provided.
[0087]
On the other hand, the precharge circuit 108 precedes the image signal with a precharge signal of a predetermined voltage level on the data line 6 so as to perform precharge, that is, to write the voltage of the image signal to the data line 6 with a small load. Each is configured to supply.
[0088]
In addition, a light-blocking peripheral parting 53 is formed around an image display area including a plurality of pixel portions. The peripheral parting 53 is a light shielding film for distinguishing between the display area on the TFT array substrate 10 and the non-display area around the display area.
[0089]
Note that, among the plurality of pixel portions constituting the image display region, the other end not connected to the drain region D of the storage capacitor 70 constituting the uppermost row in FIG. 4 is scanned via the constant potential line 71. It is connected to the drive circuit 104 and is always held at a constant potential.
[0090]
Next, the actual overall configuration of the liquid crystal panel configured as described above will be described with reference to FIGS.
[0091]
FIG. 5 is a plan view of the TFT array substrate 10 as viewed from the side of the counter substrate 20 together with the components formed thereon, and FIG. 6 shows the HH ′ of FIG. It is sectional drawing.
[0092]
As shown in FIG. 5, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and a light-blocking peripheral parting 53 is provided in parallel to the inside thereof.
[0093]
On the other hand, the data line driving circuit 101 and the mounting terminal 102 are provided along one side of the TFT array substrate 10 in the region outside the sealing material 52, and the scanning line driving circuit 104 has two sides adjacent to the one side. It is provided along.
[0094]
At this time, if the delay of the scanning signal supplied to the scanning line 3 does not become a problem, it goes without saying that the scanning line driving circuit 104 may be only on one side.
[0095]
Further, the data line driving circuit 101 may be arranged on both sides along the side of the image display area. More specifically, for example, an image signal is supplied from the data line driving circuit disposed along one side of the image display area to the odd-numbered data lines 6, and the even-numbered data lines 6 You may make it supply an image signal from the data line drive circuit arrange | positioned along the edge | side on the opposite side of an image display area.
[0096]
If the data line 6 is driven in a comb-like shape in this way, the area occupied by the data line driving circuit 101 can be expanded, so that a complicated circuit can be configured.
[0097]
Furthermore, a plurality of wirings 105 are provided on the remaining side of the TFT array substrate 10 to connect between the scanning line driving circuits 104 provided on both sides of the image display region. A precharge circuit 108 (see FIG. 4) is provided.
[0098]
Further, at least one corner portion of the counter substrate 20 is provided with a conductive material 106 for electrical conduction between the TFT array substrate 10 and the counter substrate 20.
[0099]
As shown in FIG. 6, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 5 is fixed to the TFT array substrate 10 by the sealing material 52.
[0100]
As described above, according to the liquid crystal panel of the first embodiment, the metal electrode 15 that connects the pixel electrode 9 and the drain region D and the contact hole 8 that connects the pixel electrode 9 are connected to the contact hole 11. Since the contact hole 8 that affects the orientation of the liquid crystal layer 50 is formed at a position away from the center of the pixel portion, the disclination line is formed. The DL is formed in a portion close to the periphery of the pixel portion, and the region where the orientation of the liquid crystal layer 50 is disturbed can be limited to improve the aperture ratio of the pixel portion.
[0101]
Further, since the contact hole 8 is formed on a flat portion of the metal electrode 15, even when the contact hole 8 is reduced in size, sufficient electrical continuity can be obtained with the metal electrode 15. 8 can be reduced in size, and the disclination line DL can be further moved to the outside of the pixel portion, so that the aperture ratio of the pixel portion can be further improved.
[0102]
Furthermore, since the TFT 30 has two channel regions C1 and C2, the drain voltage required to be applied to the drain region D in order to drive the liquid crystal layer 50 is reduced as compared with the case where the channel region is one. Thus, the so-called off current of the TFT 30 can be reduced.
[0103]
Furthermore, the TFT 30 having a plurality of channel regions C1 and C2 can improve the aperture ratio by reducing the influence of the contact hole 8 on the uniformity of the orientation of the liquid crystal layer 50.
[0104]
Further, since the plurality of channel regions C1 and C2 are formed by bending and arranging the semiconductor layer 1 in a plane, the plurality of channel regions C1 and C2, the drain region D, and the source region S are close to each other. As a result, the region in the pixel portion occupied by the TFT 30 can be minimized, so that the aperture ratio in the pixel portion can be further improved.
[0105]
(II)Second embodiment
Next, a second embodiment which is another embodiment according to the present invention will be described with reference to FIGS.
[0106]
FIG. 7 is a plan view schematically showing a configuration of one pixel portion in the TFT array substrate on which data lines, scanning lines, pixel electrodes and the like according to the second embodiment are formed and the vicinity thereof. 7 schematically shows the AA ′ sectional view (FIG. 8A), the BB ′ sectional view (FIG. 8B), and the CC ′ sectional view (FIG. 8C) of FIG. It is sectional drawing shown.
[0107]
In the above-described first embodiment, the arrangement example of each element in the case where a dual gate type TFT is used as the TFT 30 has been described. However, in the second embodiment, a so-called triple gate having three channel regions as TFTs. A type TFT is used.
[0108]
7 and 8, the same members as those in the first embodiment are denoted by the same member numbers, and detailed description thereof is omitted.
[0109]
Furthermore, in the second embodiment, the configuration (two-dimensional arrangement as a liquid crystal panel, etc.) and operation other than the arrangement of elements in the pixel portion are the same as those in the first embodiment, and thus detailed description thereof is also omitted.
[0110]
First, as shown in FIG. 7, the TFT 30 ′ of the second embodiment includes three channel regions C 1, C 2, and C 3 (by arranging the semiconductor layer 1 so as to cross the bottom of the scanning line 3 three times. A slanted line region in the lower right in FIG. 7 is formed.
[0111]
Accordingly, in the TFT 30 ′, the drain region D, the channel regions C 1, C 2 and C 3 and the source region S are connected to each other by the semiconductor layer 1.
[0112]
The drain region D is connected to the island-shaped metal electrode 15 through the contact hole 11, and the metal electrode 15 is further connected to the pixel electrode 9 through the contact hole 8.
[0113]
At this time, in the pixel portion of the second embodiment, similarly to the first embodiment, the metal electrode 15 is moved from the portion where the contact hole 11 is formed to the center of the pixel electrode 9 with respect to the contact hole 11. The contact hole 8 is formed extending in the opposite direction (leftward in FIG. 7), and the contact hole 8 is formed on the extended metal electrode 15. In this case, the contact hole 8 is formed above the semiconductor layer 1 that connects the channel region C2 and the channel region C3.
[0114]
With this configuration, as in the first embodiment, the contact hole 8 that comes into contact with the liquid crystal is formed at a position away from the center of the pixel portion, and thus the disclination line DL in the pixel portion of the second embodiment. Is formed at a position shown by a dotted line in FIG. 7 away from the opening.
[0115]
Further, in the pixel portion of the second embodiment, as in the first embodiment, a part of the scanning line 3 in the previous stage is formed to be correspondingly extended, so that one capacitor electrode 70a constituting the storage capacitor 70 is formed. Furthermore, by forming a part of the semiconductor layer 1 to be extended, another capacitor electrode 70b constituting the storage capacitor 70 is formed.
[0116]
Next, the cross-sectional structure of each part shown in FIG. 7 will be described with reference to FIG. 8. First, regarding the AA ′ cross-sectional view in FIG. 7, as shown in FIG. 11 is connected to the pixel electrode 9 through the metal electrode 15 and the contact hole 8.
[0117]
The source region S is connected to the data line 6 through the contact hole 5.
[0118]
In FIG. 8A, the island-shaped metal electrode 15 is formed extending in the direction opposite to the center direction of the pixel portion, and the contact hole 8 is formed in the extended portion.
[0119]
In FIG. 8A, the configuration of the counter substrate 20 is the same as in the case of the first embodiment, and is not shown.
[0120]
Next, regarding the BB ′ sectional view in FIG. 7, a channel region C2 is formed in a part of the semiconductor layer 1 formed on the TFT array substrate 10, as shown in FIG. 8B. The scanning line 3 is disposed above the channel region C2 with the gate insulating film 12 interposed therebetween.
[0121]
On the other hand, the above-described metal electrode 15 is formed on the first interlayer insulating film 13 formed on the scanning line 3, and the contact hole 8 is formed in the second interlayer insulating film 14 thereon, and further, A pixel electrode 9 is formed at a position corresponding to the pixel portion on the second interlayer insulating film 14.
[0122]
In FIG. 8B, the configuration of the counter substrate 20 is the same as in the case of the first embodiment, and is not described.
[0123]
Next, regarding the CC ′ cross-sectional view in FIG. 7, as shown in FIG. 8C, a part of the semiconductor layer 1 is extended below the data line 6, and this constitutes the storage capacitor 70. Capacitance electrode 70b.
[0124]
On the other hand, a capacitor electrode 70a formed by extending the scanning line 3 in the previous stage is stacked on the capacitor electrode 70b with the gate insulating film 12 interposed therebetween.
[0125]
Then, by sandwiching the gate insulating film 12 between the capacitor electrodes 70a and 70b, a storage capacitor 70 using the gate insulating film 12 as a dielectric film is formed.
[0126]
Note that the capacitor electrode 70b extends below the preceding scanning line 3 itself, and in this part also, the storage capacitor 70 is formed by the capacitor electrode 70b and the scanning line 3 with the gate insulating film 12 interposed therebetween. ing.
[0127]
In FIG. 8C as well, the configuration of the counter substrate 20 is the same as in the case of the first embodiment, and the description is omitted.
[0128]
As described above, according to the liquid crystal panel of the second embodiment, the same effect as that of the liquid crystal panel of the first embodiment is achieved, and in addition to this, the TFT 30 ′ having one channel region is provided. Since three are formed, the drain voltage required to be applied to the drain region D in order to drive the liquid crystal layer 50 can be further reduced as compared with the case of one or two channel regions. This so-called off-current can be further reduced.
[0129]
Furthermore, even in the TFT 30 ′ having the three channel regions C 1 to C 3, the influence of the contact hole 8 on the alignment uniformity of the liquid crystal layer 50 can be reduced and the aperture ratio can be improved.
[0130]
Further, since the plurality of channel regions C1 to C3 are formed by bending and arranging the semiconductor layer 1 in a plane, the plurality of channel regions C1 to C3, the drain region S, and the source region S are close to each other. As a result, the region in the pixel portion occupied by the TFT 30 can be minimized, so that the aperture ratio in the pixel portion can be further improved.
[0131]
(III)Third embodiment
Next, a third embodiment, which is another embodiment according to the present invention, will be described with reference to FIGS.
[0132]
FIG. 9 is a plan view schematically showing a configuration of one pixel portion in the TFT array substrate on which data lines, scanning lines, pixel electrodes and the like according to the third embodiment are formed and the vicinity thereof. FIG. 9 is a schematic cross-sectional view taken along the line AA ′ in FIG. 8 (FIG. 9A), the cross-sectional view along the line BB ′ (FIG. 9B), and the cross-sectional view along the line CC ′ (FIG. 9C), respectively. It is sectional drawing shown.
[0133]
In the above-described second embodiment, the arrangement example of each element when the triple gate type TFT 30 ′ is used as the TFT 30 has been described. However, in the third embodiment, two TFTs similar to the first embodiment are used as the TFT. A dual gate type TFT having one channel region is used, and so-called data lines, scanning lines, TFTs, and contact holes (each formed of an opaque material) are used on the TFT array substrate 10. In this example, a light-shielding film is formed, and the light-shielding film is used as an element arrangement that shields a region that adversely affects image quality including the disclination line.
[0134]
9 and 10, the same members as those in the first embodiment or the second embodiment are denoted by the same member numbers, and detailed description thereof is omitted.
[0135]
Further, in the third embodiment, the configuration (two-dimensional arrangement as a liquid crystal panel, etc.) and operation other than the arrangement of elements in the pixel portion are the same as those in the first embodiment or the second embodiment. Description is omitted.
[0136]
First, as shown in FIG. 9, the TFT 30 ″ of the third embodiment extends a part of the scanning line 3 below the contact hole 8, and below the extended part and the part of the other scanning line 3. By arranging the semiconductor layer 1 so as to be disposed at a right angle so that the semiconductor layer 1 is disposed, two channel regions C1 and C2 (the hatched region on the right and downward in FIG. 9) are formed.
[0137]
Therefore, the TFT 30 ″ has a configuration in which the drain region D, the channel regions C 1 and C 2, and the source region S are connected to each other by the semiconductor layer 1.
[0138]
The drain region D is connected to the island-shaped metal electrode 15 through the contact hole 11, and the metal electrode 15 is further connected to the pixel electrode 9 through the contact hole 8.
[0139]
At this time, in the pixel portion of the third embodiment, similarly to the first embodiment or the third embodiment, the metal electrode 15 is connected to the contact hole 11 from the portion where the contact hole 11 is formed. The contact hole 8 is formed so as to extend in a direction opposite to the center of the electrode 9 (leftward in FIG. 9), and on the portion of the extended metal electrode 15. In this case, the contact hole 8 is formed above the channel region C2.
[0140]
Therefore, since the extension part of the scanning line 3 exists under the contact hole 8 of the third embodiment, as a result, the depth of the contact hole 8 is larger than that of the first embodiment or the second embodiment. Accordingly, the planar size of the contact hole 8 itself is reduced.
[0141]
With this configuration, as in the first embodiment or the second embodiment, the contact hole 8 that comes into contact with the liquid crystal is formed at a position away from the center of the pixel portion. Therefore, in the pixel portion of the third embodiment, The disclination line DL is formed at a position indicated by a dotted line in FIG. 9 away from the opening.
[0142]
In the configuration shown in FIG. 9, since the contact hole 8 can be reduced in size as described above and further formed in the leftward position in FIG. 9, the disclination line DL is further formed in the leftward position. Thus, a higher aperture ratio can be achieved.
[0143]
Furthermore, in the pixel portion of the third embodiment, as in the first embodiment or the second embodiment, a storage capacitor 70 is configured by forming a part of the preceding scanning line 3 to be extended correspondingly. One capacitor electrode 70 a is formed, and a part of the semiconductor layer 1 is extended to form another capacitor electrode 70 b constituting the storage capacitor 70.
[0144]
Next, the cross-sectional structure of each part shown in FIG. 9 will be described with reference to FIG. 10. First, regarding the AA ′ cross-sectional view in FIG. 9, as shown in FIG. 11 is connected to the pixel electrode 9 through the metal electrode 15 and the contact hole 8.
[0145]
The source region S is connected to the data line 6 through the contact hole 5.
[0146]
In FIG. 10A, an island-shaped metal electrode 15 is formed extending in the direction opposite to the center direction of the pixel portion, and a contact hole 8 is formed in the extended portion.
[0147]
Further, the TFT 30 ″ differs from the first or second embodiment in that a doped region C1 ′ doped with a low concentration is formed between the channel region C1 and the drain region D. The TFT 30 ″ of the third embodiment has a so-called LDD (Lightly Doped Drain) structure.
[0148]
In FIG. 10A, the configuration of the counter substrate 20 is the same as that in the case of the first embodiment or the second embodiment, and the description is omitted.
[0149]
Next, regarding the BB ′ cross-sectional view in FIG. 9, as shown in FIG. 10B, a channel region C <b> 1 is formed immediately below the contact hole 8, and the channel region C <b> 1 is located between the contact hole 8. In this layer, the scanning line 3 is disposed with the gate insulating film 12 interposed between the channel region C1 and the metal electrode 15 is formed.
[0150]
Further, in the same layer as the layer in which the channel region C1 is formed, a semiconductor connected to the capacitor electrode 70b constituting the storage capacitor 70 in the next pixel portion and the capacitor electrode 70b formed under the data line 6 Layer 1 is formed.
[0151]
In FIG. 10B, the configuration of the counter substrate 20 is the same as in the case of the first embodiment or the second embodiment, and is not described.
[0152]
Next, regarding the CC ′ cross-sectional view in FIG. 9, as shown in FIG. 10C, a part of the semiconductor layer 1 extends below the data line 6, and this constitutes the storage capacitor 70. Capacitance electrode 70b.
[0153]
On the other hand, a capacitor electrode 70a formed by extending the scanning line 3 in the previous stage is stacked on the capacitor electrode 70b with the gate insulating film 12 interposed therebetween.
[0154]
Then, by sandwiching the gate insulating film 12 between the capacitor electrodes 70a and 70b, a storage capacitor 70 using the gate insulating film 12 as a dielectric film is formed.
[0155]
Note that the capacitor electrode 70b extends below the preceding scanning line 3 itself, and in this part also, the storage capacitor 70 is formed by the capacitor electrode 70b and the scanning line 3 with the gate insulating film 12 interposed therebetween. ing.
[0156]
In FIG. 10C as well, the configuration of the counter substrate 20 is the same as in the case of the first embodiment or the second embodiment, and the description is omitted.
[0157]
As described above, according to the liquid crystal panel of the third embodiment, the same effect as that of the liquid crystal panel of the first embodiment or the second embodiment is achieved, and the data line, the scanning line, A light-shielding film is formed on the TFT array substrate 10 using the TFT and each contact hole, and the light-shielding film shields a region that adversely affects the image quality including the disclination line DL, and the disclination line DL further includes Since it is formed at the peripheral edge in the pixel portion, it is not necessary to form a light shielding film on the counter substrate side, and a higher aperture ratio can be achieved.
[0158]
Note that, on the TFT array substrate 10 of each of the above-described embodiments, an inspection circuit for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment may be further formed.
[0159]
Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a driving LSI mounted on a TAB (tape automated bonding substrate) is connected to the periphery of the TFT array substrate 10. You may make it connect electrically and mechanically via the anisotropic conductive film provided in the part.
[0160]
Further, for example, the TN (twisted nematic) mode, the STN (super TN) mode, and the D-STN (double- A polarizing film, a retardation film, a polarizing plate, and the like can be arranged in a predetermined direction according to an operation mode such as an STN mode or a normally white mode / normally black mode.
[0161]
Here, since the liquid crystal panel in each embodiment described above is applied to a color liquid crystal projector, three liquid crystal panels are respectively used as RGB light valves, and each panel has a dichroic for RGB color separation. Each color light separated through the mirror is incident as projection light.
[0162]
Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter.
[0163]
However, an RGB color filter may be formed on the counter substrate 20 together with the protective film in a region which is the opening R facing the pixel electrode 9. In this way, the liquid crystal panel according to each embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflection type color liquid crystal television other than the liquid crystal projector.
[0164]
Furthermore, a microlens may be formed on the counter substrate 20 so as to correspond to one pixel. In this way, a bright liquid crystal device can be realized by improving the collection efficiency of incident light.
[0165]
Furthermore, a plurality of interference layers having different refractive indexes may be deposited on the counter substrate 20 to form a dichroic filter that produces RGB colors using light interference. According to this counter substrate with a dichroic filter, a brighter color liquid crystal display device can be realized.
[0166]
Further, the TFT provided in each pixel has been described as being a polysilicon TFT, but the present invention is also effective for other types of TFT such as an amorphous silicon TFT.
[0167]
Furthermore, the present invention is also effective for so-called self-aligned TFTs and offset TFTs.
[0168]
【The invention's effect】
As described above, according to the present invention, the second contact hole that affects the driving characteristics of the electro-optic element is formed at a position away from the center of the pixel portion. The influence on the drive characteristics of the electro-optical element can be reduced.
[0169]
More specifically, since the second contact hole that affects the continuity of the alignment of the liquid crystal element is formed away from the center of the pixel portion, the influence is reduced and the aperture ratio in the pixel portion is improved. Can do.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of various elements, wirings, and the like provided in a plurality of matrix pixel portions constituting an image forming area in the first embodiment.
FIG. 2 is a plan view schematically showing a configuration of one pixel portion and its vicinity in a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like according to the first embodiment are formed.
3 is a cross-sectional view of each part of FIG. 2, (a) is a cross-sectional view schematically showing the AA ′ cross section of FIG. 2, and (b) is a schematic view of the BB ′ cross section of FIG. It is sectional drawing shown typically, (c) is sectional drawing which shows typically CC 'cross section of FIG.
FIG. 4 is a plan view showing a two-dimensional wiring layout and the like on a TFT array substrate together with peripheral circuits.
FIG. 5 is a plan view of a TFT array substrate as viewed from the side of a counter substrate together with each component formed thereon.
6 is a cross-sectional view taken along the line H-H ′ of FIG. 5 including the counter substrate.
FIG. 7 is a plan view schematically showing a configuration of one pixel portion and its vicinity in a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like according to the second embodiment are formed.
8 is a cross-sectional view of each part of FIG. 7, (a) is a cross-sectional view schematically showing the AA ′ cross section of FIG. 7, and (b) is a schematic cross-section of the BB ′ cross section of FIG. It is sectional drawing shown typically, (c) is sectional drawing which shows CC 'cross section of FIG. 7 typically.
FIG. 9 is a plan view schematically showing a configuration of one pixel portion and its vicinity in a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like according to a third embodiment are formed.
10 is a cross-sectional view of each part of FIG. 9, (a) is a cross-sectional view schematically showing the AA ′ cross section of FIG. 9, and (b) is a schematic cross-section of the BB ′ cross section of FIG. It is sectional drawing shown typically, (c) is sectional drawing which shows typically CC 'cross section of FIG.
[Explanation of symbols]
1 ... Semiconductor layer
3. Scanning line (gate electrode)
5, 8, 11 ... contact hole
6. Data line (source electrode)
9: Pixel electrode
10 ... TFT array substrate
12 ... Gate insulating film
13: First interlayer insulating film
14 ... Second interlayer insulating film
15 ... Metal electrode
20 ... Counter substrate
21 ... Counter electrode
30, 30 ', 30 "... TFT
50 ... Liquid crystal layer
52 ... Sealing material
53.
70 ... Storage capacity
71 ... Constant potential line
70a, 70b ... capacitance electrodes
101: Data line driving circuit
104: Scanning line driving circuit
108: Precharge circuit
C1, C2, C3... Channel region
C1 '... doping region
DL: Disclination line
R ... Opening
D: Drain region
S ... Source area

Claims (4)

A plurality of scanning lines arranged on the first substrate, a plurality of data lines, each scanning line and each data line connected to each other and arranged in the vicinity of the intersection of the scanning line and the data line A switching element, a pixel electrode electrically connected to the switching element, a counter electrode disposed opposite to the pixel electrode on a second substrate, and disposed between the first and second substrates A liquid crystal device having a liquid crystal,
The switching element is connected to a first electrode formed on the first insulating film through a first contact hole formed in the first insulating film disposed on the switching element,
The first electrode is connected to the pixel electrode formed on the second insulating film through a second contact hole formed in the first insulating film and the second insulating film disposed on the first electrode. Connected,
The second contact hole is disposed in the vicinity of the intersection, on the peripheral side farther from the center of the pixel electrode than the first contact hole, and a data line connected to the switching element; The liquid crystal device is disposed between the first contact hole and the first contact hole.   The liquid crystal device according to claim 1, wherein the second contact hole is formed on a flat portion of the first electrode.   3. The liquid crystal device according to claim 1, wherein the switching element is a thin film transistor element, and a drain region of the transistor element is connected to the first electrode through the first contact hole. A liquid crystal device characterized by the above.   4. The liquid crystal device according to claim 3, wherein a semiconductor layer included in the transistor element is insulated from the scanning line and intersects the scanning line a plurality of times, whereby a plurality of transistors are connected in series to form the transistor element. A liquid crystal device characterized by being made.

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