JP2000208611A - Production of semiconductor device having trench element isolating region - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfactorily embed an insulating layer in a trench element isolating region. SOLUTION: This method includes the following processes of a process for successively forming a pad layer 12, a stopper layer 14 and a resist layer R1 having a prescribed pattern on a silicon substrate 10, a process for performing the ion implantion of oxygen materials to the stopper layer 14 obliquely to the surface of the stopper layer 14 with the resist layer R1 as a mask, an etching process for etching the stopper layer 14 and the pad layer 12, a process for forming a trench by etching the silicon substrate 10, a process for forming a protecting film 90 at a terminal part 14a of the stopper layer 14 by thermal oxidation, a process for flattening an insulating layer 20 to charge the trench while forming the insulating layer 20 all the entire surface, a process for removing the stopper layer 14, and a process for forming the trench element isolating region by etching a protruding part 22 and the protective film 90.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an element isolation groove.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor elements, for example, MOS transistors, it is necessary to miniaturize a region for separating semiconductor elements. In order to achieve the miniaturization of this region, a trench element isolation technique for providing a groove (hereinafter referred to as a "trench") on a substrate between semiconductor elements and filling the trench with an insulating material to isolate the semiconductor elements from each other has been studied. Have been. An example of this technique will be described below.

FIGS. 24 to 28 are cross-sectional views schematically showing steps of forming a trench element isolation region 123 using a conventional trench element isolation technique.

First, as shown in FIG. 24, after a pad layer 112 and a stopper layer 114 are sequentially deposited on a silicon substrate 110, a resist pattern R10 having a predetermined pattern is formed on the stopper layer 114. Using the resist layer R10 as a mask, the stopper layer 114 is etched.

Then, as shown in FIG. 25, the resist layer R10 is removed by ashing, and the silicon substrate 110 is etched using the stopper layer 114 as a mask to form a trench 116. After that, the exposed surface of the silicon substrate 110 in the trench 116 is thermally oxidized to form a trench oxide film 118.

Next, an insulating layer 120 is deposited on the entire surface so as to fill the trench 116, and as shown in FIG. 26, the insulating layer 120 is planarized using the stopper layer 114 as a mask. Next, the stopper layer 114 is removed using hot phosphoric acid.

In a subsequent step, the insulating layer 120 is
A portion protruding from the level of the upper surface of the silicon substrate 110 is isotropically etched to form a trench isolation region 123 as shown in FIG.

However, when trench element isolation region 123 is formed as described above, depression 125 is formed at the upper end of insulating layer 120 as shown in FIG.

[0009] As shown in FIG. 28, the depression 125 has a steep slope of the silicon substrate 110 and the insulating layer 120 in the depression 125. If the inclination is steep, the gate electrode material remains in the recess 125 in the etching of the gate electrode material for forming the gate electrode. If the gate electrode material remains in the recess 125, a problem such as a short circuit occurs.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device having a trench element isolation region, in which an insulating layer in a trench element isolation region is satisfactorily buried.

[0011]

A method of manufacturing a semiconductor device having a trench element isolation region according to the present invention includes the following steps (a) to (k). (A) forming a pad layer on the surface of a silicon substrate;
(B) forming a stopper layer for chemical mechanical polishing on the surface of the pad layer; (c) forming a resist layer having a predetermined pattern on the surface of the stopper layer; (d) Using the resist layer as a mask, ion-implanting an oxygen-based substance into the stopper layer from a direction oblique to the surface of the stopper layer, and (e) using the resist layer as a mask to form the stopper layer and the pad layer. (F) etching the silicon substrate using the stopper layer as a mask to form an element isolation groove, and (g) thermally oxidizing a protective film at an end of the stopper layer. (H) forming an insulating layer filling the isolation trenches on the entire surface, and (i) forming the stopper layer by a chemical mechanical polishing method. And (j) removing the stopper layer; and (k) a portion of the insulating layer protruding from a surface level of a region of the silicon substrate where an element is formed. Forming the trench isolation region by etching the protection film.

The features of the present invention are mainly the following two points.

(1) First, a step (k) is performed by forming a protective film covering the side surface of the protruding portion.

By forming the protective film, in the step (k), the protective film protects the side surface of the protruding portion, so that the recess at the upper end of the insulating layer is less likely to occur. As a result of suppressing the occurrence of the depression, a defect in the transistor characteristics, for example, an inverse narrow channel effect and Hump can be prevented. Also, since the electrode material does not accumulate in the recess, the patterning of the gate electrode is performed well,
Short circuit can be prevented.

(2) Second, a protection film is formed mainly in the steps (d) and (g). That is, except that the step (d) was added, the protective film was formed without including any special steps. Therefore, according to the present invention,
A dense protective film can be easily formed.

The ion implantation of the oxygen-based substance in the step (d) is preferably performed under the following conditions from the viewpoint of forming a better protective film.

The oxygen-based material is preferably oxygen or ozone. Energy is 15 to 30 keV
And the dose is preferably 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² . The angle between the surface of the stopper layer and the traveling direction of the ions of the oxygen-based material is preferably 45 to 80 degrees.

The thermal oxidation method in the step (g) can be mainly exemplified by the following two thermal oxidation methods from the viewpoint of forming a better protective film.

(1) First, there is a method of performing thermal oxidation in the presence of steam (hereinafter referred to as "wet oxidation"). This wet oxidation has an advantage that a short processing time is sufficient because the oxidation rate is high and the oxidation can be performed at a low temperature. The temperature of the thermal oxidation in the wet oxidation is preferably 800 to 950 ° C. in view of the controllability of the film thickness.

(2) Second, a method of performing thermal oxidation in an atmosphere of oxygen or a mixed gas of oxygen and an inert gas (hereinafter referred to as "dry oxidation"). Although this dry oxidation requires oxidation at a high temperature, it has the advantage that the wet etching resistance of the buried oxide film can be improved, and depressions are less likely to occur. The temperature of the thermal oxidation in the dry oxidation is preferably 1000 to 1150 ° C. from the viewpoint of improving the wet etching resistance of the buried oxide film.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

(Structure of Device) A semiconductor device having a trench element isolation region obtained by the manufacturing method of the present invention will be described.

FIG. 23 shows a semiconductor device (hereinafter, referred to as “semiconductor device”) 100 having a trench element isolation region obtained by the manufacturing method of the present invention.

The semiconductor device 100 shown in FIG. 23 has a trench element isolation region 23, an n-type MOS element 80 and a p-type M element.
OS element 82 is included.

The trench element isolation region 23 is a region formed by filling the trench 16 provided in the silicon substrate 10 with the insulating layer 20. Trench element isolation region 23 has a role of isolating between MOS elements and defining an element region. With the trench element isolation region 23 as a boundary, a p-type retrograde well 32 is formed in one element region, and an n-type retrograde well 30 is formed in the other element region.

On the p-type retrograde well 32, n
A type MOS element 80 is formed, and a p-type MOS element 82 is formed on the n-type retrograde well 30.

The n-type MOS device 80 has a gate oxide film 28
, A gate electrode 46 and an n-type impurity diffusion layer 50.

The gate oxide film 28 in the n-type MOS device 80 is formed on the p-type retrograde well 32. On this gate oxide film 28, a gate electrode 46 is formed. The gate electrode 46 includes a polycrystalline silicon layer 40 and a metal silicide layer 42 formed on the polycrystalline silicon layer 40. Then, a sidewall insulating film 70 is formed so as to cover the gate oxide film 28 and the sidewall of the gate electrode 46.

The n-type impurity diffusion layer 50 constitutes a source / drain region. Then, the n-type impurity diffusion layer 50
Comprises an LDD structure having a low concentration n-type impurity diffusion layer 50a and a high concentration n-type impurity diffusion layer 50b.

The p-type MOS element 82 is formed on the gate oxide film 28
, A gate electrode 46 and a p-type impurity diffusion layer 60.

The gate oxide film 28 in the p-type MOS element 82 is formed on the n-type retrograde well 30. Gate electrode 46 and sidewall insulating film 70
Are the same as those of the n-type MOS element 80.

The p-type impurity diffusion layer 60 is the same as the n-type impurity diffusion layer 50 except that it is p-type.

(Manufacturing Process) Next, a manufacturing process of the semiconductor device 100 shown in FIG. 23 will be described. Figure 1
FIG. 22 shows a manufacturing process of the semiconductor device 100.

(1) Formation of Trench and Protective Film First, description will be made with reference to FIG. Silicon substrate 10
The pad layer 12 is formed thereon. The material of the pad layer 12 can be, for example, SiO ₂ , SiON, or the like. When the pad layer 12 is made of SiO ₂ , it can be formed by a thermal oxidation method, a CVD method, or the like.
When N is used, it can be formed by a CVD method or the like. The thickness of the pad layer 12 is, for example, 5 to 20 n.
m.

Next, the stopper layer 1 is formed on the pad layer 12.
4 is formed. Examples of the stopper layer 14 include a silicon nitride layer, a multilayer structure of a silicon nitride layer and a polycrystalline silicon layer or an amorphous silicon layer, and a known method such as CVD.
And the like. The stopper layer 14 has a thickness enough to function as a stopper in the subsequent CMP, for example, a thickness of 50 to 150 nm.

On the stopper layer 14, a resist pattern R1 having a predetermined pattern is formed. The resist layer R1 is opened above a region where the trench 16 is to be formed.

Next, as shown in FIG.
Is used as a mask, an oxygen-based substance is ion-implanted into the stopper layer 14 from an oblique direction with respect to the exposed surface of the stopper layer 14. By this ion implantation, an oxygen-based substance is implanted not only into the stopper layer 14 at the opening of the resist layer R1 but also into the region of the stopper layer 14 below the resist layer R1. Oxygen-based substances include oxygen and ozone. Regarding the conditions of ion implantation, the energy is preferably 15 to 30 keV, more preferably 20 to 25 kV.
eV, and the dose is preferably 5 × 10 ^{14 to} 5 × 1.
0 ¹⁵ cm ^-2 , more preferably 1 × 10 ¹⁵ to 2 × 10 ¹⁵ c
m- ² . The angle between the exposed surface of the stopper layer and the traveling direction of the ions of the oxygen-based material is preferably 45 to 80 degrees, more preferably 50 to 70 degrees.

Next, as shown in FIG.
Is used as a mask, the stopper layer 14 and the pad layer 12 are etched. This etching is performed by, for example, dry etching. In the case of dry etching, the etchant may be, for example, a mixed gas of Cl ₂ and O ₂ .

The end 14a of the stopper layer 14 has
An oxygen-based substance is ion-implanted.

Next, the resist layer R1 is removed by ashing. Next, as shown in FIG.
Is used as a mask to etch the silicon substrate 10 to form a trench 16. The depth of the trench 16 varies depending on the device design, but is, for example, 300 to 500 nm. The etching of the silicon substrate 10 can be performed by dry etching.

Although not shown, the end of the pad layer 12 interposed between the silicon substrate 10 and the stopper layer 14 is etched.

Next, as shown in FIG. 5, the exposed surface of the silicon substrate 10 in the trench 16 is oxidized by a thermal oxidation method to form an oxide film (hereinafter referred to as "trench oxide film") 18.
To form

In this thermal oxidation, oxygen caused by the ion-implanted oxygen-based material is removed from the end 14 of the stopper layer 14.
a is promoted, and thus a protective film 90 is formed.

Further, since the edge of the pad layer 12 is etched, the upper edge of the silicon substrate 10 forming the trench 16 is formed by the thermal oxidation.
Oxidized and rounded. Since the upper edge portion of the silicon substrate 10 is rounded, a depression at an upper end portion of the insulating layer 20 described later is less likely to occur. The method of this thermal oxidation is not particularly limited, and wet oxidation (a method of thermal oxidation in the presence of steam) and dry oxidation (a method of thermal oxidation in an atmosphere of oxygen or a mixed gas of oxygen and an inert gas) are available. preferable. Wet oxidation has the advantage of requiring a short processing time because the oxidation rate is high and oxidation at low temperatures is possible. Dry oxidation requires oxidation at a high temperature, but has the advantage that the wet etching resistance of the trench oxide film (buried oxide film) 18 can be improved, and depressions are less likely to occur. The temperature of the thermal oxidation in wet oxidation is preferably from 800 to 950 ° C., more preferably from 900 to 950 ° C., from the viewpoint of controllability of the film thickness. The temperature of the thermal oxidation in the dry oxidation is set at 100 from the viewpoint of improving the wet etching resistance of the trench oxide film (buried oxide film) 18.
The temperature is preferably from 0 to 1150 ° C, more preferably from 1100 to 1150 ° C. Examples of the inert gas in the dry oxidation include helium, neon, argon, and krypton.

As shown in FIG. 6, an insulating layer 20 is deposited on the entire surface so as to fill the trench 16. Insulating layer 2
The film thickness of 0 is a film thickness that fills the trench 16 and covers at least the stopper layer 14, for example, 500 to 800.
nm. The material of the insulating layer 20 is made of, for example, silicon oxide. As a method of depositing the insulating layer 20, for example, high-density plasma CVD, thermal CVD, TEOS
A plasma CVD method or the like can be given.

Next, as shown in FIG.
Flatten by the MP method. This flattening is performed by the stopper layer 1.
Repeat until 4 is exposed. That is, the insulating layer 20 is planarized using the stopper layer 14 as a stopper. Next, as shown in FIG. 8, the stopper layer 14 is removed using, for example, a hot phosphoric acid solution.

Next, as shown in FIG. 9, the protrusion 22 and the protective film 90 are isotropically etched. During this etching, the side surfaces of the protruding portions 22 are protected by the protective film 90, so that the lateral etching is suppressed. As a result, depressions are less likely to occur at the upper end of the insulating layer 20. Therefore, a trench element isolation region 23 in which the insulating layer is satisfactorily embedded is formed. Examples of the etchant include an etchant containing hydrofluoric acid. During this etching, the pad layer 12 is also etched away.

(2) Formation of Well Next, as shown in FIG. 10, a sacrificial oxide film 24 is formed on the exposed surface of the silicon substrate 10 by a thermal oxidation method. The thickness of the sacrificial oxide film 24 is, for example, 10 to 20 nm.

Subsequently, the sacrificial oxide film 24 and the trench 1
A resist layer R2 having a predetermined pattern is formed on the surface of the insulating layer 20 that fills the insulating layer 6. The resist layer R2 has n
The opening is formed so that the surface of the region to be the well is exposed. Using the resist layer R2 as a mask, an n-type retrograde well 30 is formed in the silicon substrate 10 by injecting n-type impurities such as phosphorus and arsenic into the silicon substrate 10 one or more times. The retrograde well refers to a well having a peak of the impurity concentration of the well at a deep position in the silicon substrate 10.

As shown in FIG. 11, a resist layer R3 is formed on the surface of the insulating layer 20 filling the sacrificial oxide film 24 and the trench 16. The resist layer R3 is opened so that the surface of the region to be a p-well is exposed. By using the resist layer R3 as a mask, a p-type impurity such as boron is implanted into the silicon substrate 10 one or more times to form a p-type retrograde well 32 in the silicon substrate 10.

Next, as shown in FIG.
4 is isotropically etched. At this time, the protrusion 2
2 and the protective film 90 still remain, the protrusion 22 and the protective film 90 are also isotropically etched. Examples of the etchant include an etchant containing hydrofluoric acid.

(3) Formation of Gate Electrode Next, as shown in FIG.
An oxide film 26 is formed on the element region defined by 3. A part of the oxide film 26 becomes a gate oxide film 28.

As shown in FIG. 14, a polycrystalline silicon layer 40 is formed on insulating layer 20 and oxide film 26 by a CVD method or the like. The polycrystalline silicon layer 40 is doped.

On the surface of the polycrystalline silicon layer 40, a metal silicide layer 42 is formed. Examples of the material of the metal silicide layer 42 include silicide such as tungsten, titanium, and molybdenum, and examples of the method for forming the silicide layer 42 include a stampering method.

Thereafter, a silicon oxide layer 44 is formed on the surface of the metal silicide layer 42. As a method for forming the silicon oxide layer 44, for example, a CVD method or the like can be given.

As shown in FIG. 15, the silicon oxide layer 44
A resist layer R4 is formed so as to cover a region where the gate electrode 46 is to be formed. Next, the silicon oxide layer 44 is etched using the resist layer R4 as a mask.

Thereafter, as shown in FIG. 16, the resist layer R4 is removed by ashing.

Next, as shown in FIG. 17, using the silicon oxide layer 44 as a mask, the metal silicide layer 42 and the polycrystalline silicon layer 40 are etched. Thus, a gate electrode 46 composed of the polycrystalline silicon layer 40 and the metal silicide layer 42 is formed.

(4) Formation of Source / Drain As shown in FIG. 18, a resist layer R5 covering the n-type retrograde well 30 is formed. Using the resist layer R5 as a mask, phosphorus or the like is ion-implanted into the p-type retrograde well 32 to form the p-type retrograde well 32.
A low-concentration n-type impurity diffusion layer 50a forming source / drain regions is formed therein.

After removing the resist layer R5, a resist layer R6 covering the p-type retrograde well 32 is formed as shown in FIG. Using the resist layer R6 as a mask, boron or the like is ion-implanted into the n-type retrograde well 30, and the low-concentration p-type impurity diffusion layer 60a constituting the source / drain region is formed in the n-type retrograde well 30. Form.

Next, after removing the resist layer R6, the CV
An insulating layer (not shown), for example, a silicon nitride film, a silicon oxide film, or the like is formed on the entire surface by the D method or the like.
Next, as shown in FIG. 20, the insulating layer is anisotropically etched by reactive ion etching or the like to form a sidewall insulating film 70.

Next, as shown in FIG. 21, a resist layer R7 covering the n-type retrograde well 30 is formed. Using the resist layer R7, the gate electrode 46, and the sidewall insulating film 70 as a mask, an impurity such as phosphorus is
Ions are implanted into the p-type retrograde well 32 to form a high-concentration n-type impurity diffusion layer 50b. This allows
An n-type impurity diffusion layer 50 having an LDD structure is formed.

Next, after removing the resist layer R7, FIG.
As shown in FIG. 2, a resist layer R8 covering the p-type retrograde well 32 is formed. Using the resist layer R8, the gate electrode 46, and the sidewall insulating film 70 as a mask, an impurity such as boron is ion-implanted into the n-type retrograde well 30 to form a high-concentration p-type impurity diffusion layer 60b. I do. Thereby, the p-type impurity diffusion layer 60 having the LDD structure is formed.

Next, the semiconductor device 100 according to the present embodiment as shown in FIG. 23 is completed by removing the resist layer R8 by ashing.

The present embodiment is characterized mainly by the following two points.

(1) First, a protection film 90 for covering the side surfaces of the protrusion 22 is formed, and the protrusion 22 is isotropically etched.

By forming the protective film 90, the protrusion 22
In the step of isotropically etching, the protective film 90 protects the side surface of the protruding portion 22, so that the upper end portion of the insulating layer 20 is less likely to be recessed. As a result of suppressing the occurrence of depressions, defects in transistor characteristics, such as an inverse narrow channel effect and a hump (Hump)
Can be prevented. In addition, for example, when forming a gate electrode, it is possible to suppress a problem such as accumulation of an electrode material at an upper end portion of the insulating layer 20, so that a short circuit is less likely to occur.

(2) Second, mainly, the stopper layer 14
The step of implanting an oxygen-based material obliquely with respect to the exposed surface of the stopper layer 14 and the step of thermally oxidizing the exposed surface of the silicon substrate 10 in the trench 16 include the steps of:
Is formed. That is, the protective film 90 is formed without including a special process except that a process of implanting an oxygen-based material into the stopper layer 14 is added. Therefore, according to the method of the present embodiment, the dense protective film 90 can be easily formed.

The above embodiment can be variously modified without departing from the gist of the present invention.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to an embodiment.

FIG. 2 is a cross-sectional view schematically showing steps of a method of manufacturing the semiconductor device according to the embodiment.

FIG. 3 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 4 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 5 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 6 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 7 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 8 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 9 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 10 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 11 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 12 is a cross-sectional view schematically showing a step of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 13 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 14 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 15 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 16 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 17 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 18 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 19 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 20 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 21 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 22 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 23 is a cross-sectional view schematically showing a semiconductor device according to an embodiment.

FIG. 24 is a cross-sectional view schematically showing steps of a method of manufacturing a semiconductor device according to a conventional example.

FIG. 25 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 26 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 27 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 28 is an enlarged schematic cross-sectional view of the depression in FIG. 27;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Silicon substrate 12 Pad layer 14 Stopper layer 16 Trench 18 Trench oxide film 20 Insulating layer 22 Projection 23 Trench element isolation region 24 Sacrificial oxide film 26 Oxide film 28 Gate oxide film 30 n-type retrograde well 32 p-type retrograde Well 40 polycrystalline silicon layer 42 metal silicide layer 44 silicon oxide layer 46 gate electrode 50 n-type impurity diffusion layer 50a low concentration n-type impurity diffusion layer 50b high concentration n-type impurity diffusion layer 60 p-type impurity diffusion layer 60a low concentration P-type impurity diffusion layer 60b high-concentration p-type impurity diffusion layer 70 sidewall insulating film 80 n-type MOS element 82 p-type MOS element 90 protective film 100 semiconductor device

Continued on the front page F term (reference) 5F032 AA35 AA36 AA44 AA45 CA03 CA17 CA20 DA02 DA04 DA23 DA24 DA25 DA26 DA30 DA33 DA43 DA53 DA60 DA77 DA78 5F048 AA04 AA07 AC03 BB05 BB08 BB12 BC06 BE03 BG14 DA25 DA27

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor device having a trench isolation region including the following steps (a) to (k). (A) forming a pad layer on the surface of a silicon substrate;
(B) forming a stopper layer for chemical mechanical polishing on the surface of the pad layer; (c) forming a resist layer having a predetermined pattern on the surface of the stopper layer; (d) Using the resist layer as a mask, ion-implanting an oxygen-based substance into the stopper layer from a direction oblique to the surface of the stopper layer, and (e) using the resist layer as a mask to form the stopper layer and the pad layer. (F) etching the silicon substrate using the stopper layer as a mask to form an element isolation groove, and (g) protecting the protective film at the end of the stopper layer by thermal oxidation. (H) a step of forming an insulating layer filling the device isolation trench over the entire surface, and (i) forming the stopper layer by a chemical mechanical polishing method. And (j) removing the stopper layer; and (k) a portion of the insulating layer protruding from a surface level of a region of the silicon substrate where an element is formed. Forming a trench isolation region by etching the protection film. 2. The method according to claim 1, wherein the oxygen-based material in the step (d) is oxygen or ozone. 3. The ion implantation condition according to claim 1, wherein the conditions of the ion implantation in the step (d) are as follows: an energy of 15 to 30 keV and a dose of 5 × 10 ^{14 to} 5
A method for manufacturing a semiconductor device having a trench element isolation region of × 10 ¹⁵ cm ⁻² . 4. The method according to claim 1, wherein the angle between the surface of the stopper layer and the traveling direction of the ions of the oxygen-based substance in the step (d) is 45 to 8.
A method for manufacturing a semiconductor device having a trench element isolation region at 0 degrees. 5. The trench element isolation region according to claim 1, wherein the method of thermally oxidizing the stopper layer in the step (g) is a method of thermally oxidizing in the presence of water vapor. A method for manufacturing a semiconductor device having: 6. The method according to claim 5, wherein the temperature of the thermal oxidation in the step (g) is 800 to 95.
A method for manufacturing a semiconductor device having a trench element isolation region at 0 ° C. 7. The method according to claim 1, wherein the method of thermally oxidizing the stopper layer in the step (g) is performed in an atmosphere of oxygen or a mixed gas of oxygen and an inert gas. A method of manufacturing a semiconductor device having a trench element isolation region, which is an oxidizing method. 8. The method according to claim 7, wherein the temperature of the thermal oxidation in the step (g) is 1000 to 1
A method for manufacturing a semiconductor device having a trench element isolation region at 150 ° C.