JP2000207274A - Unit and method for readout control over common memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the frequency of data read from a common memory and consequently to shorten the time needed to read the data out. SOLUTION: A latch 6 which temporarily holds data read out of the common memory 2 is provided between a processor 1 and the common memory 2. The processor 1 is equipped with a readout signal generating means 11, which generates readout signal one time more than the number of data read out of the common memory 2 and an address operating means 12, which ignores the data read out corresponding to the 1st readout signal among data transferred from the latch 6 and makes the data transferred from the latch 6, corresponding to the 2nd and succeeding readout signal correspond to the addresses at the time of the generation of last readout signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read control device and a read control method for a shared memory having a latch between a processor and the shared memory for temporarily holding data read from the shared memory.

[0002]

2. Description of the Related Art Generally, when memory resources are shared by a plurality of processors (microprocessors), it is necessary to arbitrate a bus between a shared memory, which is a shared memory resource, and a processor (Japanese Unexamined Patent Application Publication No. Hei. No. 133142). Although some processors have a bus arbitration function, when a processor that does not have a bus arbitration terminal (READY terminal) is used to share memory resources, for example, as shown in FIG. A bus arbitration circuit 3 between the microprocessor 1 and the shared memory 2
It is necessary to provide.

The bus arbitration circuit 3 shown in FIG.
Is passed through control circuit 4 and delay circuit 5 to provide read signal RDb to shared memory 2 and latch 6 temporarily holds data read from shared memory 2 in response to read signal RDb. The output end of the latch 6 is connected to the processor 1 via a buffer 7 which is a three-state buffer. The buffer 7 outputs the data held in the latch 7 when the processor 1 outputs the read signal RDa. 1 handover. When receiving a busy signal BUSY output while shared memory 2 is being accessed by another processor 1 ′, control circuit 4 does not supply a read signal to latch 6 and delay circuit 5. The busy signal BUSY from the shared memory 2 is also supplied to the processor 1, and the processor 1 stops generating the read signal while receiving the busy signal BUSY. In FIG. 4, the code with an apostrophe indicates that the shared memory 2 is the processor 1 ', and is the same as the code without the apostrophe.

In the configuration shown in FIG. 4, the data read from the shared memory 2 is held in the latch 6, and the data held in the latch 6 is transferred to the processor 1 through the buffer 7 and then read out by the delay circuit 5. RDb is supplied to the shared memory 2, and data read from the shared memory 2 is held in the latch 6. That is, when data is read from the shared memory 2 and transferred to the processor 1, the data at the address specified when the processor 1 generates the read signal RDa is not transferred to the processor 1 when the read signal RDa is generated. It is held by the latch 6. In other words, the data corresponding to the address specified when the read signal RDa is generated is not delivered to the processor 1 unless the read signal RDa is generated again.

Therefore, when the above-described bus arbitration circuit 3 is provided, the data read from the shared memory 2 is transferred to the processor 1 according to the procedure shown in FIG. That is, if the busy signal BUSY is not output from the shared memory 2 (S1), the processor 1 performs an operation of generating the read signal RDa and transferring data from the shared memory 2 to the latch 6 (S2). At this time, the data transferred from the latch 6 to the processor 1 through the buffer 7 does not correspond to the address specified by the processor 1, and is ignored by the processor 1. At this time, if the busy signal BUSY is not output from the shared memory 2 (S3), the processor 1 generates the read signal RDa again and transfers the data from the shared memory 2 to the latch 6 (S4). However, in step S4, the same address as in step S2 is specified. In this case, the data input from the latch 6 to the processor 1 through the buffer 7 corresponds to the address specified by the processor 1.

Thereafter, the processor 1 increases the address for reading data from the shared memory 2 by 1 (S
5) The above operation is repeated until a required number of data is read from the shared memory 2. The figure shows an example in which data of a plurality of consecutive addresses is transferred from the shared memory 2 to the processor 1, and the value obtained by adding 1 to the address set in step S5 adds 1 to the final value of the address to be specified. If the value has reached (S6), the reading of data from the shared memory 2 ends.

For example, when reading data at addresses 100 to 109, the operation is as shown in Table 1.

[0008]

[Table 1]

[0009]

As described above, if the shared memory 2 is accessed according to the procedure shown in FIG. 5, the processor 1 generates the read signal RDa twice each time one data is read from the shared memory 2. Compared to the case of accessing and reading a normal memory.
Double access is required. In addition, since the BUSY signal is generated from the shared memory 2, the frequency of interruption of reading by the BUSY signal increases as the number of accesses doubles, resulting in the time required to read data from the shared memory 2. Very large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce the frequency of access when reading data from a shared memory, thereby reducing the time required for reading data. Another object of the present invention is to provide a read control device and a read control method for a shared memory which are also shortened.

[0011]

According to the first aspect of the present invention, a latch for temporarily holding data read from a shared memory is provided between the processor and the shared memory, and the latch is provided when a read signal is output from the processor. A bus arbitration circuit for reading the data at the address specified by the processor from the shared memory together with the read signal and holding the data in the latch after the data held in the shared memory is input to the processor; A read signal generating means for generating the read signal many times, and ignoring data read in response to the first read signal of the data transferred from the latch, and outputting data from the latch in response to the second and subsequent read signals. Address processing means for associating the transferred data with the address at which the previous read signal was generated. But on the service. According to this configuration, the number of data to be read from the shared memory is one more than the number of data to be read.
Since it is only necessary to generate the read signal extra times, there is no significant increase in the time required for reading as compared with the normal access to the memory.

According to a second aspect of the present invention, in the first aspect of the present invention, when the bus arbitration circuit receives a busy signal output from the shared memory while the shared memory is being accessed by another processor, the bus arbitration circuit reads out from the processor. No signal is provided to the shared memory and latch. According to this configuration, when a busy signal is generated from the shared memory, access to the shared memory is stopped, so that contention between a plurality of processors sharing the shared memory as a memory resource can be arbitrated. As described above, even when the contention arbitration is performed, since the number of accesses when reading necessary data from the shared memory is relatively small, the frequency of generating a busy signal during access is low, and the time required for reading is greatly increased. Absent.

According to a third aspect of the present invention, a latch for temporarily holding data read from the shared memory is provided between the processor and the shared memory, and when a read signal is output from the processor, the data held in the latch is transferred. In a shared memory read control method in which data at an address specified by the processor is read from the shared memory together with the read signal after input to the processor and held in a latch, a read signal is generated once more than the number of data read from the shared memory. And ignores the data read from the latch corresponding to the first read signal out of the data transferred from the latch and sets the data transferred from the latch one time earlier in response to the second and subsequent read signals. Is associated with the address when the read signal is generated. According to this method, a read signal needs to be generated only once more than the number of data to be read from the shared memory, so that the time required for reading does not greatly increase as compared with access to a normal memory. .

According to a fourth aspect of the present invention, in the third aspect of the present invention, input / output of data to / from the latch is stopped while the shared memory is accessed by another processor and a busy signal is generated from the shared memory. Things. According to this method, when a busy signal is generated from the shared memory,
Since access to the shared memory is stopped, contention between a plurality of processors sharing the shared memory as a memory resource can be arbitrated. As described above, even when the contention arbitration is performed, since the number of accesses when reading necessary data from the shared memory is relatively small, the frequency of generating a busy signal during access is low, and the time required for reading is greatly increased. Absent.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) In this embodiment, as shown in FIG. 1, a configuration similar to a conventional configuration having a bus arbitration circuit 3 between a processor 1 and a shared memory 2 is shown. The configuration and operation of the bus arbitration circuit 3 are the same as those of the conventional configuration shown in FIG. However, in the present embodiment, the processor (microprocessor) 1
The read signal generating means 11 generates a read signal once more than the number of data read from the shared memory 2, and the read signal corresponding to the first read signal out of the data transferred from the latch 6. Address operation means 12 for ignoring the data and associating the data transferred from the latch 6 with the address at the time of generating the previous read signal in response to the second and subsequent read signals is provided.

The read signal RD from the processor 1
a is output, the buffer 7 transfers the data held in the latch 6 to the processor 1, and the read signal RDa
Are inverted in the control circuit 4 as shown in FIG.
The output of the control circuit 4 is delayed by a predetermined time T1 in the delay circuit 5 as shown in FIG. Shared memory 2
FIG. 2A shows that the output of the delay circuit 5 is at the L level.
And outputs the data of the designated address from the processor 1 through the address bus ADD to the data bus DAT. Here, the latch 6 holds the data sent to the data bus DAT at the rise of the output of the control circuit 4 indicated by the arrow in FIG. That is, since the delay circuit 5 is provided, the data bus DA
The data can be held in the latch 6 during the period when the data is reliably output to T.

However, in the present embodiment, as shown in FIG. 3, if the busy signal BUSY is not output from the shared memory 2 (S1), the processor 1 sends the read signal RDa
Is performed to transfer data from the shared memory 2 to the latch 6 (S2). At this time, the data transferred from the latch 6 to the processor 1 through the buffer 7 does not correspond to the address specified by the processor 1.
Only data passed from the latch 6 to the processor 1 corresponding to a is ignored, and other data is taken into the processor 1 as valid data. Thereafter, the processor 1 increases the address for reading data from the shared memory 2 by 1 (S3), and repeats the above operation until a required number of data are read from the shared memory 2. The figure shows an example in which data of a plurality of consecutive addresses is transferred from the shared memory 2 to the processor 1, and the value obtained by adding 1 to the address set in step S3 adds 2 to the final value of the address to be specified. If the value is (S
4) The data reading from the shared memory 2 ends. In short, the processor 1 uses the read signal generation means 11 to increase the read signal R by one more than the required number of data.
Da is generated.

The data acquired by the procedure shown in FIG.
Address 1 for the address specified by processor 1
Since the data corresponds to a smaller address each time, a process of associating each data input through the buffer 7 with an address obtained by subtracting 1 from the address specified when the data is read out is performed by the address operating means 12 in the processor 1. Do. By this processing, the data is associated with the address.

For example, when reading data at addresses 100 to 109, the operation is as shown in Table 2.

[0020]

[Table 2]

As is apparent from Table 2, if the number of accesses is one more than the number of data continuously read from the shared memory 2, the required number of data can be read, and the time required for reading the data can be reduced. This is significantly shorter than the conventional configuration.

[0022]

According to the first aspect of the present invention, a latch for temporarily holding data read from the shared memory is provided between the processor and the shared memory, and the latch is held in the latch when a read signal is output from the processor. A bus arbitration circuit for reading data at an address designated by the processor from the shared memory together with the read signal after the data is input to the processor and holding the data in a latch; and generating a read signal once more than the number of data read from the shared memory. Read signal generating means and one of data transferred from the latch
The data read from the latch in response to the second read signal is ignored, and the data transferred from the latch in response to the second and subsequent read signals is stored in the address at which the previous read signal was generated. An address operating means to be associated is provided in the processor. According to this configuration, it is only necessary to generate a read signal once more than the number of data to be read from the shared memory. Therefore, there is no significant increase in the time required for reading as compared with a normal memory access. .

According to a second aspect of the present invention, in the first aspect of the present invention, when the bus arbitration circuit receives a busy signal output from the shared memory while the shared memory is being accessed by another processor, the bus arbitration circuit reads out from the processor. No signal is provided to the shared memory and latch. According to this configuration, when a busy signal is generated from the shared memory, access to the shared memory is stopped, so that contention between a plurality of processors sharing the shared memory as a memory resource can be arbitrated. As described above, even when the contention arbitration is performed, since the number of accesses when reading necessary data from the shared memory is relatively small, the frequency of generating a busy signal during access is low, and the time required for reading is greatly increased. Absent.

According to a third aspect of the present invention, a latch for temporarily holding data read from the shared memory is provided between the processor and the shared memory, and when a read signal is output from the processor, the data held in the latch is transferred. In a shared memory read control method in which data at an address specified by the processor is read from the shared memory together with the read signal after input to the processor and held in a latch, a read signal is generated once more than the number of data read from the shared memory. And ignores the data read from the latch corresponding to the first read signal out of the data transferred from the latch and sets the data transferred from the latch one time earlier in response to the second and subsequent read signals. Is associated with the address when the read signal is generated. According to this method, a read signal needs to be generated only once more than the number of data to be read from the shared memory, so that the time required for reading does not greatly increase as compared with access to a normal memory. .

According to a fourth aspect of the present invention, in the third aspect of the present invention, input / output of data to / from the latch is stopped while the shared memory is read by another processor and a busy signal is generated from the shared memory. Things. According to this method, when a busy signal is generated from the shared memory, reading to the shared memory is stopped, so that contention between a plurality of processors sharing the shared memory as a memory resource can be arbitrated. As described above, even when performing contention arbitration, since the number of times of reading required data from the shared memory is relatively small, the frequency of generation of a busy signal during reading is small, and the time required for reading is greatly increased. Absent.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an operation explanatory view of the above.

FIG. 3 is an operation explanatory view of the above.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is an operation explanatory view of the above.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor 2 Shared memory 3 Bus arbitration circuit 4 Control circuit 5 Delay circuit 6 Latch 7 Buffer 11 Read signal generation means 12 Address operation means

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[Procedure amendment]

[Submission Date] January 11, 2000 (2000.1.1)
1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 2

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0003

[Correction method] Change

[Correction contents]

The bus arbitration circuit 3 shown in FIG.
Is passed through control circuit 4 and delay circuit 5 to provide read signal RDb to shared memory 2 and latch 6 temporarily holds data read from shared memory 2 in response to read signal RDb. The output end of the latch 6 is connected to the processor 1 via a buffer 7 which is a three-state buffer. The buffer 7 outputs the data held in the latch 7 when the processor 1 outputs the read signal RDa. 1 handover. The control circuit 4 prevents the read signal from being supplied to the latch 6 and the delay circuit 5 while receiving the busy signal BUSY output when the shared memory 2 is being accessed by another processor 1 '. The busy signal BUSY from the shared memory 2 is also supplied to the processor 1, and the processor 1 stops generating the read signal while receiving the busy signal BUSY. In FIG. 4, the code with an apostrophe indicates that the shared memory 2 is the processor 1 ', and is the same as the code without the apostrophe.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

According to a second aspect of the present invention, in the first aspect of the present invention, the bus arbitration circuit receives the busy signal output from the shared memory when the shared memory is being accessed by another processor. Is not supplied to the shared memory and the latch. According to this configuration, the busy signal is generated from the shared memory.
During this time , access to the shared memory is stopped, so that contention between a plurality of processors sharing the shared memory as a memory resource can be arbitrated. As described above, even when the contention arbitration is performed, since the number of accesses when reading necessary data from the shared memory is relatively small, the frequency of generating a busy signal during access is low, and the time required for reading is greatly increased. Absent.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction contents]

According to a fourth aspect of the present invention, in the third aspect of the present invention, input / output of data to / from the latch is stopped while the shared memory is accessed by another processor and a busy signal is generated from the shared memory. Things. According to this method, a busy signal is generated from the shared memory .
During the period , access to the shared memory is stopped, so that contention between a plurality of processors sharing the shared memory as a memory resource can be arbitrated. As described above, even when the contention arbitration is performed, since the number of accesses when reading necessary data from the shared memory is relatively small, the frequency of generating a busy signal during access is low, and the time required for reading is greatly increased. Absent.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0023

[Correction method] Change

[Correction contents]

According to a second aspect of the present invention, in the first aspect of the present invention, the bus arbitration circuit receives the busy signal output from the shared memory when the shared memory is being accessed by another processor. Is not supplied to the shared memory and the latch. According to this configuration, the busy signal is generated from the shared memory.
During this time , access to the shared memory is stopped, so that contention between a plurality of processors sharing the shared memory as a memory resource can be arbitrated. As described above, even when the contention arbitration is performed, since the number of accesses when reading necessary data from the shared memory is relatively small, the frequency of generating a busy signal during access is low, and the time required for reading is greatly increased. Absent.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0025

[Correction method] Change

[Correction contents]

According to a fourth aspect of the present invention, in the third aspect of the present invention, input / output of data to / from the latch is stopped while the shared memory is read by another processor and a busy signal is generated from the shared memory. Things. According to this method, the period during which the busy signal is generated from the shared memory
In this case, since reading to the shared memory is stopped, contention between a plurality of processors sharing the shared memory as a memory resource can be arbitrated. As described above, even when performing contention arbitration, since the number of times of reading required data from the shared memory is relatively small, the frequency of generation of a busy signal during reading is small, and the time required for reading is greatly increased. Absent.

Claims (4)

[Claims] A latch for temporarily holding data read from a shared memory is provided between a processor and a shared memory, and when a read signal is output from the processor, after the data held in the latch is input to the processor. A bus arbitration circuit for reading data at an address specified by the processor together with the read signal from the shared memory and holding the data in a latch; a read signal generating means for generating a read signal once more than the number of data read from the shared memory; Out of the data transferred from the first read signal, and ignores the data transferred from the latch corresponding to the second and subsequent read signals by the immediately preceding read signal. Address processing means for associating with the address at the time when the address is generated is provided in the processor. Mori's readout controller 2. The bus arbitration circuit does not apply a read signal from a processor to a shared memory and a latch when receiving a busy signal output from the shared memory while the shared memory is being accessed by another processor. 2. The read control device for a shared memory according to claim 1, wherein 3. A latch for temporarily holding data read from the shared memory is provided between the processor and the shared memory, and when a read signal is output from the processor, after the data held in the latch is input to the processor. In a read control method for a shared memory in which data at an address specified by a processor is read from a shared memory together with the read signal and held in a latch, a read signal is generated once more than the number of data to be read from the shared memory and transferred from the latch. Of the read data, the data read in response to the first read signal is ignored, and the data transferred from the latch in response to the second and subsequent read signals is set to 1
A read control method for a shared memory, wherein the read control signal is associated with an address when a previous read signal is generated. 4. The shared memory according to claim 3, wherein input / output of data to / from the latch is stopped while the shared memory is being accessed by another processor and a busy signal is being generated from the shared memory. Read control method.