JP2000194556A5 - - Google Patents

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Publication number
JP2000194556A5
JP2000194556A5 JP1999365694A JP36569499A JP2000194556A5 JP 2000194556 A5 JP2000194556 A5 JP 2000194556A5 JP 1999365694 A JP1999365694 A JP 1999365694A JP 36569499 A JP36569499 A JP 36569499A JP 2000194556 A5 JP2000194556 A5 JP 2000194556A5
Authority
JP
Japan
Prior art keywords
counter
instruction
value
look
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999365694A
Other languages
English (en)
Japanese (ja)
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JP2000194556A (ja
Filing date
Publication date
Priority claimed from US09/221,187 external-priority patent/US6311266B1/en
Application filed filed Critical
Publication of JP2000194556A publication Critical patent/JP2000194556A/ja
Publication of JP2000194556A5 publication Critical patent/JP2000194556A5/ja
Pending legal-status Critical Current

Links

JP11365694A 1998-12-23 1999-12-22 命令ルックアヘッドシステムおよびハ―ドウェア Pending JP2000194556A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/221,187 US6311266B1 (en) 1998-12-23 1998-12-23 Instruction look-ahead system and hardware
US09/221.187 1998-12-23

Publications (2)

Publication Number Publication Date
JP2000194556A JP2000194556A (ja) 2000-07-14
JP2000194556A5 true JP2000194556A5 (enExample) 2007-02-15

Family

ID=22826734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11365694A Pending JP2000194556A (ja) 1998-12-23 1999-12-22 命令ルックアヘッドシステムおよびハ―ドウェア

Country Status (3)

Country Link
US (1) US6311266B1 (enExample)
EP (1) EP1014261A1 (enExample)
JP (1) JP2000194556A (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2447907B (en) * 2007-03-26 2009-02-18 Imagination Tech Ltd Processing long-latency instructions in a pipelined processor
US7779234B2 (en) * 2007-10-23 2010-08-17 International Business Machines Corporation System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor
US9471317B2 (en) * 2012-09-27 2016-10-18 Texas Instruments Deutschland Gmbh Execution of additional instructions in conjunction atomically as specified in instruction field
US9400653B2 (en) * 2013-03-14 2016-07-26 Samsung Electronics Co., Ltd. System and method to clear and rebuild dependencies
US10185568B2 (en) 2016-04-22 2019-01-22 Microsoft Technology Licensing, Llc Annotation logic for dynamic instruction lookahead distance determination

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5555384A (en) 1989-12-01 1996-09-10 Silicon Graphics, Inc. Rescheduling conflicting issued instructions by delaying one conflicting instruction into the same pipeline stage as a third non-conflicting instruction
US5712996A (en) 1993-03-15 1998-01-27 Siemens Aktiengesellschaft Process for dividing instructions of a computer program into instruction groups for parallel processing
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
US6233599B1 (en) * 1997-07-10 2001-05-15 International Business Machines Corporation Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
US6223208B1 (en) * 1997-10-03 2001-04-24 International Business Machines Corporation Moving data in and out of processor units using idle register/storage functional units
US6105051A (en) * 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
KR100280460B1 (ko) * 1998-04-08 2001-02-01 김영환 데이터 처리 장치 및 이의 복수의 스레드 처리 방법

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