TWI339354B - Microcontroller instruction set - Google Patents

Description

1339354 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a microcontroller, and more specifically to the present invention, to an opcode instruction that is assembled in an instruction set and used to manipulate the behavior of the microcontroller. [Prior Art] A microcontroller unit (MCU) has been used in the manufacturing and electronics industries for many years. Figure 1 shows a typical core memory bus configuration for a medium MCU device. In many cases, the microcontroller utilizes a reduced instruction set computing (RISC) microprocessor. The high performance of some of these devices is attributable to several architectural features that are common in RISC microprocessors. These features include:

Harvard architecture long word instruction single word instruction single cycle instruction instruction pipeline operation streamlined instruction set register file archive architecture orthogonal (symmetric) instruction Harvard architecture: As shown in Figure 2, the Harvard architecture has program memory 26 and data memory 22, The memory of the memory system is separated and can be accessed by the CPU 24 from a separate bus. This results in an improvement in bandwidth over the traditional von Neumann architecture (shown in Figure 3). In the von Neumann architecture, the CPU 34 uses the same bus to fetch the program from the same memory 36. 96790.doc 1339354 In order to execute an instruction, the v〇n Neumann machine must go through the 8-bit bus machine for one or more (_ many times) accesses to take the command. Then, it may be necessary to capture, operate and It is possible to write data. As can be seen from this description, the busbar can become extremely crowded. Contrary to the von Neumann machine, under the Harvard architecture, all 14 bits of the instruction are fetched in a single command cycle. Therefore, under the Hamrd architecture, when the program memory is being accessed, the data memory system is on a separate bus and can be read and written. These separate buss can be read while executing an instruction. One instruction. Long word instruction: The instruction bus of the long word instruction is wider than the 8-bit data memory bus (more bits of the former) ^ This feature can be realized because the two bus lines are separate. Make The size of the command is different from the 8-bit wide data word, so that the program memory can be used more effectively because the width of the program memory is optimized for the architectural requirements. Single word instruction: The single word instruction operation code is 14 bits wide. Thus, all single word instructions can be used. A 14-bit wide program memory access bus can capture a 14-bit instruction in a single cycle. If a single word instruction is used, the number of words in the program memory location is equal to the device's The number of instructions. This means that all locations are valid instructions. Typically, in the von Neumann architecture (shown in Figure 3), most of the instructions are multi-bytes. However, in general, there are 4K byte programs. The memory device will allow approximately 2K instructions. This 2: 丨 ratio is generalized 'and depends on the application code. Because each instruction uses multiple bits 96790.doc 1339354 group', each location cannot be guaranteed Both are valid instructions. Command pipeline: This command pipeline is the secondary pipeline that makes the acquisition and execution of the command overlap. The sleep of the command - the machine cycle ("TCY"), and The execution of the instruction consumes another TCY. However, since the current instruction's couch is overlapped with the execution of the previous instruction, the instruction is taken during the TCY of each order, and another instruction is executed. Single-cycle instructions: If the program memory bus is 14 bits wide, the entire instruction can be fetched in a single TCY. This instruction package gives α 7匕3 all the information needed and is tied to

Execute in a single cycle. b I If the result of the deduction modifies the contents of the program counter, then there may be a delay in the execution of the program. This requires clearing the pipeline and taking a new instruction. Reduced instruction set: = instruction money is carefully designed and the phantom is highly orthogonal (: requires fewer instructions to perform all necessary tasks. If the instruction is y, the entire instruction set can be learned faster. Architecture: The temporary storage system can be directly or indirectly addressed. The special function of this register is included in the program. The two-state mapping is in the quadrilateral memory orthogonal (symmetric) Instruction: Orthogonal instructions make it possible to use any operation of any line. There is no "special instruction" in the memory port of this register, 96779.doc 1339354 孝式° is easy and efficient. The learning curve can be greatly simplified. The medium-sized instruction set uses only two non-scratch-oriented instructions for two core features. The SLEEP refers to ", which places the device in the lowest power usage mode. Another one is the CLRWDT instruction, which prevents the wafer from operating properly by preventing the watchdog timer (WDT) from overflowing and resetting the device. Clock scheme/instruction cycle: Input the pulse in the internal port (self-〇scl) ) divided into four In order to generate non-overlapping heavy clocks, namely Ql, Q2, QWQ4. Internally, in each ... incremental tip a (PC), and in Q4 t capture instructions from the program memory and latch the pot in the instruction The buffer I decodes and executes the finger 7 during the subsequent object correction 4. The clock and instruction execution flow are illustrated in Figures 4 and 5. Instruction flow/pipeline operation: One "instruction cycle" 四个 four Q cycles (q1) as shown in Figure 4. , q2, q^ Q4) The 'q cycles include γ as shown in Figure 5. In Fig. 5, except for any program branch, execute the (4) command in a single cycle. It takes two cycles because the instruction is fetched from the pipeline and the new instruction is fetched and executed. The instruction takes one instruction cycle, while the decoding and execution of the week consumes another instruction cycle. f and 'Because of the pipeline operation, each instruction is valid in the - cycle and also the program counter is changed (for example, it takes - an extra cycle to complete the instruction (Figure 5). The program counter is repeated in Q1. The batch increment is in the execution cycle and will be captured in the week_ The instruction is latched into r, which means that the instruction is executed in the Q2, 96779.doc 1339354 Q', Q4 cycle. The read is performed during the period. And write (destination write) data memory during Q4. Figure 5 shows the operation of the secondary pipeline for the sequence of instructions shown. At time tcy, the first instruction is fetched from the program memory. (7) During the execution of the first instruction, the second instruction is executed at the same time. In TCY2_, the second instruction is executed while the third instruction is being executed. In TCY3_, the fourth instruction is executed while the third instruction is executed (CALL SUB_ip when the second instruction is completed) At the time, the cpu forces the address of the instruction four to enter (4)' and then changes the program counter (pc) to the address of []. This means that you need to "clear" the instructions that were taken during TCY3 from the pipeline. During TCY4, instruction four is cleared (executed as a N〇p) and the instruction of address SUBJ is fetched. Finally, at TCY5, execute instruction five and dig the instruction of address SUB_1 + 1. Although the prior art microcontroller is useful, it cannot simulate various modules. Moreover, the type of microcontroller shown in Figure ! cannot Linearizing the address space. Finally, prior art microcontrollers are susceptible to compiler error problems. Those in need are devices, methods and systems for microcontrollers that can linearize address space for implementation. Modular simulation. The present invention also has the need to reduce compiler errors. SUMMARY OF THE INVENTION The present invention overcomes the above problems and other deficiencies and deficiencies of the prior art by providing a set of microcontroller control instructions. The instruction set eliminates many of the compiler errors encountered in the prior art. Furthermore, the __device and system are used to implement a linearized address space, which makes modular simulation possible. The present invention can be directly < Inter-ground addressing #胄存(四)帛"Data Memory 96779.doc 1339354. All special function registers, temporary memory Mx, and program counter (pc) and work temporary storage, mapped to this data The memory set is called the instruction set, which makes it possible to use any address--orthogonal (any operation on the line. This symmetry), plus the register on the register, 'plus the absence of "special best," The programming of the invention is simple and efficient. In addition, the learning curve for writing to the software application can be enlarged. One of the improvements of the present invention relative to the second technology is that the two building registers can be used for some. In the two operand instructions, this allows the data to be moved directly between the two registers without having to go through the W register '0' to improve performance and reduce the use of program memory. Examples include an ALU/W register, a PLA, an 8-bit multiplier, a stacked program counter (4), a table latch/table index, a ROM latch/IR latch, FSR, Interrupt directional circuits and the most common state registers. Unlike the prior art, the design of the present invention does not require a separate module timer, all reset generation circuits (WDT, POR, BOR, etc.), interrupt flags. , actuating the flag, INTC The ON register, the RCON register, the configuration bit, the device ID character, the ID location, and the clock driver. Those skilled in the art will appreciate additional embodiments after reference to the detailed description and the drawings. The present invention is an apparatus, method and system for providing a microcontroller instruction set and a microcontroller architecture in a plurality of specific embodiments, the microcontroller architecture comprising a linearized address space, which Implementing a modular simulation. 96779.doc 12 1339354 The device architecture of the preferred embodiment of the present invention modifies the prior art Harvard architecture with a four-phase internal clock scheme such that the data path is 8 bits and the instruction length is 16 bits. Moreover, the preferred embodiment has a linearized memory addressing scheme that eliminates the need for paging and partitioning. The memory addressing scheme of the present invention allows program memory addressing capabilities to be as high as the stereol. The invention also supports simulation of modules. The present invention overcomes the above problems and other deficiencies and deficiencies of the prior art by providing a set of microcontroller instructions that eliminates many of the compiler errors encountered in the prior art. Moreover, a device and system are provided for implementing a linearized address space that enables modular simulation. The present invention can address its scratchpad file or data memory directly or indirectly. All special function registers, including the program counter (pc) and the work register (W), are mapped in the data memory. It turns out that there is an orthogonal (symmetric) instruction set that allows any operation to be performed on any register using any addressing mode. The nature of this symmetry, combined with the absence of "special best cases, makes the programming of the present invention both Simple and efficient. In addition, the learning curve can be greatly simplified. One of the series of architectural improvements of the present invention relative to the prior art is that two file registers can be used in some of the two operand instructions. The scratchpads move directly between the registers without having to go through the ... register, thereby improving performance and reducing the use of program memory. Figure 6 shows a block diagram of the core of the microcontroller of the present invention. According to the customary practice, the connecting signal line of Figure 6 may include a diagonal line. The number next to the diagonal line indicates the bandwidth of the signal line (in bits). Referring to the upper right corner of Figure 6, there is - data 96779.doc 1 Recollection 1G4' is used to store data and transmit data to the -t central processing unit 70 (described below) sub-k 4 central processing single S transmission data. The data memory system consists of multiple The address location is composed. In a preferred embodiment of the present invention, the data memory m is a linearized 4K memory, which is divided into a plurality of 4 knives, each of which has sixteen pages or a repository. Typically, each repository has 256 address locations. In the preferred embodiment, one of the plurality of repositories is dedicated to general purpose and dedicated registers, in this case the highest The repository, i.e., repository 0. A selection circuit 108 is consuming a data memory 104 via an address latch 102. The selection circuit (10) is used to select a plurality of supply repository addresses. The specific embodiment includes an ALU 140 and a work register 136; - PLA; - 8-bit multiplier; a program counter (pc) i68 and stack 170; - table latch 124; table indicator 148: a r〇m lock 152 and IR latches 126; FSRs 120, 121, 122; interrupt directional circuits and the most common state registers. Unlike the prior art, the design of the present invention does not require a timer in a single module, all Reset generation circuit (WDT, POR, BOR, etc. , break flag, actuated flag, INTC〇N register, RCON register, configuration bit, device m-character, 1-position and clock driver. I/O list: Available with the present invention A large list of input/output (1/0) commands, the I/O list is shown in table i. 96779.doc 14 1339354 Table 1 I/O List Name Counting I/O Normal Operation Operation Test Module Program Module Simulation Module addr<21:0> 22/0 program memory address nqbank<3:0> 4/0 active low RAM repository select d<15:0> 16/1 program memory data db<7:0> 8 /1/0 Data bus forcext 1/1 Force external command test mode irp<7:0> 8/0 Peripheral address irp9 1/0 Instruction register bit 9 ncodeprt 1/1 Active low code protection neprtim 1/ 1 active low EPROM write end nhalt 1/1 activity low pause nintake 1/1 activity low interrupt acknowledge early and wake up from sleep np<7:0> 8/0 table latch data npcmux 1/0 active low PC Npchold 1/0 activity low PC keep nprtchg 1/1 activity low 埠 change interrupt Nq4clrwdt 1/0 active low clear wdt nq4sleep 1/0 active low sleep nqrd 1/0 active low read file nreset 1/1 active low reset nwrf 1/0 active low write file ql:q4 4/1 4 phase Q Clock qi3 1/1 Q clock combination q23 1/1 Q clock combination q41 1/1 Q clock combination testO 1/1 test mode 0 tsthvdet 1/1 high voltage detection wreprom 1/0 write Eprom writem 1/0 write memory wrtbl 1/0 table write instruction nintakd 1/1 interrupt acknowledge delay intak 1/1 interrupt acknowledge 96790.doc •15- 1339354 clock scheme/instruction cycle as shown in Figure 7, in Internally, the clock input (self-〇scl) is divided into four to generate non-overlapping quadruple clocks, namely Q1, Q2, and QmQ4. Internally, the program counter (PC) is incremented every ^Qi, and the pointer is fetched from the program memory using Q4: and latched in the instruction temporary memory 11. The instructions are decoded and executed during subsequent Q1 and Q4. The PLA decoding is completed at Q1. During the teacher cycle, the operands are read from the memory or peripheral components and ALU performs the calculation. During Q4, the results are written to the destination location. Figure 8 illustrates the clock flow. 7 Vanadium Q cycle activity is shown in Figure 7. Each instruction cycle (TCY) is from four cycles (9) to completion. The HQ cycle is the same as the device oscillator period (TOSC). 0 is decoded and read, When processing data, writing, etc.: 曰疋T diagram (Figure 7) shows the relationship between Q cycle and instruction cycle. The four Q cycles of two-line instruction cycle (TCY) can be generalized as:

Q 1. Instruction decoding cycle or forced NOP Q2. Instruction read cycle or NOP Q3: Processing data

Q4 • The heartbeat write cycle or NOP master instruction will display the detailed Q cycle operation of the instruction. The instruction stream/pipeline operation is set to ^_q_ (φ'Q2'(4)(10) and the decoding and execution consumes another, and the "order cycle, 曰々k, is taken. However, due to pipeline operation, 96779.doc 16 1339354 each instruction Executed effectively in a cycle. There are four types of instruction streams. The first class is a normal 1-character 1-cycle pipeline instruction. As shown in Figure 9, these instructions will consume the "expiration cycle". A 1-character 2-cycle pipeline clearing means that these private orders include relative branches, relative calls, skips, and returns. When the field S 7 is changed to PC, the pipeline is discarded. As shown in Figure 1, this makes The instruction is executed in two valid cycles. The third type is a table operation instruction. These instructions will suspend the capture to insert and read or write cycles to the program memory. When executing the table operation (4) The (five) cycle, and the next-cycle execution after the table operation, as shown in Figure 11. The fourth class is the new two-word instruction. These instructions include MOVFF and M0VLF. In these instructions, the operation after the instruction Contains the remainder of the addresses. For the M during the first character period OVFF, the machine will perform a read of the source register. During the execution of the second character 'get the source address, then the instruction will complete the move' as shown in Figure 12. M0VLF is similar, but it is (10) Move 2 literal values into the cycle, as shown in Figure 13. The fifth 'system' is a two-word instruction for CALL and GOTO. The instruction after the instruction in these instructions contains the remainder of the jump or call destination address. ^ In the case, these instructions will take 3 cycles to execute, which causes 2 to fetch the 2 instruction characters and 1 for subsequent pipeline clearing. However, by the second capture A high-speed path is provided to update the PC 'with a complete value in the first cycle of instruction execution to obtain a 2-cycle instruction, as shown in Figure 14. Sixth, interrupt recognition execution. In the interrupt section below The instruction cycle during the interrupt is discussed. 96779.doc

ALU The present invention includes an 8-bit arithmetic and logic unit (alu) M2 and a work register 136' as shown in FIG. The ALU 142 is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the scratchpad and any scratchpad file. The ALU U2 is octet wide and is capable of performing addition, subtraction, and shifting. Unless otherwise mentioned, the arithmetic operation is the complement of f. The work (w) register 136 is an 8-bit work temporary storage for the ALUl4 operation. The w register 136 is addressable and can be directly written or read: AUJUO can operate on two operands. Or a single operand performs arithmetic or logic operations. All single operand instructions operate on the ... scratchpad 136 or the intended file register. For two operand instructions, the t-operating elements are the W register 136' and the other-system-file register or -8-bit immediate constant, or an equivalent storage medium. Depending on the instruction being executed, ALU 14〇 can affect the STATUS register (described below) one carry (C), digital carry (DC), zero (z), overflow (〇v) and negative (8) The C and DC bits are used as a borrow and a digital lending bit, respectively, in subtraction. The preferred embodiment of the present month includes an -8 X8 hardware multiplier 1 34, which is included in the ALU 142 as shown in Fig. 6 'seven a* m kg. By making the multiplication _ / acknowledgment, the 4 operations can be completed in a single instruction cycle. This hardware transports the unsigned multiplication of the 16-bit result. The result is stored in the 16-bit product register (PRQDH: PR〇DL multiplier does not affect any flags in the ST Na register. Status register 96779.doc -18-. Figure 15 shows The bit 7-5 is not implemented. The ST-S register contains the status bit of the ALui4~ register. In the preferred embodiment of the present invention, 'is taken as |0, read. Line 'N', which is the negative bit 疋. This bit is used for signed arithmetic (2's complement) ° which indicates whether the result is negative, (ALUMSb=1), 1=the result is negative, 〇=result Positive. Positioned as 3 "0V" overflow bit. This bit is used for signed arithmetic (2's complement). It indicates that the 7-bit size overflows the sign bit (the bit is changed) Branch state. For this bit '1 = signed arithmetic overflow, (in this arithmetic operation), and 〇 = no overflow occurs. The element z" is the bit. For this bit, 丨 = arithmetic or The result of the logical operation is that the result of the arithmetic and logical operation is non-zero. 4 yuan 1 series DC" digital carry / borrow bit. For this bit, 1 = the fourth low order of the fruit yuan The raw bit is output, and 〇 = the fourth low-order bit of the result does not have a carry output. It should be noted that for the borrow, the polarity can be reversed. The bit 0 is the "C" carry/borrow bit. Yuan, 1 = the result of the two significant bits τ ο a carry output, and 〇 = the most significant bit of the result does not carry a carry output. Like bit 1 'for borrowing, the polarity can be reversed. c and DC The bit system subtraction method is used as a borrowing and a digit borrowing bit respectively. The carry system ALU bit 7 carries the carry output. The digital carry system aLu bit 3 carries the carry output. If the ALU result bit <7:〇> 1〇,, then the zero is true. ^^ is the ALU result bit 7. If the complement result of 2 exceeds + 127 or is less than _128, then 96796.doc -19- 1339354 is set to the overflow bit. Overflow ALU bit 6 carry output and ALU bit 7 carry output XOR operation. Like all other registers, the STATUS register can be the destination of any instruction. If the STATUS register affects any status bit The write of the instruction of the meta-instruction disables the writing of the status bit. According to the ALU result and the instruction specification To set or clear the bits. Therefore, the result of the instruction to use the STATUS register as a destination may not match expectations.

For example, the CLRF REG instruction typically writes the scratchpad to 〇 and sets the Z bit. The CLRF STATUS instruction will disable writing to N, OV, DC, and C bits and set the Z bit. This causes the STATUS register to become 〇〇〇u uluu. Therefore, it is recommended to use only the BCF, BSF, SWAPF, and MOVWF instructions to change the STATUS register because these instructions do not affect any status bits. To find out how other instructions affect these status bits, see "Instruction Set Overview." Program counter module

Modify the program counter (PC) 168 (see Figure 6) to allow expansion to a maximum of 21 bits. This is done by adding a 5-bit wide PCLATU register, which operates similar to the PCLATH register. The PC 168 is also modified to address the bytes in the program memory rather than the words. To implement this, a tuple addressing bit at the LSb of the PC 168 is always 〇. The LSb bit of Pcl is readable but not writable. If the user attempts to write 丨I to LSb, the result will be '〇'. To allow the hidden test EPr〇m, pc 168 needs to have a hidden 22nd bit (bit 21) (see Figure 16). This PC bit is 0 in normal case. When entering test mode or programming mode, set this 96779.doc -20- 1339354 bit and retrieve the instructions from the test area. Once this bit is set, it cannot be cleared by executing the program, and the device must be reset. The program counter (PC) 168 is up to a 21-bit scratchpad as shown in FIG. PCL 184, the lower byte of PC 168, is mapped into data memory 104 (see Figure 6). The PCL 184 is readable and writable, just like any other scratchpad. PCH 182 and PCU 180 are high-order tuples of PC and are not directly addressable. Since the PCH 182 and PCU 184 are not mapped into the data or program memory 160, the scratchpads PCLATH 178 (PC high latch) and PCLATU 176 (PC upper latch) are used as the high byte of the PC 168. Hold the latch. PCLATH 178 and PCLATU 176 are mapped into data memory 104. The user can read and write to the PCH 182 via the PCLATH 178 and read and write to the PCU 180 via the PCLATU 176. Each time the instruction is fetched during Q1, the word of the PC 168 is incremented by 2 unless: • by one GOTO, CALL, RETURN, RETLW, RETFIE, or Branch instruction modification 0 • Modification by interrupt response. • Due to an instruction write to the destination of PCL 168. "Skip" is equivalent to one of the skipped addresses to force a NOP period. Figures 16 and 17 show the operation of the program counter for various situations. Referring to Figure 16, the operation of PC 168, PCLATH 178 and PCLATU 176 for different instructions is as follows: a. Read command for PCL: Any instruction to read PCL 184. All byte instructions for d=0; 96779.doc -21 · 1339354 MOVFF PCL, X ; CPFSEQ ; CPFSGT ; CPFSLT ; MULWF ; TSTFSZ then PCL to data bus and then to ALU or to destination. Finally, PCH to PCLATH and PCU to PCLATU. b. Write instruction for PCL: Any instruction written to PCL 184. For example, MOVWF; CLRF; SETF, then write 8-bit data to data bus 1 74, then to PCL 1 84. Also, PCLATH to PCH and PCLATU to PCU. c. Read-modify-write instructions for PCL:

Any instruction that performs a read-write-modify operation on the PCL. All byte instructions of d=l; bit instructions; NEGF. Read: PCL to data bus to ALU. Write: Write 8-bit results to the data bus and to PCL, then PCLATH to PCH; finally PCLATU to PCU.

Read-modify-write only affects PCL 184 with the result. The values in PCLATH 178 and PCLATU 176 are loaded into PCH 182 and PCU 180, respectively. For example, for the instruction "ADDWF", PCL 1 84 will cause the following jump. If you are pointing

Before the command, PC = 0003F0h, W = 30h, PCLATH = 〇5h and PCLATU = lh ' then PC = 01052〇h after the instruction » In order to complete a real 20-bit calculation jump, the user needs to calculate the 20-bit destination bit. Address, write PCLATH 178 and PCLATU 176, then write the low value to PCL 168 〇d. RETURN command: Use <MRU> to stack PC to PC <20:0>, GOTO and CALL instruction PC 168, The operation of PCLATH 178 and PCLATU 176 is as follows: e. CALL, GOTO instructions: Provide a destination address in a 2-word instruction (opcode). The first word opcode 96779.doc -22- 1339354 <6:0> to PCL<7:1>. The first word operation code <7> to PCLATH<0> and to PCH<0>. The second word operation code <6:〇> to PCLATH<7:1> and PCH <7:1>. The second word opcode <ιι:7> to PCLATU<4:0> and PCU <4:0> ° It should be noted that the following operations related to PC 168 do not change PCLATH 178 and PCLATU 176: a. RETLW, RETURN and RETFIE instructions b. Force the interrupt vector to the PC.

c. Read-modify-write instructions for PCL (eg BSF PCL, 2). Back to Stack Operation The present invention has a 31 layer deep return (or hard) stack. The depth of the stack has increased relative to the prior art to allow for more complex programs. This stack is not part of the program or data memory space.

Push the PC 168 onto the stack when executing a CALL or RC ALL command or confirming an interrupt. When the RETURN, RETLW, or RETFIE instruction is executed, the PC 168 value is pulled from the stack. PCLATU 176 and PCLATH 178 are not affected by any return commands. The stack is used as a 31-character x 21-bit RAM with a 5-bit stacking indicator, and the stacking indicator is initialized to OOOOOb0 after all resets. There is no RAM word associated with the stacked indicator OOOh. This is only a reset value. A CALL-type instruction causes a stack indicator to be incremented during the push-in to the stack, and the contents of the PC are written at the RAM location pointed to by the stack indicator. A RETURN type command causes the contents of the RAM location pointed to by the STKPTR to be transferred to the PC during fetching from the stack, and then the stacking index is decremented. 96779.doc -23· 1339354 Stack top access

The top of the stack is readable and writable. Three register locations TOSU, TOSH, and TOSL address the stack RAM location pointed to by STKPTR. This allows the user to implement a software stack when necessary. After a CALL or RC ALL instruction or an interrupt, the software can read the pushed value by reading the TOSU, TOSH, and TOSL registers. This value can be placed on a user-defined software stack. On return, the software can replace TOSU, TOSH and TOSL and make a return. It should be noted that during this time, the user must disable the global interrupt actuation bit to prevent inadvertent stacking operations. PUSH and POP instructions

Because the top of stack (TOS) is readable and writable, the ability to push values onto the stack and pull values from the stack without disturbing normal program execution is an ideal choice. In order to push the current PC value onto the stack, a PUSH instruction can be executed. This pushes the current PC value onto the stack; set TOS = PC and PC = PC + 2. The ability to pull a TOS value from the stack and replace it with a value previously pushed onto the stack without disturbing normal execution is achieved by using a POP instruction. The POP instruction pulls the TOS value from the stack, but this value is not written to the PC; the previous value pushed onto the stack becomes the TOS value. Return Stacking Indicator (STKPTR) The STKPTR register contains the return stack indicator value and the overflow and underflow bits. Stack Overflow Bits (STKOVF) and Underflow Bits (STKUNF) allow software to verify stacking conditions. The STKOVF and 96779.doc -24·1339354 STKUNF bits are cleared only after the POR is reset. After pushing the PC onto the stack 31 times (no value is pulled from the stack), the 32nd push overwrites the value from the 31st push and sets the STK-OVF bit, and STKPTR remains at 11111b. The 33rd push overrides the 32nd push (and so on) while the STKPTR remains at 11111b. After the stack is removed multiple times to unload the stack, the next take-out will return a zero value to the PC and set the STKUNF bit while keeping the STKPTR at 00000b. The next time it is taken back to zero again (and so on) while keeping STKPTR at 00000b » It should be noted that returning a zero to the PC in the case of underflow has the effect of orienting the program to the reset vector, where the stacking condition can be verified and Take the appropriate action. Stacking metrics can be accessed via the STKPTR register. The user can read and write the stack indicator values. The RTOS can use this value to return to stack maintenance. Figure 18 shows the STKPTR register. The value of the stacked indicator will be 〇 to 31. When resetting, the stack indicator value will be 〇. When pushed in, the stack indicator will increment 'and decrease when it is fetched. Stack Overflow/Underflow Reset The overflow and underflow can cause a device to reset the interrupt code according to the user's choice. The reset is actuated using a configuration bit STVRE. When the STVRE bit is deactivated, an overflow or underflow will set the appropriate STKOVF or STKUNF bit without causing a reset. When the STVRE bit is actuated, an overflow or underflow will set the appropriate STKOVF or STKUNF bit, and then the nature of a device reset is very similar to the WDT reset. In either case, the STK0VF or STKUNF bit is not cleared unless the user software or P〇R reset clears it. Figure 18 96779.doc -25-1339354 through 21 illustrate the stack register. 22 to 29 illustrate the stacking operation. Program Memory A preferred embodiment of the present invention has up to 2 million bytes (2 Μ) χ 8 user program memory space. The program memory space is primarily intended to contain instructions for execution 'however' table read and write instructions can be used to store and access data tables. There is another - heart 8 test program memory space for testing R0M, configuration bits and identification characters. The device has a program counter of up to 21 bits that can address 2MX8 program memory space. There is also a 22nd bit, which is hidden during the normal operation, and when it is set (4), the configuration bit, device ID and test R 〇 are accessible. This bit can be set in test mode or programming mode and must be reset to clear this bit. Use this bit • You will not be able to access the user program memory space. Since the PC must access the instructions on the boundary of an even number of bits in the Spear-Type Hidden Object, the LSb of the PC is implied, 〇, and for each instruction, the PC is incremented by two. «Hai sigh vector 000000h, and the high priority interrupt vector is 0 0 0 0 0 8 h, and the day 基 / base it 44 * low priority interrupt vector system 〇〇〇〇 18h (see Figure 3 〇). ▼ Program Memory Organization Each location in the body has a 1-bit address. In addition, every 2 adjacent bits and the right one ^ - , eight male and one sub-address. Figure 31 shows a mapping of the <forms' memory of the indicated byte and the address. In the program memory, the sub-items must be aligned. Figure 32 shows a program with several exemplary instructions ", and the hexadecimal table placed in the map for those instructions will work with the byte entity. The table block does not have to be word 96797 .doc •26· 1339354 Alignment, so the table block can start and end at any byte address. The exception to this is the use of table writes to program internal program memory or external character wide flash memory. When stylized, you may need to align the write data with the character width used by the stylization method. Program Memory Mode The present invention can operate in one of five possible program memory configurations. This configuration is selected by configuring the bit. The possible modes are: • MP-Microprocessor • EMC-Expanded Microcontroller 0 • PEMC-Protected Expansion Microcontroller • MC-Microcontroller • PMC-Protected Microcontroller Microcontroller and Protected Microcontroller The mode is only allowed to be executed internally. All accesses outside of the program's memory read all zeros. The protected microcontroller mode also activates the code protection feature. The microcontroller is a preset mode for an unprogrammed device. Expand the microcontroller mode to access internal program memory and external program memory. Execution automatically switches between internal and external memory. The 2 bits: The address allows the program memory range of 2M bytes. The protected extended microcontroller mode will protect the table from reading/writing external program memory by preventing read/write to the internal memory table. ΙΜ Presentation This microprocessor mode only accesses external program memory. The program memory on the wafer is ignored. The 2!bit address allows for 2 rivers of the tuple = memory 96779.doc • 27· 1339354 range. Test memory and configuration bits can be read by using the TBLRD instruction during normal operation of the device. If the LWRT bit in the RC0N register is set or the device is in S-mode and programming mode, then only the TBLWT instruction can be used to modify these areas.

Execution from these areas is only possible in test and programming modes. 9 Expanded microcontroller mode and microprocessor mode are only available on devices with external memory busses that are defined as part of the 1/0 pin. Table 2 lists which modes access internal and external memory. Figure 33 illustrates device memory mapping in different program modes. Figure 2 Device Mode Memory Access Operation Mode Internal Program Memory External Program Memory Microprocessor No Access Execution / TBLRD/TBLWT Extended Microcontroller Execution / TBLRD / TBLWT Execution / TBLRD / TBLWT Protected Extended Microcontroller Execution Execute /TBLRD/TBLWT Microcontroller Execution /TBLRD/TBLWT No Access Protected Microcontroller %f/TBLRD No Access External Program Memory Interface When selecting microprocessor or expansion microcontroller mode, up to four The blame is the system bus. Part of the two 埠 and the third 系 are multiplexed addresses/data El platoons and a part of the other 埠 系 is used for control signals. An external component is required to solve the multiplex address and data. The external memory interface can be run in 8-bit 7G Beacon & or 16-bit data mode. The address on the external memory interface is the total tuple address. Figures 36 and 37 illustrate the external memory connection of 16-bit and 8-bit data, respectively. 96779.doc • 28· 1339354 Connect to the external program memory bus to share the 1/〇埠 function on the pin. Figure μ shows a typical mapping of the external bus function on the I/O pin function. In the extended microcontroller mode, when the device is executed outside of the internal memory, the control signals will be inactive. It will enter a state in which 5 forces >, eight <19:0> are tri-state; 0E, WRH, WRL, 1^ and []8 signal systems "i"; UBAO and ALE are "0"" 16 bits If the external interface is 16 bits, then the external interface will be taken as a 16-bit character. . The OE output actuation signal will actuate both types of program memory at a time to output a 16-bit character. There is no need to connect the least significant bit ΒΑ0 of the address to the memory device. An external table read logically executes a tuple at a time, although the memory will read a 16-bit character from the outside. The least significant bit of the location will be selected internally between the high and low bytes (LSb = 0 to the lower byte, LSb = 1 to the higher byte). The external address in the microprocessor and extended microcontroller mode is 21 bits wide; this allows addressing up to 2M bytes b. An external table write on a 16-bit bus is logically executed once. group. The contiguous write will depend on the type of external device connected and the WM<1:〇> bit in the MEMCON register, as shown in Figure 34. The table operation section details the actual write cycle & 8-bit external interface. If the external interface is 8 bits, it will be retrieved as two 8-bit bytes - Xuan et al. Two bytes are fetched during the - instruction cycle. There is no need to connect the least significant bit of the address to the memory device. Sakiy actuation signal and 96679.doc • 29- will be activated in the Q3 part of the 4 cycles to read the most π-valid group of the instruction from the program memory, and then in the part of the cycle, the 〇 will become 〇 The least significant byte will be taken to form a 16-bit instruction character. The reading of the foreign form is also performed by one tuple at a time. An external form is written into the system _ human execution - a byte. In each external write, the WRL system's active 0 field selects the 8-bit interface, does not use WRH, line, and the pin returns to the I/O埠 function. A configuration bit selects the 8-bit mode of the external interface. The external wait period is X. Hey. The memory interface supports the waiting period. The external memory wait cycle is only applicable to table read and table write operations through the external bus because the execution of the device is associated with instruction fetching, so the execution rate is less meaningful than the fetch rate. Therefore, if you need to make the program unloaded, you must slow the processor speed by a different TCY time. The WAIT <丨:〇> bit in the MEMCON register will select 〇, 1, 2 or 3 additional TCY cycles in each memory capture cycle. For a 16-bit 疋" table read and write, these wait cycles will be valid. On the 8-bit interface, for table reads and writes, this wait will only occur on Q4. The default setting waiting for power-on is to determine the wait for a maximum of 3 TcY cycles. This ensures that slow memory can work in the microprocessor wedge immediately after reset. A configuration bit, called WAIT, will activate or deactivate the wait state. Figure 39 illustrates the 16-bit interface, while Figure 4 illustrates the 8-bit. In both cases, 96796.doc -30- 1339354 shows the program memory instruction capture without wait and the table read with wait state. . External bus signal deactivation In order to flexibly utilize the pins submitted to the external bus, several deactivations are provided in the configuration bits. To deactivate the entire external bus, as may be done while expanding the microcontroller mode, and to allow a Dma function, configure the EBDIS bit in the MEM-CON register as shown in Figure 35. This deactivation will allow tristate processing of the entire external bus interface. This will allow DMA operations and direct control of external devices via program control via the 1/0 pin function. In the simulator system, the -ME device must have an input to indicate the bus stop configuration bit so that the 1/0 function can detect the state of the pin as the external interface. The _ME device also has a special input pin that indicates whether the simulator system is in the microprocessor or expansion microcontroller mode. Data Memory In the present invention, the data memory and general RAM size can be expanded to 4096 bytes. The data memory address is 12 bits wide. The data memory is divided into 16 repositories, each of which has 256 bytes, and the repositories include a general purpose register (GPR) and a special function register (SFR mechanizes GPR into a single element) The group wide RAM array is equivalent in size to the combined GPR register. Usually the SFR is allocated between the peripheral components whose s FR controls its function. The storage select register (BSR<3:G>) is used to select the storage. (4) The scratchpad may access more than 16 repositories, however the direct long addressing mode 96779.doc 31 1339354 is limited to 12-bit addresses or 16 repositories. bsR is subject to corresponding restrictions. Read, modify, and write to a specific location during the instruction cycle. Only one address is generated per cycle, so it is not possible to read a location and modify/write another location in a single cycle. Figure 42 illustrates an example data. Memory Map. General Purpose Register In all PIC devices, all data RAM is used as a scratchpad by all instructions. Most data memory banks contain only GPR memory, and all devices must be included in the repository. G p R memory The absolute minimum number of GPRs in repository 0 is 128. This GPR region, called access RAM, is necessary so that the programmer can have a data structure that can be accessed regardless of the BSR settings. The SFR is a special temporary storage η, which is usually used for device and peripheral control and status functions. All instructions can access these registers. If possible, the upper 128 bytes of the storage (4) should contain all the coffee. If (iv) not using all available locations on a particular device, the unfinished location is not implemented and its reading device, such as the lcd controller, may have a sir region in a repository other than the repository 15. The boundary of the SFR in the library 15 can be modified by the device. At least 16 coffees must be included in the access. Figure 43 shows the possible function register map. Figure 44 disk 45 + #, # 。 45 display TMm Force Registers Addressing Mode 96797.doc • 32- 1339354 The present invention supports 7 data addressing modes: • Inherent • Text • Direct Short • Direct Mandatory • Direct Long • Indirect • Index Indirect Offset Three Mode, that is, straight Mandatory, Direct Long and Indirect Indexing are new modes of the PIC architecture. Inherently for some instructions, such as DAW, no addressing is required other than the addressing defined in the opcode. Text literals contain a literal constant field, usually Used for a mathematical operation, such as ADDLW. Text addressing is also used for GOTO, CALL and branch opcodes. Directly short Most math and move instructions operate in direct short addressing mode. In this addressing mode, the instruction contains the lowest data. The eight bits of the valid address. The remaining four bits of the address are from the repository select register or BSR. The BSR is used to switch between repositories in the data memory area (see Figure 47). The need for a large-capacity general-purpose memory space indicates a general-purpose RAM partition scheme. The lower half of the BSR selects the currently active general purpose RAM storage. 96779.doc -33 -

I3393M library. To assist with this operation, the instructions. The M0VLB repository has been provided in the instruction set. If you do not implement the repository currently selected from , (for example, repository 丨 3), any fetch will read all, 0,. Complete any writes of the paired bins and set/clear the STATUS register bit as appropriate. Direct Force Directs all Special Function Registers (SFRs) into the Data Memory Space Order. In order to conveniently access the SFR, all of them are mapped into the repository 15 as usual. To simplify access, there is a 1-bit field in the instruction that points to the lower half of the general-purpose read repository and the upper half of the SFR's repository 15, regardless of the content of the BSR. The BSR is set to BsR=n, so that three banks can be addressed by any command, that is, the banks 直接 and 15 in the direct forcing mode and the bank in the direct short mode. Direct Long Direct Long Address encodes all twelve bits of the data address into the instruction. This mode is only used by the MOVFF instruction. Indirect Addressing Indirect addressing is a mode of addressing data memory. The data memory address in the instruction is determined by another temporary storage Is. This may be useful for data tables or stacking in data memory. Figure 53 shows the operation of indirect addressing. The value of the FSR register is used as the data memory address. Indirect Addressing Register The present invention has three I 2 bit registers for indirect addressing. Such temporary storage B · Yi Yi · 96779.doc -34- 1339354

• FSROH and FSROL

• FSR1H and FSR1L

• FSR2H and FSR2L FSR are 12-bit registers and allow any location in the 4096-bit data memory address range to be addressed.

In addition to this, there are scratchpads INDF0, INDF1, and INDF2 that are not physically implemented. Reading or writing to these registers initiates indirect addressing, where the value of the data in the FSR register corresponds to the address of the data. If the file INDF0 (or INDF1, 2) itself is indirectly read via the FSR, all '0's (set zero bits) are read. Similarly, if INDF0 (or INDF1, 2) is written indirectly, then the operation will be equivalent to NOP and the STATUS bit will not be affected. Indirect Addressing Operation Each INDF register has four addresses associated with it. When data access to one of the four INDF locations is completed, the selected address configures the FSR scratchpad as:

• Automatically decrement the value (address) in the FSR after indirect access (post-decreasing). • Automatically increments the value (address) in the FSR after indirect access (post-increment). • Automatically increment the value (address) in the FSR (pre-increment) before indirect access. • The value (address) in the FSR is not changed after indirect access (no change). When using the auto-increment or auto-decrement feature, the effect on the FSR is not reflected in the STATUS register. For example, if the indirect addressing causes the FSR to be equal to '0', then the Z bit will not be set. Adding these features allows the FSR to be used to stack metrics in addition to data table operations. Index Indirect Addressing 96779.doc -35- 1339354 Each INDF has an address associated with it that performs an indirect access to an index. When a data access to this INDF location occurs, the FSR is configured to: • Add a signed value in the W scratchpad and the value in the FSR to form the address prior to indirect access. • Do not change the FSR value. Indirect Addressing (INDF) Register Interconnect Write If the FSR register contains a value, the value points to one of the indirect registers (FEFh-FEBh, FE7h-FE3h, FDFh-FDBh), and the indirect read The fetch will read OOh (set zero bit), and an indirect write will be equivalent to a NOP (the STATUS bit is unaffected). Index (FSR) Register Interconnect Write If an indirect addressing operation is completed where the target address is an FSRnH or FSRnL register, the write operation will dominate the pre-increment/decrement or post-increment/decrement function. For example: FSR0=FE8h (one less than the FSR0L position) W=50h MOVWF *(++FSR0) ; (PREINCO) Increase FSR0 by one to FE9h, pointing to FSR0L. Then, writing W to FSR0L changes FSR0L to 50h. However, FSR0=FE9h (the position of FSR0L) W=50h MOVWF *FSR0++ ; (POSTINCO) At the same time as FSR0 is incremented, an attempt is made to write W to FSR0L. W writes will be faster than post-increment and FSR0L will be 50h. 96779.doc -36- 1339354 Instruction Set Overview The instruction set of the present invention consists of 77 instructions. Due to excessive page and repository switching in prior art architectures, linearization of program and data memory mapping is required, and the δ mystery set is modified to facilitate this linearization. The data memory space of the preferred embodiment of the present invention has up to 4 bytes, which consists of 16 banks, each of which has 256 bytes. In a preferred embodiment of the present invention, all of the special function registers are located in a repository, preferably one of the opcodes of all instructions that execute file manipulation (which can force a virtual repository) Bit. Therefore, it is not necessary to switch to the storage 0 library to access the special function register. In a preferred embodiment, the program's memory space is modified to a maximum of 2 bytes on the basis of prior art systems. Increase the pc&3 bits to a maximum of 21 bits, and change some of the instructions (CALL·, GOTO) that caused the jump to a two-word instruction to load the 21-bit value for the PC. Another improvement over the prior art includes a modular simulator. This requires communication between the two slices used for the simulation, and in order to achieve the required speed, it is not possible to have different source and destination registers in the same instruction cycle. · Therefore 'eliminate the MOVPF and MOVFP instructions in the prior art. In order to maintain this power, add a two-word instruction MOVFF. The instruction set of the present invention can be grouped into three categories: • Bit tuple oriented • Bit oriented • Text and control operations. Figure 56 shows this look & temple format. Figure 54 shows the field description of the opcode. These 96779.doc -37- 1339354 instructions help to understand the opcodes in each of the specific instruction descriptions found in Figures 57 through 59 and in Appendix A. Figure 4 illustrates the instruction decode map. For a byte-oriented instruction, f denotes a file register specifier, and (!) denotes a destination specifier. The file register specifier specifies which file register to use for the instruction. The destination specifier specifies where the result of the operation is to be placed. If, d, =, 〇, then the result is placed in the % scratchpad. If 'd' =, l, then the The result is placed in the file register specified by the instruction. Similarly, for byte-oriented instructions, a· represents the virtual repository selection bit. If 'a'='〇', the BSR is overwritten and selected Virtual repository. If =, the repository select register (BSR) is not overwritten. For bit-oriented instructions, b, indicates the number of bits in a single field designator that affects the selected file operation. And 'f denotes the file address where the bit is located. For text and control operations, k means an 8-, 12, 16 or 20-bit constant or literal value. Moreover, V means fast call/return selection bit. If s-〇, the shadow register (sha (jow register) is not used. If s, =, 1 ·, the w, BSR and STATUS registers are updated from the shadow register via a RETURN or HETFIE instruction, or the shadow register is loaded from the corresponding register via a CALL instruction. ,, n, the complement of the system 2, which determines the direction and magnitude of the jump relative to the branch instruction. The instruction set is highly orthogonal and is grouped into: • a byte-oriented operation • a bit-oriented operation 96779.doc -38- 1339354 • Text and control operations execute all instructions in a single instruction cycle unless: • a conditional test is true • the program counter is changed by an instruction • a file is transferred to a file transfer • a table read area is executed or The table write instruction takes two instruction cycles in the above case, and the second cycle is executed as a NOP.

Special Function Scratchpad as Source/Destinity The orthogonal instruction set of the present invention allows reading and writing of all file registers, including special function registers. There are some special cases that users should be aware of:

STATUS as destination

If an instruction is written to the STATUS register, the Z, C, DC, 0V, and N bits can be set or cleared as a result of the instruction and the written original data bit can be overwritten.

Read, write or read-modify-write on PCL PCL as source or destination can have the following results: • For a read PCL, first PCU to PCLATU; then PCH to PCLATH; then PCL to destination . • For a write to PCL, first PCLATU to PCU; then PCLATH to PCH; then 8-bit result value to PCL. • For a read-modify-write: first PCL to ALU operand, then PCLATH to PCH, then PCLATU to PCU, then 8-bit result to 96790.doc 09- 1339354 PCL° where: PCL=program counter low bit Group PCH=Program Counter High Bit PCLATH=Program Counter High Hold Latch PCU=Program Counter Upper Part Tuple PCLATU=Program Counter Upper Hold Latch dest=destination, W or f.

Bit manipulation All bit manipulation instructions are completed by first reading the entire scratchpad, operating on the selected bit, and writing back the result (read-modify-write (R-M-W)). The user should remember this point when operating on some special function registers (such as 埠). It should be noted that status bits (including interrupt flag bits) manipulated by the device are set or cleared during the Q1 cycle. Therefore, there is no problem when executing the R-M-W instruction on the scratchpad containing these bits.

Figures 60 through 113 contain a flow chart of the general operation of the instructions within the instruction set of the present invention. The figures show the generalization and specific steps of the instructions in the instruction set for capturing and executing the invention. For example, FIG. 60 shows the steps for extracting a byte-oriented archive register operation, including instructions ADDWF, ADDWFC, ANDWF, COMF, DECF, INCF, IORWF, MOVF, RLCF, RLNCF, RRCF, RRNCF, SUBFWB, SUBWF, SUBWFB, SWAPF, XORWF, MOVWF and NOP. Similarly, Figure 61 shows the steps for performing a byte-oriented archive register operation, including the instructions ADD WF, ADD WFC, AND WF, COME, DECF, INCF, 96779.doc -40-1339354 IORWF, MOVF, RLCF , RNLCF, RRCF, RRNCF, SUBFWB, SUBWF, SUBWFB, SWAPF and XORWF (but MOVWF only performs a dummy read, and the NOP performs a dummy read and a dummy write) <» Figure 77 shows the capture of the text operation The steps include instructions ADDLW, ANDLW, IORLW, MOVLW, SUBLW, and XORLW. As before, Figure 78 shows the execution steps of the text operation, including the instructions ADDLW, ANDLW, IORLW, MOVLW, SUBLW, and XORLW.

Figure 90 shows a flow chart of the branching operation including instructions BC, BN, BNC, BNN, BNV, BNZ, BV and BZ. Similarly, Figure 90 shows a flow chart for performing a branch operation including instructions BC, BN, BNC, BNN, BNV, BNZ, BV, and BZ. The remaining diagrams show the steps to retrieve and execute other instructions in the instruction set.

For multi-word instructions that require two captures to get a complete instruction, three flow blocks are used to illustrate the entire capture and execution process. For example, Figures 70 through 72 illustrate the MOVFF instruction. Figure 70 shows a relatively standard capture operation. However, Figure 71 shows the execution of the first part of the MOVFF on the left side of the operation box, while the right part of the operation block shows the capture of the second character of the instruction. Thus, Figure 72 shows only the execution steps of the second character of the MOVFF instruction. A similar flow chart is provided for other multi-word instructions: LFSR (Figures 79 to 81); GOTO (Figures 102 to 104); CALL (Figures 105 to 107); TBLRD*, TBLRD* +, TBLRD*- and TBLRD + *( Figures 108 to 110); TBLWT*, TBLWT*+, TBLWT*- and TBLWT+* (Figures 111 to 113). Appendix A contains a detailed list of opcodes and instructions for the instruction set of the present invention & the material incorporated in Appendix A by reference for all purposes. 96779.doc 1339354 Content. The data contained in the IR is treated as an unsigned integer and the result is not stored in FSR2. There are four addressing modes: • Indirect (INDF); • Incremental/Decrement (FSR2 + ), (+FSR2) and (FSR2-) Interconnect modes; • Offset Interconnect mode (FSR2 + W, where W Content is used for offset);

• Has a text offset connection mode (FSR2+ text). The present invention includes an instruction set that, when invoked, executes one or more tasks on the microcontroller. The following describes several instructions. In special cases, such instructions may be invoked by, for example, a switch or other equivalent measure.

The "PUSHL" command pushes an 8-bit literal value onto the stack. The actual grammar of the PUSHL instruction is "PUSHL k", where 0 <= k <= 225. The call to this command does not affect the state of the microcontroller. The code of the PUSHL instruction is "1110 1010 kkkk kkkk", in which the 8-bit text is specified by the kkkk kkkk part of the instruction. Here, the 8-bit text is copied to the location where the second file selection register ("FSR2") is being addressed, and FSR2 is decremented. The "SUBFSR" command subtracts a 5-digit literal from a file selection register ("FSR"). The syntax of this command is "SUBFSR f, k", where 0 <= f <= 2 and 0 <= k < = 63. The call to this command does not affect the state of the microcontroller. The code of the command is "111 0 1 001 ffkk kkkk". When called, it subtracts 6-bit (unsigned) text from 96790.doc -43 - 1339354 FSRf and stores the result back to FSRf, where the command The "ff" part specifies a specific file selection register, and the "kk kkkk" part of the instruction specifies the text. The "SUBULNK" command subtracts a 5-digit literal from the second file selection register ("FSR2") and returns the resulting value. The syntax of this command is "SUBULNK k", where 0 <=k<= 63. The call to this command does not affect the state of the microcontroller. The command is encoded as "1110 1001 llkk kkkk", when called, it subtracts 6-bit (unsigned) text from FSR2, stores the result back into FSR2, and returns the result to the caller with the execution. The "ADDFSR" instruction adds a 5-digit literal to an FSR. The syntax of this instruction is "ADDFSR f,k", where 0 <= f <= 2 and 0 <= k <= 63. The state of the microcontroller is not affected by this instruction. The code of the instruction is "1110 1000 ffkk kkkk". When called, it adds 6-bit (unsigned) text to the slave FSRf and stores the resulting value back into FSRf, where the "ff" part of the instruction Specify a specific file selection register, and the "kk kkkk" part of the instruction specifies the text. The "ADDULNK" instruction adds a 5-digit literal to FSR2 and returns the result to the call return routine. The syntax of this instruction is "ADDULNK k", where 0 <= k <= 63. The call to this instruction does not affect the state of the microcontroller. The code of the instruction is "111 〇1 〇〇〇11 kk kkkk", where when invoked, a 6-bit (unsigned) text (which is specified by the "kk kkkk" portion of the instruction) is added to FSR2. The result is stored back to FSR2 and execution is returned to the pager. The "MOVSF" instruction stores a stack location to the general purpose register 96779.doc 1339354 ("GPR"). The syntax of this instruction is "MOVSF s,d", where 〇 <= s <= 127 and 0 <= d <== 4095. The call of this instruction does not affect the state of the microcontroller 5|. The code of the instruction is in the two words, where Word 1 is "111 〇丨〇丄i

Osss ssss"' and Word 2 is "1111 dddd dddd dddd", and the "sss ssss" part of the first character of the instruction specifies a source, and the "dddd dddd dddd" part of the second character specifies the destination . When the instruction is called, 'add the 7-bit literal value to the value in FSR2 to get the source address of an 8-bit value' and then copy the source address to a position specified by the 12-bit value d. The FSR2 value is not affected by the MOVSF instruction and the state of the microcontroller is not affected. The "MOVSS" instruction copies a stack position to another stack position. The syntax of the instruction is "MOVSS s,d", where 0 <= s <= 127 and 〇 <= d <= 127. The call to this instruction does not affect the state of the microcontroller. The encoding of the instruction is in the two words 'where Word 1 is "1110 l〇n lsss ssss", and Word 2 is "1111 χχχχ xddd dddd", and the "sss ssss" part of the first character of the instruction is specified A source, and the "ddd dddd" portion of the second character specifies the destination. When the instruction is invoked, a 7-bit literal value is added to the value in FSR2 to obtain a source address of an 8-bit value. The source address is then copied to the address by the address (the address is The 7-bit value is added to the value in FSR2 to determine the location specified. The fs‘R2 value is not affected by the M〇vss instruction and the state of the microcontroller is not affected. The "CALLW" command is an indirect call. The syntax of this command is "CALLW". The call to this instruction does not affect the state of the microcontroller. The code of this command is "〇〇〇〇〇〇〇〇〇〇〇1 〇1 〇〇", when the instruction is called, 'push the address of the instruction 96796.doc -45-1339354 to the hardware On the stack. Specifically, copy the value from the first scratchpad (eg PCLATU: PCLATH) to the higher 16-bit command of the program counter "pc" and the second register (eg w register "WREGj" The value in )) is copied to the lower 8-bit of the PC.

The invention is thus fully adapted to carry out the objects and advantages and advantages of the invention described herein. While the invention has been illustrated and described with reference to the exemplary embodiments of the present invention As is known to those skilled in the art, the present invention can be modified and modified to have a similar type and function. The specific embodiments of the invention have been described and illustrated by way of illustration Therefore, the invention is limited only by the spirit and scope of the appended claims, and the equivalents are fully recognized in all respects. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a prior art mid-level microcontroller unit. FIG. 2 is a schematic block diagram of a prior art Harvard architecture. FIG. 3 is a schematic block diagram of a prior art v〇n Neumann architecture. Figure 7 is a schematic diagram of the execution of multiple instructions; Figure 6 is a schematic block diagram of the core of the microcontroller of the present invention; Figure 7 is a timing diagram of the q-cycle activity of the present invention; 8 is a timing diagram of a clock/instruction cycle of the present invention; FIG. 9 is a flowchart of a command pipeline of the present invention; FIG. 10 is a flowchart of a command pipeline of the present invention; 96779.doc -46 - 1339354 FIG. 11 is an instruction of the present invention Figure 12 is a flow chart of a command pipeline of the present invention; Figure 13 is a flow chart of a command pipeline of the present invention; Figure 14 is a flow chart of a command pipeline of the present invention; Figure 15 is a block diagram of a state register of the present invention Figure 16 is a block diagram of the program counter of the present invention; the block diagram is a block diagram of the program of the present invention using the CALL^G〇T〇 instruction; Figure 18 is a block diagram of the stacked index register of the present invention; Figure 19 is the present invention Figure 20 is a block diagram of a stacked top high register of the present invention; Figure 21 is a block diagram of a stacked top low register of the present invention; Figure 23 illustrates the first call on the initialization stack of the present invention; Figure 24 illustrates the second consecutive call on the stack of the present invention; Figure 25 illustrates the 31st and 32nd consecutive CALLs on the stack of the present invention; Figure 26 illustrates a return p 〇 p operation on the stack of the present invention; the retrace Figure 275 shows the stack return of the stack underflow condition in the present invention; Figure 28 illustrates a stack on the stack of the present invention FIG. 29 illustrates a ρ〇ρ command on the stack of the present invention; FIG. 30 is a block diagram of the program memory map and stack of the present invention; FIG. 3 is a block diagram of the memory map of the present invention. Figure 32 is a block diagram of the memory map of the present invention; 96779.doc -47· 1339354 Figure 3 is a block diagram of the device memory map of the present invention in different program modes; Figure 34 is a block diagram illustrating the present invention Block diagram of MEMCON register; Figure 35 is a diagram illustrating the present invention Figure 36 is a block diagram of a 16-bit external memory connection configuration of the present invention; Figure 37 is a block diagram of an 8-bit external memory connection configuration of the present invention; 3 is a list of typical 埠 functions of the present invention; FIG. 39 is a timing diagram of an external program memory bus in the 16-bit mode of the present invention; FIG. 40 is an external program memory bus in the octet mode of the present invention. Figure 41 is a list of external bus cycle types of the present invention; Figure 42 is a schematic block diagram of the data memory mapping and instruction "&amp;" bits of the present invention; Figure 43 is a special function of the present invention. Figure 44 is a schematic diagram of the core special function register of the present invention; Figure 45 is a continuation of the core special function register of Figure 44; Figure 46 is a schematic block diagram of the direct short addressing mode of the present invention; Figure 47 is a schematic block diagram of the BSR operation of the present invention; Figure 48 is a schematic block diagram of the prison operation of the present invention during the simulation/test mode; Figure 49 is a block diagram of the direct strong addressing mode of the present invention; This hair Schematic block diagram of the direct strong addressing mode; 96779.doc • 48 · 1339354 Figure 5 1 is a schematic block diagram of the direct long addressing mode of the present invention; Figure 52 is a schematic block diagram of the interfacing mode of the present invention; Figure 45 is a schematic block diagram of the present invention; Figure 55 is a list of addressable symbols in the present invention; Figure 56 is a general format of the instructions of the present invention; Figure 58 is a partial list of the instruction set of the present invention; Figure 59 is a partial list of the instruction set of the present invention; Figure 60 is a bit group oriented file register operation of the present invention. Figure 61 is a flow chart of the operation (execution) of the byte-oriented file register of the present invention, and Figure 62 is a flow chart of the CLRF, NEGF, SETF (read) instructions of the present invention; Figure 63 is the present invention Flowchart of CLRF, NEGF, SETF (execution) instructions, Fig. 64 is a flow chart of DECFSZ, DCFSNZ, INCFSZ, ICFSNZ (draw) instructions of the present invention; Fig. 65 is a DECFSZ, DCFSNZ, INCFSZ, I of the present invention. <Desc/Clms Page number> Flowchart; 96779.doc -49- 1339354 Figure 68 is a flow chart of the MULWF (Draw) instruction of the present invention; Figure 69 is a flow chart of the MULWF (Execution) instruction of the present invention; Figure 70 is a MULFF of the present invention (撷Figure 71 is a flow chart of the MULFF (Execution 1) instruction of the present invention; Figure 72 is a flow chart of the MULFF (Execution 2) instruction of the present invention;

Figure 73 is a flow chart of the BCF, BSF, BTG (draw) instructions of the present invention; Figure 74 is a flow chart of the BCF, BSF, BTG (draw) instructions of the present invention; Figure 75 is a BTFSC and BTFSS of the present invention (Fig. Figure 76 is a flow chart of the BTFSC and BTFSS (execution) instructions of the present invention; Figure 77 is a flow chart of the text operation (capture) of the present invention; Figure 78 is a text operation of the present invention ( Figure 79 is a flow chart of the LFSR (Extraction) instruction of the present invention; Figure 80 is a flow chart of the LFSR (Execution 1) instruction of the present invention; and Figure 81 is an LFSR (Execution 2) instruction of the present invention. Figure 82 is a flow chart of the DAW (draw) instruction of the present invention;

Figure 83 is a flow chart of the DAW (execution) instruction of the present invention; Figure 84 is a flow chart of the MULLW (execution) instruction of the present invention; Figure 85 is a flow chart of the MULLW (execution) instruction of the present invention; Flowchart of the CLRWDT, HALT' RESET and SLEEP (intake) instructions of the invention; Figure 87 is a flow chart of the CLRWDT, HALT, RESET and SLEEP (execution) instructions; Figure 88 is the MOVELB of the present invention. Figure 30 is a flow chart of the MOVLB (execution) instruction of the present invention; 96779.doc -50-1339354 Figure 90 is a flow chart of the branch operation (taken) of the present invention; Flowchart of the branch operation (execution) of the present invention; Fig. 92 is a flowchart of the BRA and RCALL instructions of the present invention; Fig. 93 is a flowchart of the BRA and RCALL (execution) instructions of the present invention; FIG. 95 is a flowchart of a PUSH (execution) instruction of the present invention; FIG. 96 is a flowchart of a POP (Capture) instruction of the present invention; FIG. 97 is a flowchart of the present invention. Flowchart of POP (execution) instruction; Figure 98 is a RETURN and RETFIE (read) instruction of the present invention Figure 99 is a flow chart of the RETURN and RETFIE (execute) instructions of the present invention; Figure 100 is a flow chart of the RETLW (execution) instruction of the present invention; and Figure 101 is a flow chart of the RETLW (execution) instruction of the present invention. Figure 102 is a flow chart of a GOTO (Extract) instruction of the present invention; Figure 103 is a flow chart of a GOTO (Execution 1) instruction of the present invention; Figure 104 is a flow chart of a GOTO (Execution 2) instruction of the present invention; 105 is a flowchart of a CALL instruction of the present invention; FIG. 106 is a flowchart of a CALL (execution 1) instruction of the present invention; FIG. 107 is a flowchart of a CALL (execution 2) instruction of the present invention; Flowchart of the TBLRD*, TBLRD*+, TBLRD*· and TBLRD + * (take) instructions of the present invention; FIG. 109 is a TBLRD*, TBLRD*+, TBLRD*- and TBLRD+* of the present invention (execution 1 Flowchart of the instruction; 96779.doc -51 · 1339354 Figure 110 is a flow chart of the TBLRD*, TBLRD*+, TBLRD*- and TBLRD + * (execution 2) instructions of the present invention; Figure 111 is a TBLWT* of the present invention , TBLWT*+, TBLWT*- and TBLWT+* (draw) instructions flow chart; Figure 112 is the TBLWT*, TBLWT*+, TBLWT*- and TBLWT+ Flowchart of the (execution) instruction; Figure 113 is a flow chart of the TBLWT*, TBLWT*+, TBLWT*- and TBLWT+* (execution 2) instructions of the present invention; Figure 4 is an instruction decoding map of the present invention; 115 is a block diagram of an alternate paging scheme in accordance with the principles of the present invention. Figure 11 is a block diagram of an alternate paging scheme in accordance with the principles of the present invention. [Main component symbol description] 22 Data memory

24 CPU 26 program memory

34 CPU 36 Data and Program Memory 100 Microcontroller Core 102 Address Latches 104 Data Memory 106 Data Latching Benefits 108 Select Circuitry 110 Repository 112 Decoder 96779.doc -52- 1339354

118 Repository Select Scratchpad 120 FSR 121 FSR 122 FSR 124 Table Latch 126 IR Latch 128 Product Scratchpad 134 Hardware Multiplier 136 Operation (W) Scratchpad 140 Arithmetic and Logic Unit (ALU) 142 Arithmetic and Logic Unit (ALU) 144 Instruction Decoder 148 Table Indicator 152 ROM Latch 154 System Spool: Bank 158 Data Latch 160 Data or Program Memory 162 Address Latch 168 Program Counter (PC) 170 Stack 172 Stacking Indicators 174 Data Bus 176 PCLATU 178 PCLATH 96779.doc -53- 1339354

180 PCU 182 PCH 184 PCL

96779.doc •54·

Claims (1)

1339354 ____ Bamboo Year Y month W correction wood 10, the scope of application for patents: 1 · A microcontroller, which contains: . Central processing unit; : Section: Memory: it has a linearized address space and with the order The data storage system is divided into n repositories; the central processing unit comprises: a repository selection unit that accesses the repositories - or accesses a virtual repository, whereby the virtual repository combines the data Part of the memory space and the user-defined part of the two banks of memory carving. a hidden space 'and wherein the selected repository is formed - a scratchpad broadcast; wherein the user defines a local memory space mapped to any location in the poor memory; an arithmetic logic unit, The temporary register is lightly combined; a plurality of special function registers, - one of the special function registers stored in the storage library H in the poor memory, and the arithmetic logic unit a coupled work register; - a program counter register is located in the central processing unit; the program counter register is mapped in the data memory; and - a work register is located in the The central processing unit is affixed to the arithmetic logic unit _H temporary storage (4) is mapped in the data memory; 'where the micro controller has a finger for 栌 用 用 玄 玄 玄 玄 玄 玄4 sets 'At least one of the instructions includes one open, and the smart bit indicates the storage shoulder 96779-990824.doc, and the selection unit accesses one of the storages or the virtual storage. 4 &quot;Monthly item I of the micro-controller, wherein the instruction set includes an instruction having the code of Chuanxiong 1〇1〇kkkk kkkk 'When the instruction is invoked, an 8-bit text is copied to be selected by a file The location pointed to by the scratchpad is then made. The halal file selects the scratchpad to be decremented, and the text is specified in the portion of the instruction. 3. A requestor, such as a microcontroller, wherein the instruction set includes an instruction having an encoding 111/1001 ffkkkkkk, wherein when the instruction is invoked, a -6-bit unsigned text is subtracted from a file selection register to form - As a result, the result is stored in the (4) selection register, the text is specified in the kk kkkk portion of the instruction, and the file selection register is specified in the subscription portion of the instruction. 4. 5. The microcontroller of claim 1, wherein the instruction set includes an instruction having an encoding 1110 1001 llkkkkkk 'where the instruction is invoked, subtracting from an instance selection register - an unsigned 6 bit The text is formed to form a result, and the result is stored back to the file selection, and the text is specified in the kk kkkk portion of the instruction. The micro-controller of claim 1, wherein the instruction set includes an instruction 1 having an encoding UHM_ffkkkkkk, wherein when the instruction is invoked, an unsigned 6-bit text is added to a file selection register to form a result. Stored in the file selection register, the text is specified in the kk kkkk portion of the instruction, and the file selection register a is specified in the instruction of the instruction. 6. The microcontroller of claim 1 The instruction set includes an instruction having an encoding 96779-990824.doc 1339354 1110 1000 likkkkkk, wherein when the instruction is invoked, a 6-bit text specified by the kk kkkk portion of the instruction is added to a file selection temporary storage. To form a result and store the result back to the file selection register. 7. The microcontroller of claim 1, wherein the instruction set includes an instruction having an encoding 1110 1011 Osss ssss 1111 dddd dddd dddd, wherein when the instruction is invoked, an 8-bit value is copied to the 12 The destination specified by the bit value dddd dddd dddd specifies the location of the 8-bit value copied to the destination by adding the 7-bit literal value sss ssss to the value in a file selection register . 8. The microcontroller of claim 1, wherein the instruction set includes an instruction having an encoding 1110 1011 1 sss ssss 1111 xxxx xddd dddd, wherein when the instruction is invoked, an 8-bit value is copied to The position specified by the ddd dddd portion of the instruction determines the position of the 8-bit value by adding the 7-bit literal value SSS SSSS to the value in a file selection register. 9. The microcontroller of claim 1, wherein the instruction set includes an instruction having a code of 0000 〇〇〇〇 0001 〇 1 ,, wherein when the instruction is invoked, the address of the next instruction is pushed to Hardware stacking. 10. The microcontroller of claim 1, wherein the instruction set includes an instruction having a code of 0000 0000 0001 〇 1 ,, wherein when the instruction is invoked, the value from a first register is copied to a program The higher 16 bits of the counter are 'and a value in a second register is copied to the lower 8 bits of the program counter. 96779-990824.doc \, such as the requester's microcontroller, wherein the user-defined local memory space has an address range of 00h to 5Fh in the virtual repository, the local memory space of the first repository There is an address range of 60h h in the virtual repository, and the local memory space of the far second repository has an address range of 8〇h to FFh in the virtual repository. 12. The requestor's microcontroller 'further includes a programmable index bit operation to define a -first and second mode, wherein in the first mode the virtual: the repository does not have the data store In the case where the manufacturer defines the local memory peptide, the local memory space of the second repository is combined, and in the second mode, the virtual repository is in the case of the user-defined local memory space having the data memory. Combine the local memory space of the two repositories. 13_If the middleware program is executed, the bit is executed as a fuze. 14. The microcontroller of claim 12, wherein the program is contending. The index bit is executed by the software and the microcontroller of claim 12, which is executed in the switch actuation technique. 96779-990824.doc