JP2000188535A - タイミング回路 - Google Patents

タイミング回路

Info

Publication number
JP2000188535A
JP2000188535A JP11138419A JP13841999A JP2000188535A JP 2000188535 A JP2000188535 A JP 2000188535A JP 11138419 A JP11138419 A JP 11138419A JP 13841999 A JP13841999 A JP 13841999A JP 2000188535 A JP2000188535 A JP 2000188535A
Authority
JP
Japan
Prior art keywords
clock
clock tree
signal
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11138419A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000188535A5 (https=
Inventor
Allen C Brown
シー・アレン・ブラウン
Damir Smitlener
ダミーア・スミトレナー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2000188535A publication Critical patent/JP2000188535A/ja
Publication of JP2000188535A5 publication Critical patent/JP2000188535A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
JP11138419A 1998-06-03 1999-05-19 タイミング回路 Withdrawn JP2000188535A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/090,678 US6114877A (en) 1998-06-03 1998-06-03 Timing circuit utilizing a clock tree as a delay device
US090,678 1998-06-03

Publications (2)

Publication Number Publication Date
JP2000188535A true JP2000188535A (ja) 2000-07-04
JP2000188535A5 JP2000188535A5 (https=) 2006-07-13

Family

ID=22223815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11138419A Withdrawn JP2000188535A (ja) 1998-06-03 1999-05-19 タイミング回路

Country Status (5)

Country Link
US (1) US6114877A (https=)
EP (1) EP0962851B1 (https=)
JP (1) JP2000188535A (https=)
DE (1) DE69926308T2 (https=)
SG (1) SG77219A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1214788B1 (de) 1999-09-22 2003-03-26 Siemens Aktiengesellschaft Integrierter schaltkreis mit zumindest zwei taktsystemen
US6513149B1 (en) * 2000-03-31 2003-01-28 International Business Machines Corporation Routing balanced clock signals
US6933757B1 (en) * 2002-10-31 2005-08-23 Cypress Semiconductor Corporation Timing method and apparatus for integrated circuit device
US7581131B1 (en) * 2005-05-09 2009-08-25 National Semiconductor Corporation Method and system for balancing clock trees in a multi-voltage synchronous digital environment
US7486130B2 (en) * 2005-12-14 2009-02-03 Ember Corporation Clock skew compensation
US7479819B2 (en) * 2006-12-14 2009-01-20 International Business Machines Corporation Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees
US20080229266A1 (en) * 2006-12-14 2008-09-18 International Business Machines Corporation Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
US20080229265A1 (en) * 2006-12-14 2008-09-18 International Business Machines Corporation Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
JP2009140999A (ja) * 2007-12-04 2009-06-25 Toshiba Corp 半導体集積回路
US8181140B2 (en) * 2009-11-09 2012-05-15 Xilinx, Inc. T-coil network design for improved bandwidth and electrostatic discharge immunity

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023893A (en) * 1988-10-17 1991-06-11 Advanced Micro Devices, Inc. Two phase non-overlapping clock counter circuit to be used in an integrated circuit
JPH0824143B2 (ja) * 1989-02-08 1996-03-06 株式会社東芝 集積回路の配置配線方式
US5124571A (en) * 1991-03-29 1992-06-23 International Business Machines Corporation Data processing system having four phase clocks generated separately on each processor chip
US5430397A (en) * 1993-01-27 1995-07-04 Hitachi, Ltd. Intra-LSI clock distribution circuit
JP2959372B2 (ja) * 1993-12-03 1999-10-06 日本電気株式会社 クロック生成回路
US5638542A (en) * 1993-12-29 1997-06-10 Intel Corporation Low power non-overlap two phase complementary clock unit using synchronous delay line
US5517147A (en) * 1994-11-17 1996-05-14 Unisys Corporation Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits
US5635857A (en) * 1994-12-08 1997-06-03 Unisys Corporation IC chip using a common multiplexor logic element for performing logic operations
US5617047A (en) * 1995-06-06 1997-04-01 International Business Machines Corporation Reset and pulse width control circuits for high-performance multi-port memories and register files
US5717229A (en) * 1996-03-26 1998-02-10 Intel Corporation Method and apparatus for routing a clock tree in an integrated circuit package

Also Published As

Publication number Publication date
EP0962851B1 (en) 2005-07-27
DE69926308T2 (de) 2006-05-24
SG77219A1 (en) 2000-12-19
EP0962851A2 (en) 1999-12-08
US6114877A (en) 2000-09-05
DE69926308D1 (de) 2005-09-01
EP0962851A3 (en) 2002-01-16

Similar Documents

Publication Publication Date Title
US4879481A (en) Dual I/O macrocell for high speed synchronous state machine
US5103114A (en) Circuit technique for creating predetermined duty cycle
US8253466B2 (en) Clock generators for generation of in-phase and quadrature clock signals
US5402012A (en) Sequentially clocked domino-logic cells
JP2003501935A (ja) 四相クロック構成用シングルレール・ドミノロジック
JP2000188535A (ja) タイミング回路
US4896057A (en) High-speed dynamic domino circuit implemented with gaas mesfets
US5821775A (en) Method and apparatus to interface monotonic and non-monotonic domino logic
JP2002245109A (ja) 半導体集積回路の設計方法及び設計システム
JP2002055732A (ja) デスキュー回路を有するクロック生成器
US5818366A (en) Reduced transistor-count data storage and multiplexing system
TWI287187B (en) Opposite-phase scheme for peak current reduction
JP2611034B2 (ja) 遅延回路
US4988892A (en) Method and circuit for generating dependent clock signals
US6661262B1 (en) Frequency doubling two-phase clock generation circuit
JPH07262237A (ja) クロックスキュー制御方式
JP4412788B2 (ja) パラレル−シリアル変換回路
JP2786463B2 (ja) フリップフロップ回路
JPH04233014A (ja) コンピュータ・システム
US5856746A (en) Logic speed-up by selecting true/false combinations with the slowest logic signal
US6380775B1 (en) Multiplexed distribution system for CMOS signals
EP1146413A2 (en) Data signal that mimics a clock signals
JPH0212411B2 (https=)
JPS62189811A (ja) Ｃｍｏｓクロツク回路
Yoo et al. Timing constraints for high-speed counterflow-clocked pipelining

Legal Events

Date Code Title Description
RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20060413

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060517

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060517

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060518

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20060629

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061201

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20070608