JP2000183706A - Clock distribution method and its circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock distribution method and its circuit by which a clock can be distributed at a low cost with a simple method. SOLUTION: A transmitter side S1 consists of an oscillator 5 that outputs a clock 1, a frequency divider 6 that divides the frequency of the clock 1 to produce a clock 2, a frequency divider 7 that divides the frequency of the clock 2 to produce a clock 3, a frequency divider 8 that divides the frequency of the clock 3 to produce a clock 4, a pulse generating circuit 9 that uses the clocks 1, 2, 3, 4 to produce a pulse multiplexed output, and buffer circuits 10, 11 that distributes the generated pulse multiplexed output and the clock 1 to other units. On the other hand, a receiver side R1 consists of buffer circuits 12, 13 that receive the distributed clock 1 and the distributed pulse multiplexed output, and a pulse recovery circuit 14 that recovers the original single clock 3 and the original single clock 4 from the received pulse multiplexed output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock distribution method and circuit, and more particularly to a clock distribution method and circuit for distributing a plurality of phase-synchronized clocks among a plurality of units in a transmission device or the like.

[0002]

2. Description of the Related Art Conventionally, in a transmission apparatus or the like, the apparatus is often divided and accommodated in a plurality of units called a subrack in which a plurality of packages are mounted. At this time, each unit requires a unified clock as a device, and receives a clock distribution from a clock generation unit. In a system that simply requires the same frequency, this clock receives only the earliest clock, and the other required clocks need only be generated by dividing the received clock. Synchronous clocks are often required, and the required number of clocks are individually received.

FIG. 5 is a schematic diagram showing a conventional clock distribution method and circuit configuration. FIG. 5A is composed of a unit 1 and a unit 2, and a clock generation unit provided in the unit 1 distributes four types of phase-synchronized clocks to the unit 2 through four lines. The method of performing unbalanced transmission of a logic level by TTL or the like using such four lines has a high possibility of malfunction due to external noise. Therefore, V.1 of the recommendation by ITU (International Telecommunication Union) has been adopted. There is a method of employing the balanced transmission method described in No. 11, but the number of lines for distributing the clock is twice the number of lines required for unbalanced transmission, and a total of eight lines are required.

On the other hand, between the units, there is a large amount of information to be transmitted and received in addition to the clock distribution. For example, main signal data, monitoring information such as alarms, control information, etc. The number is increasing. Therefore, conventionally, a method of reducing the number of lines used for clock distribution to reduce the number of connectors has been considered. In this method, as shown in FIG. 5B, the earliest of a plurality of clocks is used as a main clock, and the code configuration is a bipolar code. It is alternately converted into two levels of +1 and -1. The other clocks are distributed by causing the violation of the bipolar coding rule of the main clock at the timing of the corresponding clock, and the number of lines required for clock distribution is one for unbalanced transmission.

[0005]

However, the above-described method for distributing a clock using a bipolar code needs to convert the main clock into three values, that is, +1, 0, and -1. And an expensive integrated circuit, which is one of the factors that increase the cost of the transmission device. SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional clock distribution method and circuit as described above, and has as its object to provide a low-cost clock distribution method and circuit by a simple method. I do.

[0006]

In order to achieve the above object, a clock distribution method and circuit according to the present invention have the following arrangement. The clock distribution method according to claim 1 is a method for distributing a plurality of clocks among a plurality of units constituting an apparatus, wherein a clock having a second highest frequency of the plurality of clocks is used as a main clock on the transmission side. ,
By counting the timing at which the first highest frequency clock operates, each pulse conversion point of the third to nth highest frequency clocks is detected, and one of the main clocks corresponding to the conversion point is detected. The pulse width is changed to be shorter or longer, and the change is distributed as a pulse multiplexed output including pulse conversion point information corresponding to each of the third to n-th highest frequencies together with the first highest-frequency clock, and received. On the side, after inputting a pulse multiplexing input and a first highest frequency clock, the timing at which the second highest frequency main clock, which is a multiplexed pulse, operates first. The third counting is performed by counting at a high frequency operation timing and determining whether one pulse width is short or long at a predetermined timing of the main clock. From detecting the n-th high frequency of each of the pulse changing point, configured to reproduce the high frequency clock to the n-th from the third.

According to a second aspect of the present invention, there is provided a clock distributing circuit for distributing a plurality of clocks among a plurality of units constituting an apparatus, wherein a transmitting side outputs a first clock having a first highest frequency. And a plurality of frequency dividers for generating second to third to n-th clocks by dividing the output of the oscillator, and a plurality of frequency dividers for detecting pulse rising points of the third to n-th clocks. A pulse detector, a plurality of pulse position detectors for detecting a time for setting the pulse width of the second clock to a predetermined time shorter or longer from a rising point, and the pulse position using the second clock as a main clock. A plurality of pulse generators for generating a pulse whose pulse width of the main clock is shortened or lengthened to a predetermined value by a set time obtained from an output of the detector; And a second AND clock to obtain a pulse multiplexed output, and a buffer circuit for distributing the pulse multiplexed output and the first highest frequency clock to other units. On the side, a buffer circuit that receives a pulse multiplexed input and the first highest clock from another unit having a clock distribution function, a pulse detection unit that detects a pulse rising point of the pulse multiplexed input, A pulse position detection unit that determines whether the pulse width of the main clock assigned to the third to n-th clocks is short or long based on the detected pulse rising point; and detection of the pulse position detection unit. A plurality of pulse generators for generating the original third to n-th clocks based on the result.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments. FIG. 1 is a block diagram showing an embodiment of a clock distribution method and circuit according to the present invention. In the figure, a transmission side S1 is a clock 1 serving as a reference frequency.
, A frequency divider 6 that divides clock 1 to generate clock 2, a frequency divider 7 that divides clock 2 to generate clock 3, and a frequency divider that divides clock 3 A frequency divider 8 for generating a clock 4 and clocks 1, 2, 3, 4
Pulse generating circuit 9 for generating a pulse multiplexed output by using
And buffer circuits 10 and 11 for distributing the generated pulse multiplexed output and clock 1 to other units.

On the other hand, the receiving side R1 is provided with buffer circuits 12, 13 for receiving the clock 1 distributed from another unit having the clock distribution function and the pulse multiplexed input.
And a pulse regenerating circuit 14 for regenerating the original single clocks 3 and 4 from the received pulse multiplexed input.

Next, for the sake of simplicity, the first highest frequency clock 1 is set to 2048 kHz and the second highest frequency clock 2 is set to 8 kHz as synchronized clocks distributed between the units. , The third highest frequency clock 3 is set to 0.4 kHz, and the fourth highest frequency clock 4 is set to 1 Hz.
In this embodiment, four clocks are used. However, the number of clocks is not limited to this, and a plurality of clocks can be multiplexed.

The clock distribution method and circuit configured as described above operate as follows. On the transmitting side S1,
The oscillator 5 is composed of a reference frequency oscillator constituted by a crystal oscillator or the like, and outputs a clock 1 of 2048 kHz. The frequency divider 6 divides the frequency of the clock 1 by 1/256 and outputs 8 kHz that is the clock 2. The frequency divider 7 divides the clock 2 by 1/20 and generates a clock 3 of 0.4 kHz.
Output z. The frequency divider 8 divides the frequency of the clock 3 by 1/400 and outputs 1 Hz to be the clock 4. The pulse generation circuit 9 generates an 8k-pulse multiplexed output by shortening or lengthening the pulse width of the 8k-pulse with the clock 2 as the main clock corresponding to the pulse rising points of the clocks 3 and 4. The 8k pulse multiplexed output is supplied to buffer circuits 10 and 11 together with clock 1 of 2048 kHz to distribute the clock to other units.
Output via. The details of the pulse generation circuit 9 will be described later.

On the other hand, on the receiving side R1, the clock 1 sent from the transmitting side S1 of the unit having the clock distribution function and the 8k pulse multiplexed input are level-corrected via the buffer circuits 12 and 13. Enter later.
Clock 1 and 8 kHz obtained from the 8 k pulse multiplexed input are distributed to the unit as clock 2. Also, 8k
The pulse multiplexing input determines whether the pulse width of the 8k pulse is short or long at a predetermined time width by the pulse regenerating circuit 14, and the clock 3 and the clock 4 correspond to the pulse width.
Separated and regenerated and distributed in the unit. The details of the pulse reproduction circuit 14 will be described later.

Next, the operation of the pulse generation circuit 9 and the pulse reproduction circuit 14 will be described with reference to a timing distribution chart shown in FIG. 2 and a timing chart showing the operation of the circuit. (A) shows an original waveform of an 8 kHz clock serving as a main clock, and a reference waveform having an amplitude ratio of “1” and “0” levels of 1: 1.

FIG. 3B shows an enlarged waveform of the main clock.
The time to complete the "1" and "0" levels is 62.5 each
μs. Therefore, in order to multiplex a clock lower than the frequency of the main clock with the main clock, the time ratio of the level indicated by "1" of the main clock is changed to 1 / n corresponding to the pulse conversion point of the multiplexed clock. . In the present embodiment, in order to multiplex the clock 3 consisting of 0.4 kHz to the main clock (8 kHz), 20 pulses of the main clock (8 kHz ÷ 0.4 kHz) as shown in m1.
= 20) once the level time of “1” is 3/4, that is, 4
6.875 μs is set. Similarly, in order to multiplex the clock 4 of 1 Hz to the main clock, as shown in m2, 20 × 400 pulses of the main clock (8 kHzｋ1 Hz =
8000) once, the level time of "1" is halved, that is,
31.25 μs. Therefore, the main clock consisting of 8 kHz has a level time of “1” of 46.8 once every 20 times.
The waveform changes to 75 μs and to 31.25 μs once every 8000 times.

(C) shows the case where the clock recovery circuit is 8k
Clock 3 consisting of 0.4 kHz from pulse multiplex input
It is a figure in the case of reproducing | regenerating. The time width in which the pulse of the 8k-pulse multiplexed input is at level "1" is detected, and it is determined whether the time at which the level is "1" is 62.5 μs, which is the standard time, or short. The determination point is that the clock 1 of 2048 kHz is counted from the rising of the pulse of the 8k pulse multiplex input, the position of 54.6875 μs indicated by p1 in the 112th cycle is detected, and the determination is made at that position. The pulse level at the judgment point is "0"
Is determined to be a level conversion point of the clock 3 of 0.4 kHz, and the conversion point is detected at a cycle of 0.4 kHz. Therefore, the pulse of the clock 3 is reproduced using the conversion point.

(D) shows the case where the clock recovery circuit is 8k
FIG. 9 is a diagram in the case of reproducing a clock 4 of 1 Hz from a pulse multiplex input. The time width in which the pulse of the 8k-pulse multiplexed input is at level "1" is detected, and it is determined whether the time at which the level is "1" is 62.5 μs, which is the standard time, or short. The determination point is that the clock 1 of 2048 kHz is counted from the rising edge of the pulse of the 8k pulse multiplex input, and the 39.
The position of 0625 μs is detected, and the judgment is made at that position.
If the level of the pulse at the determination point is "0", it is determined that the level of the clock 4 is 1 Hz, and the conversion point is detected at a cycle of 1 Hz. Regenerate the pulse.

Next, the pulse generating circuit 9 and the pulse reproducing circuit 14 will be described in detail. FIG. 3 is a block diagram showing one embodiment of the pulse generation circuit according to the present invention. In the figure, a pulse generation circuit 9 includes a pulse detection unit 15 that detects a 0.4 kHz pulse rising point, a count unit 16 that counts clock 1, and a pulse that detects a specific count value of the output of the count unit 16. Position detectors 17, 18
A pulse generator 19 for generating a 0.4 kHz pulse multiplexing output from the two outputs of the pulse position detectors 17 and 18; a pulse detector 20 for detecting the rising point of a 1 Hz pulse; A 1 Hz pulse multiplexing output is created by the two outputs of the counting unit 21, the pulse position detecting units 22 and 23 for detecting a specific count value of the output of the counting unit 21, and the pulse position detecting units 22 and 23. A pulse generating unit 24, a phase adjusting unit 25 for matching the phase of 8 kHz of the main clock and two pulse multiplexing outputs during pulse multiplexing, and 8 kHz as the main clock using the two pulse multiplexing outputs. The AND circuit 26 performs pulse multiplexing.

The pulse generation circuit 9 configured as described above operates as follows. The pulse detection unit 15 outputs the clock 3
And 8 kHz at the rising edge of the 0.4 kHz pulse.
z, and outputs a pulse having a pulse width of z.
Count.

Next, the pulse position detector 17 detects the point at which the output of the counting unit 16 becomes the pulse rising edge of the clock 3, that is, the timing at which the count value becomes 1, and the output of the counting unit 16 outputs the count value 96. That is, the timing at which 46.875 μs has elapsed from the rising point of the clock 3 is detected by the pulse position detection unit 18.

The flip-flop is set and reset at the timings detected by the pulse position detectors 17 and 18, so that the frequency of the main clock is 8 kHz.
A pulse having a pulse width of 46.875 μs with a time of 62.5 μs, which is the standard pulse width of
The pulse is generated by the pulse generator 19 in the cycle of.

Next, the pulse detector 20 receives the clock 4 and outputs a pulse having a pulse width of 8 kHz at every rising edge of the 1 Hz pulse. Counts clock 1 by Next, the pulse position detecting unit 22 detects the timing at which the output of the counting unit 21 becomes the rising point of the clock 4, that is, the count value 1, and further, the output of the counting unit 21 is the count value 64, that is, the clock. The timing at which 31.25 μs has elapsed from the rising point of No. 4 is detected by the pulse position detecting unit 23.

By setting and resetting the flip-flop with the timing detected by the pulse position detecting units 22 and 23, 8 kHz as the main clock is set.
The pulse generation unit 24 generates a pulse having a pulse width of 31.25 μs at a cycle of 1 Hz, which is obtained by halving the time of 62.5 μs, which is the standard pulse width. Next, the phase of the clock 2 composed of 8 kHz is adjusted by the phase adjusting unit 25 so as to match the output phase of the pulse generating units 19 and 24 generated as described above, and further the pulse generating units 19 and 24 are adjusted.
And the output of the phase adjusting unit 25 is added by the AND circuit unit 26 to obtain an 8k pulse multiplexed output.

FIG. 4 is a block diagram showing one embodiment of the pulse reproducing circuit according to the present invention. In the figure, a pulse reproducing circuit 14 includes a pulse detecting section 27 for detecting a rising edge of a pulse of an inputted 8k pulse multiplexed input, a counting section 28 for counting an input clock 1, and a counting section 28 for detecting a clock 3. A pulse position detecting section 29 for detecting a specific count value of the output of the signal generator 28;
Pulse generating unit 30 for generating a clock 3 consisting of Hz
And a pulse position detecting unit 3 for detecting a specific count value of the output of the counting unit 28 in order to detect the clock 4.
1 and a pulse generator 32 that generates a clock 4 of 1 Hz based on the specific count value detected by the pulse position detector 31.

The pulse reproducing unit 14 configured as described above operates as follows. In the pulse detector 27, 8
A k-pulse multiplex input is input, and a rising point of a 8 kHz pulse is detected. The counting section 28 counts the clock 1 while the pulse is at the “1” level from the rising point of the 8 kHz pulse, and the pulse position detecting section 29 detects the clock 1 from the rising point of the 8 kHz pulse based on the count value. The position of the check point p1 separated by .6875 μs is detected. In the pulse generation unit 30, the time width of the level “1” of the 8 kHz pulse is set to the standard 62.
A pulse width of 46.875 μ, which is 3/4 of 5 μs
s is determined.

In the determination, it is determined whether the level of the 8 kHz pulse is "0" or "1" at the position of p1, and if it is "0", it is determined that the pulse of the clock 3 is a rising point. Therefore, the determination result of “0” is 0.4 kHz.
Since it occurs at z cycles, 0.4 k
A clock 3 consisting of Hz is created. Similarly, in the pulse position detecting section 31, 8 kHz as the main clock is used.
Is determined to be 31.25 μs, which is の of the standard value 62.5 μs.

The detection is performed at checkpoint P2 39.0625 μs away from the rising point of the 8 kHz pulse.
The pulse generator 32 generates a clock 4 of 1 Hz by detecting a pulse having a 1/2 pulse width generated in a 1 Hz cycle.

[0027]

As described above, according to the present invention, the clock distribution circuit can be realized by combining a general-purpose low-cost integrated circuit with the pulse width of the main clock. By changing or increasing the number of detection points of the main clock, it is possible to transmit a larger number of clocks, which is very effective in designing and manufacturing a transmission device and the like.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a clock distribution method and circuit according to the present invention.

FIG. 2 is a timing chart illustrating the operation of a clock distribution method and circuit according to the present invention.

FIG. 3 is a configuration diagram showing one embodiment of a pulse generation circuit according to the present invention.

FIG. 4 is a configuration diagram showing an embodiment of a pulse reproduction circuit according to the present invention.

FIG. 5 is a schematic diagram showing a conventional clock distribution method and circuit configuration.

[Explanation of symbols]

1, 2, 3, 4, ... unit, 5 ... oscillator, 6,
7, 8 ··· divider, 9 ··· pulse generation circuit, 10, 1
1. buffer circuit, 12, 13 buffer circuit, 14. pulse regenerating circuit, 15 pulse detector, 16 count unit, 17, 18 pulse position detector, 19 pulse generator , 20..Pulse detector, 21..Counter, 22,23..Pulse position detector, 24..Pulse generator, 25..Phase adjuster, 26..AND circuit, 27..Pulse Detector, 28..Counter, 29..Pulse position detector, 30..Pulse generator, 31..Pulse position detector, 32..Pulse generator

Claims (2)

[Claims] In a method for distributing a plurality of clocks among a plurality of units constituting an apparatus, a clock having a second highest frequency among the plurality of clocks is used as a main clock, and a first highest clock is used as a main clock. Each pulse conversion point of the third to n-th highest frequency clocks is detected by counting the timing at which the clock of the frequency operates, and one pulse width of the main clock is shortened or corresponding to the conversion point. Long, and the change is distributed as a pulse multiplexed output including pulse conversion point information corresponding to each of the third to n-th highest frequencies together with the first highest-frequency clock. After inputting the pulse multiplexing input and the first highest frequency clock, the second highest frequency main clock, which is a multiplexed pulse, operates. Is counted based on the operation timing of the first highest frequency, and it is determined whether one pulse width is short or long at a predetermined timing of the main clock, thereby determining each of the third to nth highest frequencies. A clock distribution method comprising detecting a pulse change point and reproducing a clock having a third to n-th highest frequency. 2. A circuit for distributing a plurality of clocks among a plurality of units constituting an apparatus, comprising: an oscillator for outputting a first clock having a first highest frequency; A plurality of frequency dividers for generating second, third to n-th clocks by dividing the frequency, a plurality of pulse detectors for detecting pulse rising points of the third to n-th clocks, and a second clock A plurality of pulse position detectors for detecting a time for setting the pulse width to a predetermined time shorter or longer from the rising point, and a set time obtained from the output of the pulse position detector using the second clock as a main clock. A plurality of pulse generators for generating a pulse whose pulse width of the main clock is shortened or lengthened to a predetermined value; and a pulse multiplexing unit which adds an output of the plurality of pulse generators and a second clock to generate a pulse. An AND gate for obtaining an output, and a buffer circuit for distributing the pulse multiplexed output and the first highest frequency clock to other units, respectively, and on the receiving side, a pulse multiplexed input and A buffer circuit that receives the first highest clock from another unit having a clock distribution function, a pulse detector that detects a pulse rising point of a pulse multiplexed input, and a third based on the detected pulse rising point. A pulse position detecting unit that determines whether the pulse width of the main clock assigned to the first to n-th clocks is short or long, and the third to n-th original signals based on the detection result of the pulse position detecting unit. A clock distribution circuit comprising a plurality of pulse generation units for generating a clock.