KR200205011Y1 - A supporting circuit for ssm bit - Google Patents

Abstract

The present invention relates to an SSM bit support circuit for indicating the quality of a DOTS signal provided as a synchronous reference clock signal from a transmission device. In particular, the present invention relates to an SSM bit support circuit that does not require a CPU and is applied from a synchronous clock signal source. A PLL for regenerating and outputting a reference clock signal as a stable reference clock signal, a frame information generator for inserting and outputting frame information so that the reference clock signal applied from the PLL is classified in units of frames, and a reference clock signal applied from the PLL. By analyzing, the SSM bit generator for generating a quality class message, the CRC controller for generating a CRC check signal by analyzing a reference clock signal applied from the PLL, the PLL, the frame information generator, the SSM bit generator, and the CRC controller The framer outputs a reference clock signal in which a quality grade is recorded by each applied signal. Due to the feature, the expensive central processing unit is not used, thereby reducing the price, generating a DOTS signal even if a failure occurs in the central processing unit, and outputting a synchronous reference clock signal to the connected transmission equipment in the following order. And since it is not under the control of the central processing unit, there is an industrial and industrial use effect of reducing the load of the central processing unit and thus improving the reliability of the transmission equipment.

Description

S SUPPORTING CIRCUIT FOR SSM BIT}

The present invention relates to an SSM bit support circuit for indicating the quality of a digital office timing supply (DOTS) signal provided as a reference clock signal or a clock synchronization source in a transmission device, and in particular, does not require a CPU. SSM bit support circuit.

All transmission equipments used in our country are licensed and used as reference clock source signals, which are managed and provided by the country. These signals are called DOTS signals. Display the quality grade of accuracy by the process received through the SSM (Synchronization Status Message) signal, the SSM signal is generated by the corresponding transmission equipment receiving the DOTS signal, NFAS to the transmission equipment connected in the following order Output as (None Frame Alignment Signal) signal.

Below. A conventional SSM bit support circuit will be described with reference to the accompanying drawings.

Attached for the description of the prior art, FIG. 1 is a functional block diagram of the SSM bit support circuit according to the prior art.

Referring to FIG. 1, the conventional SSM bit support circuit includes a phase locked loop (PLL) circuit 10 for receiving DOTS of a synchronous clock signal source and outputting a reference clock signal of 2 Mbps;

A framer for generating the quality or grade of the DOTS by a control signal while simultaneously applying the reference synchronous clock signal source DOTS received from the PLL 10 to a transmission device connected to the next stage in succession. 20,

A central processing unit (CPU) 30 is applied to the framer 20 to control and monitor the data signal and the address signal to generate quality information of the DOTS signal.

Hereinafter, the prior art having the above-described configuration will be described in detail with reference to the accompanying drawings. The PLL 10, which has received the 2 Mbps clock signal of the DOTS signal from the synchronous clock signal source, is synchronized with the DOTS clock signal. Outputs a signal having a stable level, and transmits the 2 Mbps signal to the framer 20 so as to output the synchronous clock signal source DOTS signal to the connected transmission equipment in the following order. Is authorized.

The CPU 30 analyzes the DOTS signal, determines a grade according to quality, and applies the data signal to the framer 20 as a data signal.

The quality indication according to the class of the DOTS signal as described above is displayed in each odd frame among all 16 frames of the 2 Mbps clock signal NFAS (None Frame Alignment Signal), and 0 in each odd frame among all odd frames. The signals recorded in the 4th, 5th, 6th, 7th and 8th bits (Bit) in the time slot and among the 0 time slots, and the signals recorded in the quality indication are called SSM (Synchronous Status Message) bits, It is recorded by the address signal applied to the framer 20 from the processing unit 30.

The framer 20 may include a data processor indicating the quality of the DOTS synchronous clock signal source and a central processor 30 so that the data signal is recorded in each zero timeslot of each odd frame, in particular in the SSM bit. Chip select must be applied from

As described above, the DOTS signal and the SSM bit signal output from the framer 20 are applied to the transmission equipment connected in the following order, and the transmission equipment connected in the next order analyzes the applied SSM bits, thereby analyzing the quality of the DOTS signal. You can check it.

As described above, the DOTS signal is a framed all one signal in which a signal of '1' is recorded in the corresponding clock, and the checking of the quality is for using a good quality DOTS signal. The signal may be transmitted through various paths, for example, when the DOTS signal is supplied from Seoul and received from Jeju Island, and the quality of the DOTS signal transmitted through the Seoul-Busan-Jeju route and the Seoul-Daejeon-Daegu-Busan-Jeju This is because there is a difference in the quality of the DOTS signal transmitted in the path of.

However, in the SSM bit support circuit according to the related art having the above-described configuration, since the central processing unit 30 is necessary and the data signal, the address signal, and the chip selection signal must be received from the central processing unit 30, An additional circuit such as a bus for transmitting a signal is required, and when a failure occurs in the central processing unit 30, there is a problem in that the SSM bit cannot be supported or set.

In addition, there is a problem of concentrating the load in the central processing unit 30.

It is an object of the present invention to provide a hardware circuit configuration for writing frame information in a zero timeslot without using a central processing unit in supporting SSM bits.

The present invention devised to achieve the above object is a PEL to regenerate and output the reference clock signal applied from the synchronous clock signal source as a stable reference clock signal, and the reference clock signal applied from the PEL frame unit A frame information generator for inserting and outputting frame information so as to be classified into an RS, an SM bit generator for generating a quality grade message by analyzing a reference clock signal applied from the PL, and a reference clock applied from the PL A reference clock signal in which a quality grade is recorded by the signals received from the sialc controller, the PLS, the frame information generator, the SM bit generator, and the sialc controller, respectively. There is a feature consisting of a framer to output.

1 is a functional block diagram of a conventional SSM bit support circuit,

2 is a functional block diagram of an SSM bit support circuit according to the present invention.

** Explanation of symbols on the main parts of the drawing **

10: PLL 20: Framer

30: central processing unit 40: frame information generation unit

50: SSM bit generation unit 60: CRC control unit

Hereinafter, with reference to the accompanying drawings will be described the SM bit support circuit according to the technology of the present invention.

Attached to explain the technique of the present invention, Figure 2 is a functional block diagram of the SSM bit support circuit according to the present invention.

Referring to FIG. 2, the SSM bit support circuit according to the present invention provides a reference clock signal applied from a synchronous clock signal source (DOTS: Digital Office Timing Supply) managed by a state. Phase Locked Loop (PLL) 10 for reforming and outputting a reference clock signal having a stable duration, and

A frame information generator 40 for inserting and outputting frame information by allowing the DOTS signal of the reference clock signal applied from the PLL 10 to be divided in units of HDB3 frames, and

An SSM bit generation unit 50 for generating a SSM (Synchronization Status Message) message bit indicating a quality class such as clock signal accuracy by analyzing a DOTS signal which is a reference clock signal applied from the PLL 10;

A CRC controller 60 for generating a check redundancy check (CRC) test signal by analyzing a DOTS signal which is a reference clock signal applied from the PLL 10;

The reference clock signal in which the quality class of the DOTS signal is recorded is received by signals received from the PLL 10, the frame information generator 40, the SSM bit generator 50, and the CRC controller 60, respectively. It consists of a framer (FRAMER) 20 to output to the transmission equipment connected to.

Hereinafter, the SSM bit support circuit according to the present invention having the above configuration will be described in detail with reference to the accompanying drawings.

The frame information generation unit 40 receives a DOTS signal of 2 M bps, which is a synchronous reference clock signal source managed and supplied by a country, and stabilizes a level and a period to output a 2 Mbps signal as a reference clock signal. And SSM bit generator 50 and CRC controller 60, respectively, and output to framer 20 at the same time.

The frame information generation unit 40 receiving the 2 Mbps reference clock signal from the PLL 10 has 30 time slots (i.e., 30 time slots) in which the 2 Mbps signal is suitable for the HDB3 format. The unit forms one frame unit, and the frame as described above is composed of 16 frames. The frame information is inserted into the synchronous reference clock signal and output.

In addition, the SSM bit generation unit 50 analyzes and processes the 2 Mbps synchronization reference signal applied from the PLL 10 to generate an SSM message bit signal indicating the quality class based on the accuracy of the DOTS signal.

The CRC controller 60, which is simultaneously supplied with the 2 Mbps synchronization reference clock signal from the PLL 10, checks whether all bits of the DOTS signal, which is a framed all one signal, are at a '1' level. In addition, a CRC test signal is generated and output to check and correct an error occurring in the transmission process at the receiving end.

The frame information generation unit 40, the SSM bit generation unit 50, and the CRC control unit 60 synchronize the 2 Mbps clock signal applied from the PLL 10 and input the output signal to the framer 20.

The framer 20 is synchronized with the clock signal of the PLL 10, and the odd number of HDB3 frame signals received from the frame information generator 40 is converted into the SSM bits applied from the SSM bit generator 50. Odd) to be inserted into 4, 5, 6, 7, and 8 bits of a '0' time-slot among the frames, and to combine the CRC check signal applied from the CRC controller 60 to a corresponding position. do.

The framer 20 outputs the combined HDB3 signal as a DOTS signal, which is a synchronous reference clock signal, using a TX TIP terminal and a TX RING terminal to transmission equipment connected in the following order.

Therefore, the SSM bit support circuit according to the present invention having the above-described configuration does not need to use the central processing unit (CPU) 30, so that even if a failure occurs in the central processing unit (CPU), there is no problem in generating the DOTS signal. In addition, the load of the central processing unit (CPU) serves to reduce the load.

Since the present invention of the above-described configuration does not use an expensive central processing unit, the price is reduced, and even if a failure occurs in the central processing unit, a DOTS signal is generated and a synchronous reference clock signal is output to the connected transmission equipment in the following order. It can work.

In addition, since it is not controlled by the central processing unit, there is an industrial and industrial use effect of reducing the load of the central processing unit and thus improving the reliability of the transmission equipment.

Claims (1)

PIEL which regenerates and outputs the reference clock signal applied from the synchronous clock signal source as a stable reference clock signal; A frame information generator for inserting and outputting frame information so that the reference clock signal applied from the PEL is divided into frames; An SM bit generator for generating a quality grade message by analyzing a reference clock signal applied from the PL; A sialsi controller configured to generate a sialsi test signal by analyzing a reference clock signal applied from the PL; The SM bit support circuit comprises a framer for outputting a reference clock signal in which a quality grade is recorded by signals applied from the PLL, the frame information generator, the SM bit generator, and the sialc controller. .