KR200159812Y1 - Matching circuit of personal computer and exchange processor bus - Google Patents

Abstract

An object of the present invention is to provide a suitable circuit between a personal computer and an exchange processor bus having a self-diagnosis circuit and integrated components.

The matching circuit between the personal computer and the switch processor bus according to the present invention includes a data matching unit 22 serving as a bidirectional buffer, a data receiving unit, a data transmitting unit, a mode / address transmitting unit, an input / output port decoder, a bus selecting unit, And a matching circuit between a personal computer including a signal converter 28 and a clock generator 29 and a processor bus of an exchange, wherein the data receiver, data transmitter, mode / address transmitter, bus selector, and input / output decoder The integrated circuit 41 is formed on one chip, and the test circuit first signal converter 32 converts a signal type and a level, a transmit / receive synchronizer 38 that synchronizes data transmission and reception. A serial / parallel converter 33 for converting serial data into parallel data, a mode decoder 34 for decoding a read or write mode of the exchange hardware, and a address decode for decoding the address of the exchange hardware. A buffer 36 for outputting the transmission data input from the test circuit first signal conversion section 32 using the further 35 and the output of the mode decoder 34 as an enable signal, and an input from the buffer 36. It consists of a test circuit second signal conversion section 37 for converting the signal method and the level of the transmission data and the output of the address decoder 35 to be output to the data matching section 22 to output the ready signal and the transmission data. It further comprises a self test circuit (31).

Description

Matching circuit between personal computer with self-diagnosis circuit and exchange processor bus

The present invention relates to a test apparatus for an electronic exchange, and more particularly, to a matching circuit between a personal computer used for testing a hardware unit controlled by a processor bus of an electronic exchange and a processor matching bus (TD-BLS) of an electronic exchange. will be.

1 is a matching circuit diagram of a conventional personal computer and a processor bus of an exchange.

Referring to FIG. 1, a matching circuit between a conventional personal computer and a processor bus of a switch is connected to a data bus of a personal computer and serves as a bidirectional buffer, and a data matching unit 2. Is connected to a data receiving section 3 for receiving data from an exchange, a data transmitter 4 for connecting data to the exchange, and a data matching section 2 for transmitting data to the exchange. The address of the input / output port of the personal computer connected to the mode / address transmitter 5 for transmitting the address and read / write mode of the hardware unit of the switch to the switch and the control bus, address bus and data matching unit 2 of the personal computer. And an input / output port for decoding a control signal, specifying an input / output port, determining a data input / output direction of the data matching unit 2, and outputting a bus selection signal of the exchange. A bus selector (7) connected to a coder (Decorder) 6, the input / output port decoder 6 for selecting one of the redundant buses of the switch according to the bus select signal of the switch, the data receiver (3), A signal converter 8 connected to a data transmitter 4, a mode / address transmitter 5, a bus selector 7, and a bus (not shown) of the processor of the exchanger to convert the level and method of the transmitted and received signal; Connected to the data receiver 3, the data transmitter 4, the mode / address transmitter 5, and the signal converter 8 to generate and supply a frame pulse for timing data transmission and reception and a clock used for data transmission. And a clock generator 9 to be included.

In this specification, the term transmission is used as a switch in a personal computer, and the term reception is used to mean that a signal is transmitted.

The operation of the matching circuit between the personal computer of FIG. 1 and the processor bus of the exchange will be described.

The input / output port decoder 6 decodes the control signals of the address, address latch enable (ALE), read signal (IOR), and write signal (IOW) of the input / output port input from the personal computer to input / output of the data matching section 2. The direction is determined, and during data transmission and reception, a ready signal is irradiated so that data transmission is performed at the data transmitter 4 and data reception is performed at the data receiver 3.

The clock generator 3 generates frame pulses and clocks during data transmission and reception and supplies them to the data receiver 3, the data transmitter 4, the mode / address transmitter 5, and the signal converter 8.

The mode / address transmitter 5 sends the read or write mode of the switch hardware unit and the address of the hardware to the switch side.

In the signal conversion section 8, a data transmission terminal, a data reception terminal, a mode / address transmission terminal, a matching bus selection terminal, a frame pulse terminal, and a clock terminal are formed on the exchange side, and the signal of the personal computer is TTL level. The signals in the hardware unit of the exchange are at RS-422 differential level, so they are converted between each other.

A matching circuit between a conventional personal computer and a processor bus of an exchange is implemented with a general Transistor-Transistor Logic (TTL).

According to the matching circuit of the conventional personal computer and the processor bus of the exchanger, when the characteristics of the combined elements changed by the combination of the general TTL, the timing of the control signal is changed, the assembly is bad, and there is a problem that there is no self-diagnostic function. .

An object of the present invention is to provide a matching circuit between a personal computer and an exchange processor bus having a self-diagnosis circuit and integrated components.

1 is a matching circuit diagram of a conventional personal computer and an exchange processor bus.

2 is a matching circuit diagram of a personal computer and an exchange processor bus according to the present invention.

3 is a detailed view of the self-diagnosis circuit 31 shown in FIG.

* Explanation of symbols for main parts of the drawings

EN: Enable terminal ALE: Address latch enable signal

1OR: I / O port read signal 1OW: I / O port write signal

RxD: Receive Data TxD: Send Data

M / A: Mode / Address CLK: Clock

Fs: Frame pulse RDY: Ready signal

Buffer: buffer 2, 22: data matching unit

8, 28 32, 37: signal converter 31: self-diagnosis circuit

2 is a diagram showing the matching of the personal computer and the processor bus of the switch according to the present invention, and FIG. 3 is a detailed view of the self-diagnosis circuit 31 shown in FIG.

2 and 3, the present invention provides a data matching section 22 which is connected to a data bus of a personal computer and acts as a bidirectional buffer, and is connected to the data matching section 22 and is provided from a switch. A data receiver for receiving data, a data transmitter connected to the data matching section 22 to transmit data to the exchange, and a data matching section 22 for switching the address and read / write mode of the hardware unit of the switch. It is connected to the mode / address transmitter which transmits to an exchange, and the control bus, address bus, and data matching part 22 of a personal computer, decodes the address and control signal of the input / output port of a personal computer, designates an input / output port, and the said data matching An input / output port decoder for determining the data input / output direction of the section 22 and outputting a bus selection signal of the exchange; A bus selector for selecting one of the redundant buses of the exchange according to the bus select signal of the switch, and is connected to the data receiver, the data transmitter, the mode / address transmitter, the bus selector, and the bus of the exchange processor (not shown). It is connected to the signal converter 28 for converting the level and method of the signal to be used, and is used for the frame pulse and data transmission to be connected to the data receiver, the data transmitter, the mode / address transmitter, and the signal converter 28 to match the timing of data transmission and reception. In a matching circuit between a personal computer including a clock generator 29 for generating and supplying a clock to be supplied, the processor bus of the switch includes the data receiver, the data transmitter, the mode / address transmitter, the bus selector, and the input / output decoder. An integrated circuit 41 on a chip of the chip, the data transmission output terminal, the mode / address transmission output terminal of the signal conversion section 28, A test circuit first signal converter 32, which is connected to a frame pulse output terminal and a clock output terminal, to convert a signal type and level, and a frame pulse output terminal and a clock output of the test circuit first signal converter 32. A transmission and reception synchronization unit 38 connected to a terminal to synchronize data transmission and reception, and a data transmission output terminal and a mode / address transmission output terminal and transmission and reception synchronization unit 38 of the test circuit first signal conversion unit 32. Serial-to-parallel converter 33 for converting serial data into parallel data, a mode decoder 34 connected to the serial-to-parallel converter 33 to decode the read or write mode of the exchanger hardware, and the serial-to-parallel conversion. The address decoder 35, which is connected to the section 33 and decodes the address of the switch hardware, and the mode decoder 34, which is connected to the transmission data output terminal and the mode decoder 34 of the test circuit first signal conversion section 32. Of) A buffer 36 for outputting transmission data input from the test circuit first signal conversion section 32 using the output signal as an enable signal, and connected to the address decoder 35 and the buffer 36 so as to provide a buffer 36. To a test circuit second signal converting section 37 for converting a signal type and a level of the transmission data and the output of the address decoder 35 inputted from the same, and outputting a ready signal and transmitting data to the data matching section 22. It is characterized in that it further comprises a self-test circuit 31 is configured.

The self-test circuit included in the matching circuit between the personal computer and the exchange processor bus according to the present invention generates data and control signals from the personal computer without connecting the hardware unit of the exchange to test the matching state with the processor matching bus of the exchange. The operation thereof will be described with reference to FIGS. 2 and 3.

The integrated circuit input / output decoder outputs a loop enable signal to enable the mode decoder 34 and the address decoder 35 to be set to a self test state.

The mode signal and the address signal of the exchanger hardware input from the signal converter 28 are converted into signal type and level by the test circuit first signal converter 32, and are converted into parallel signals by the serial-parallel converter 33, respectively. It is input to the mode decoder 34 and the address decoder 35.

The address decoder 35 decodes the address of the exchanger hardware and outputs it to the enable terminal of the buffer 36 and the test circuit second signal converter 37, and the mode decoder 34 decodes the mode signal to program the user. If it matches with the mode information defined according to the enable the buffer 36.

The buffer 36 outputs the transmission data input from the test circuit first signal converter 32 to the test circuit second signal converter 37 in an enabled state.

The test circuit second signal converter 37 uses the signal input from the address decoder 35 as a ready signal to test data transmitted from the test circuit first signal converter 32 through the buffer 36. Feedback to the first signal converter 32.

The transmission data fed back to the test circuit first signal converter 32 is output to a personal computer.

The operation of the matching circuit between the personal computer and the processor bus of the switch according to the present invention is the same as in the conventional case except for the self-diagnosis circuit.

As described above, the matching circuit between the personal computer and the exchange processor bus according to the present invention includes a self-diagnosis circuit and integrates the components so that the matching state of the exchange processor's processor matching bus can be achieved without connecting the hardware unit of the exchange. Can be tested and the characteristics of the device can be maintained.

Claims (1)

A data matching section 22 connected to a data bus of a personal computer and serving as a bidirectional buffer, a data receiving section 22 connected to the data matching section 22 to receive data from an exchange, and the data matching section 22. A data receiving unit for transmitting data to the exchange, a mode / address transmitting unit for connecting the data matching unit 22 to a dust and read / write mode of the hardware unit of the exchange, and a personal computer. Connected to the control bus, address bus and data matching section 22 to decode the address and control signal of the input / output port of the personal computer to designate the input / output port, determine the data input / output direction of the data matching section 22, and switchboard An input / output port decoder for outputting a bus selection signal of the switch; A bus selector for selecting one of the redundant buses, and a level and method of a signal transmitted and received connected to a bus (not shown) of the data receiver, the data transmitter, the mode / address transmitter, the bus selector, and the exchange processor. A clock which is connected to the signal converter 28, the data receiver, the data transmitter, the mode / address transmitter, and the signal converter 28 to generate and supply a frame pulse for timing data transmission and reception and a clock used for data transmission. In a matching circuit between a personal computer including a generator 29 and a processor bus of an exchange, the data receiver, data transmitter, mode / address transmitter, bus selector, and input / output decoder are integrated on one chip. A circuit 41, the data transmission output terminal, the mode / address transmission output terminal, the frame pulse output terminal and the clock output of the signal conversion section 28; And a test circuit first signal converter 32 for converting a signal type and level, and a frame pulse output terminal and a clock output terminal of the test circuit first signal converter 32 for data transmission and reception. The transmission / reception synchronization unit 38, which synchronizes with the synchronization, and the data transmission output terminal and the mode / address transmission output terminal of the test circuit first signal conversion unit 32, and the transmission / reception synchronization unit 38 are connected to convert serial data into parallel data. Connected to the serial-to-parallel converter 33 for conversion, the serial-to-parallel converter 33, and the mode decoder 34 for decoding the read or write mode of the switch hardware, and the serial-to-parallel converter 33 The address decoder 35 which decodes the address of the exchange hardware and the transmission data output terminal of the test circuit first signal converter 32 and the mode decoder 34 are connected to enable the output of the mode decoder 34. When using as A buffer 36 for outputting transmission data input from the circuit first signal conversion section 32, and a transmission data and address decoder connected to the address decoder 35 and the buffer 36 and input from the buffer 36 ( A self-test circuit 31 composed of a test circuit second signal converter 37 for converting the signal method and level of the output of the output 35) and outputting a ready signal and transmission data to the data matching unit 22; And a matching circuit between a personal computer and an exchange processor bus.