JP2000133801A5 - - Google Patents
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- JP2000133801A5 JP2000133801A5 JP1998305368A JP30536898A JP2000133801A5 JP 2000133801 A5 JP2000133801 A5 JP 2000133801A5 JP 1998305368 A JP1998305368 A JP 1998305368A JP 30536898 A JP30536898 A JP 30536898A JP 2000133801 A5 JP2000133801 A5 JP 2000133801A5
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- JP
- Japan
- Prior art keywords
- layer
- type
- low
- potential side
- resistance
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- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000009792 diffusion process Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 claims description 5
- 230000003252 repetitive Effects 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims 1
Description
【0005】
【課題を解決するための手段】
本発明の高耐圧半導体素子の第1の態様は、高電位側の低抵抗層と低電位側の低抵抗層の間にn型の層とp型の層が交互に繰り返されて存在する部分を有する高耐圧半導体素子であって、このn型とp型の層は高電位側の低抵抗層と低電位側の低抵抗層を結ぶ方向に延在して存在し、n型の層とp型の層が交互に繰り返されて存在する部分が前記高電位側の低抵抗層と低電位側の低抵抗層を結ぶ方向と直交方向に配置され、高耐圧印加時にこのn型とp型の層が空乏化して高電圧を支え、少なくともn型の層同士、またはp型の層同士の間にはそれより低濃度あるいは高抵抗の半導体層または絶縁層が介在していることを特徴とする。
本発明の高耐圧半導体素子の第2の態様は、基板の第1の表面に形成された高電位側の第1の拡散層と、前記基板の第2の表面に形成された低電位側の第2の拡散層と、前記基板の前記第1の拡散層側から前記第2の拡散層方向に形成された溝と、前記溝の側壁内に交互に繰り返して形成された第1導電型の第1の半導体層及び第2導電型の第2の半導体層と、前記溝内に形成され、前記第1の半導体層及び第2の半導体層より低濃度あるいは高抵抗の半導体層または絶縁層と、前記第1の拡散層と前記第2の拡散層との間で、前記第1、第2の半導体層から絶縁して形成されたゲート電極とを具備することを特徴とする。
0005
[Means for solving problems]
A first aspect of the high-voltage semiconductor device of the present invention, the presence n-type layer and a p-type layer between the high potential side of the low-resistance layer and the low potential side of the low resistance layer is returned Ri Repetitive alternately a high voltage semiconductor device having a portion, of the n-type and p-type layers are present extending in the direction connecting the low-resistance layer of low-resistance layer and the low potential side of the high potential side, n-type disposed layer and p-type layers perpendicular direction to the direction in which the moiety present repeated alternately connecting the low-resistance layer of low-resistance layer and the low potential side of the high potential side, and a high breakdown voltage applied at the n-type and p-type layers are depleted supporting a high voltage, less the n-type layer between even, or to low concentration or high-resistance semiconductor layer or the insulating layer is interposed than between the layer between the p-type it shall be the feature of the you are.
A second aspect of the high withstand voltage semiconductor element of the present invention is a high potential side first diffusion layer formed on the first surface of the substrate and a low potential side formed on the second surface of the substrate. A second diffusion layer, a groove formed from the first diffusion layer side of the substrate toward the second diffusion layer, and a first conductive type formed alternately and repeatedly in the side wall of the groove. A first semiconductor layer, a second conductive type second semiconductor layer, and a semiconductor layer or an insulating layer formed in the groove and having a lower concentration or higher resistance than the first semiconductor layer and the second semiconductor layer. The first diffusion layer and the second diffusion layer are provided with a gate electrode formed so as to be insulated from the first and second semiconductor layers.
Claims (5)
前記基板の第2の表面に形成された低電位側の第2の拡散層と、A second diffusion layer on the low potential side formed on the second surface of the substrate;
前記基板の前記第1の拡散層側から前記第2の拡散層方向に形成された溝と、A groove formed in the direction from the first diffusion layer side of the substrate toward the second diffusion layer;
前記溝の側壁内に交互に繰り返して形成された第1導電型の第1の半導体層及び第2導電型の第2の半導体層と、A first conductive type first semiconductor layer and a second conductive type second semiconductor layer, which are alternately and repeatedly formed in the sidewall of the groove;
前記溝内に形成され、前記第1の半導体層及び第2の半導体層より低濃度あるいは高抵抗の半導体層または絶縁層と、A semiconductor layer or an insulating layer formed in the trench and having a lower concentration or higher resistance than the first semiconductor layer and the second semiconductor layer;
前記第1の拡散層と前記第2の拡散層との間で、前記第1、第2の半導体層から絶縁して形成されたゲート電極とA gate electrode formed between the first diffusion layer and the second diffusion layer and insulated from the first and second semiconductor layers;
を具備することを特徴とする高耐圧半導体素子。A high withstand voltage semiconductor element comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30536898A JP3943732B2 (en) | 1998-10-27 | 1998-10-27 | High voltage semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30536898A JP3943732B2 (en) | 1998-10-27 | 1998-10-27 | High voltage semiconductor element |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2000133801A JP2000133801A (en) | 2000-05-12 |
JP2000133801A5 true JP2000133801A5 (en) | 2005-07-28 |
JP3943732B2 JP3943732B2 (en) | 2007-07-11 |
Family
ID=17944278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30536898A Expired - Fee Related JP3943732B2 (en) | 1998-10-27 | 1998-10-27 | High voltage semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3943732B2 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006210368A (en) * | 1999-07-02 | 2006-08-10 | Toyota Central Res & Dev Lab Inc | Vertical semiconductor device and its fabrication process |
JP4939760B2 (en) | 2005-03-01 | 2012-05-30 | 株式会社東芝 | Semiconductor device |
JP4997715B2 (en) * | 2005-05-18 | 2012-08-08 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
JP5052025B2 (en) * | 2006-03-29 | 2012-10-17 | 株式会社東芝 | Power semiconductor device |
JP4539680B2 (en) | 2007-05-14 | 2010-09-08 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
JP4670915B2 (en) | 2008-08-08 | 2011-04-13 | ソニー株式会社 | Semiconductor device |
KR101023079B1 (en) | 2008-11-04 | 2011-03-25 | 주식회사 동부하이텍 | Semiconductor device and method for manufacturing the device |
CN111937123A (en) * | 2018-03-26 | 2020-11-13 | 日产自动车株式会社 | Semiconductor device and method for manufacturing the same |
CN117766588B (en) * | 2024-02-22 | 2024-04-30 | 南京邮电大学 | Super-junction double SOI-LDMOS device with extended drain structure and manufacturing method |
-
1998
- 1998-10-27 JP JP30536898A patent/JP3943732B2/en not_active Expired - Fee Related
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