JP2000133801A5 - - Google Patents

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JP2000133801A5
JP2000133801A5 JP1998305368A JP30536898A JP2000133801A5 JP 2000133801 A5 JP2000133801 A5 JP 2000133801A5 JP 1998305368 A JP1998305368 A JP 1998305368A JP 30536898 A JP30536898 A JP 30536898A JP 2000133801 A5 JP2000133801 A5 JP 2000133801A5
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layer
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low
potential side
resistance
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JP2000133801A (en
JP3943732B2 (en
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【0005】
【課題を解決するための手段】
本発明の高耐圧半導体素子の第1の態様は、高電位側の低抵抗層と低電位側の低抵抗層の間にn型の層とp型の層が交互に繰り返されて存在する部分を有する高耐圧半導体素子であって、このn型p型層は高電位側の低抵抗層と低電位側の低抵抗層を結ぶ方向に延在して存在し、n型の層とp型の層が交互に繰り返されて存在する部分が前記高電位側の低抵抗層と低電位側の低抵抗層を結ぶ方向と直交方向に配置され、高耐圧印加時にこのn型とp型の層が空乏化して高電圧を支え、少なくともn層同士、またはp層同士の間にはそれより低濃度あるいは高抵抗の半導体層または絶縁層が介在していることを特徴とする。
本発明の高耐圧半導体素子の第2の態様は、基板の第1の表面に形成された高電位側の第1の拡散層と、前記基板の第2の表面に形成された低電位側の第2の拡散層と、前記基板の前記第1の拡散層側から前記第2の拡散層方向に形成された溝と、前記溝の側壁内に交互に繰り返して形成された第1導電型の第1の半導体層及び第2導電型の第2の半導体層と、前記溝内に形成され、前記第1の半導体層及び第2の半導体層より低濃度あるいは高抵抗の半導体層または絶縁層と、前記第1の拡散層と前記第2の拡散層との間で、前記第1、第2の半導体層から絶縁して形成されたゲート電極とを具備することを特徴とする。
0005
[Means for solving problems]
A first aspect of the high-voltage semiconductor device of the present invention, the presence n-type layer and a p-type layer between the high potential side of the low-resistance layer and the low potential side of the low resistance layer is returned Ri Repetitive alternately a high voltage semiconductor device having a portion, of the n-type and p-type layers are present extending in the direction connecting the low-resistance layer of low-resistance layer and the low potential side of the high potential side, n-type disposed layer and p-type layers perpendicular direction to the direction in which the moiety present repeated alternately connecting the low-resistance layer of low-resistance layer and the low potential side of the high potential side, and a high breakdown voltage applied at the n-type and p-type layers are depleted supporting a high voltage, less the n-type layer between even, or to low concentration or high-resistance semiconductor layer or the insulating layer is interposed than between the layer between the p-type it shall be the feature of the you are.
A second aspect of the high withstand voltage semiconductor element of the present invention is a high potential side first diffusion layer formed on the first surface of the substrate and a low potential side formed on the second surface of the substrate. A second diffusion layer, a groove formed from the first diffusion layer side of the substrate toward the second diffusion layer, and a first conductive type formed alternately and repeatedly in the side wall of the groove. A first semiconductor layer, a second conductive type second semiconductor layer, and a semiconductor layer or an insulating layer formed in the groove and having a lower concentration or higher resistance than the first semiconductor layer and the second semiconductor layer. The first diffusion layer and the second diffusion layer are provided with a gate electrode formed so as to be insulated from the first and second semiconductor layers.

Claims (5)

高電位側の低抵抗層と低電位側の低抵抗層の間にn型の層とp型の層が交互に繰り返されて存在する部分を有する高耐圧半導体素子であって、このn型p型層は高電位側の低抵抗層と低電位側の低抵抗層を結ぶ方向に延在して存在し、n型の層とp型の層が交互に繰り返されて存在する部分が前記高電位側の低抵抗層と低電位側の低抵抗層を結ぶ方向と直交方向に配置され、高耐圧印加時にこのn型とp型の層が空乏化して高電圧を支え、少なくともn層同士、またはp層同士の間にはそれより低濃度あるいは高抵抗の半導体層または絶縁層が介在していることを特徴とする高耐圧半導体素子。A high voltage semiconductor device having a portion where the n-type layer and a p-type layers are present is returned Ri Repetitive alternately between the high-potential side of the low-resistance layer and the low potential side of the low-resistance layer, the n type and p-type layers are present extending in the direction connecting the low-resistance layer of low-resistance layer and the low potential side of the high potential side, n-type layer and p-type layers are present alternately repeated The portion is arranged in a direction orthogonal to the direction connecting the low potential layer on the high potential side and the low resistance layer on the low potential side, and the n-type and p-type layers are depleted when a high breakdown voltage is applied to support a high voltage. and n-type layers to each other is also high breakdown voltage semiconductor device or between the layers to each other of p-type, characterized in that from the low density or high resistance of the semiconductor layer or the insulating layer which is interposed. 前記高電位側の低抵抗層と低電位側の低抵抗層は、前記基板の異なる面に形成され、前記n型の層とp型の層が交互に繰り返されて存在する部分は、前記基板の前記高電位側の低抵抗層から低電位側の低抵抗層方向に形成された溝の側壁内に形成され、前記溝内には前記n型の層とp型の層より低濃度あるいは高抵抗の半導体層または絶縁層が形成されていることを特徴とする請求項1記載の高耐圧半導体素子。The low-resistance layer on the high potential side and the low-resistance layer on the low potential side are formed on different surfaces of the substrate, and the portion where the n-type layer and the p-type layer are alternately repeated exists in the substrate. Formed in a sidewall of a groove formed in the direction from the low-resistance layer on the high potential side to the low-resistance layer on the low potential side. The concentration in the groove is lower or higher than that of the n-type layer and the p-type layer. 2. The high withstand voltage semiconductor element according to claim 1, wherein a semiconductor layer or an insulating layer of resistance is formed. 前記n型の層とp型の層が交互に繰り返されて存在する部分は、前記高電位側の低抵抗層と低電位側の低抵抗層の間の基板に形成された溝の側壁内に形成され、前記溝内には前記n型の層とp型の層より低濃度あるいは高抵抗の半導体層または絶縁層が形成されていることを特徴とする請求項1記載の高耐圧半導体素子。A portion where the n-type layer and the p-type layer are alternately repeated exists in a side wall of a groove formed in the substrate between the low potential layer on the high potential side and the low resistance layer on the low potential side. 2. The high breakdown voltage semiconductor element according to claim 1, wherein a semiconductor layer or an insulating layer having a lower concentration or higher resistance than the n-type layer and the p-type layer is formed in the trench. 前記n型の層、p型の層は、前記溝の側壁から不純物を2重に拡散して形成したことを特徴とする請求項2又は3記載の高耐圧半導体素子。4. The high breakdown voltage semiconductor element according to claim 2, wherein the n-type layer and the p-type layer are formed by diffusing impurities from the side wall of the groove. 基板の第1の表面に形成された高電位側の第1の拡散層と、A first diffusion layer on the high potential side formed on the first surface of the substrate;
前記基板の第2の表面に形成された低電位側の第2の拡散層と、A second diffusion layer on the low potential side formed on the second surface of the substrate;
前記基板の前記第1の拡散層側から前記第2の拡散層方向に形成された溝と、A groove formed in the direction from the first diffusion layer side of the substrate toward the second diffusion layer;
前記溝の側壁内に交互に繰り返して形成された第1導電型の第1の半導体層及び第2導電型の第2の半導体層と、A first conductive type first semiconductor layer and a second conductive type second semiconductor layer, which are alternately and repeatedly formed in the sidewall of the groove;
前記溝内に形成され、前記第1の半導体層及び第2の半導体層より低濃度あるいは高抵抗の半導体層または絶縁層と、A semiconductor layer or an insulating layer formed in the trench and having a lower concentration or higher resistance than the first semiconductor layer and the second semiconductor layer;
前記第1の拡散層と前記第2の拡散層との間で、前記第1、第2の半導体層から絶縁して形成されたゲート電極とA gate electrode formed between the first diffusion layer and the second diffusion layer and insulated from the first and second semiconductor layers;
を具備することを特徴とする高耐圧半導体素子。A high withstand voltage semiconductor element comprising:
JP30536898A 1998-10-27 1998-10-27 High voltage semiconductor element Expired - Fee Related JP3943732B2 (en)

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JP30536898A JP3943732B2 (en) 1998-10-27 1998-10-27 High voltage semiconductor element

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JP2000133801A JP2000133801A (en) 2000-05-12
JP2000133801A5 true JP2000133801A5 (en) 2005-07-28
JP3943732B2 JP3943732B2 (en) 2007-07-11

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210368A (en) * 1999-07-02 2006-08-10 Toyota Central Res & Dev Lab Inc Vertical semiconductor device and its fabrication process
JP4939760B2 (en) 2005-03-01 2012-05-30 株式会社東芝 Semiconductor device
JP4997715B2 (en) * 2005-05-18 2012-08-08 富士電機株式会社 Semiconductor device and manufacturing method thereof
JP5052025B2 (en) * 2006-03-29 2012-10-17 株式会社東芝 Power semiconductor device
JP4539680B2 (en) 2007-05-14 2010-09-08 株式会社デンソー Semiconductor device and manufacturing method thereof
JP4670915B2 (en) 2008-08-08 2011-04-13 ソニー株式会社 Semiconductor device
KR101023079B1 (en) 2008-11-04 2011-03-25 주식회사 동부하이텍 Semiconductor device and method for manufacturing the device
CN111937123A (en) * 2018-03-26 2020-11-13 日产自动车株式会社 Semiconductor device and method for manufacturing the same
CN117766588B (en) * 2024-02-22 2024-04-30 南京邮电大学 Super-junction double SOI-LDMOS device with extended drain structure and manufacturing method

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