WO2011086721A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2011086721A1
WO2011086721A1 PCT/JP2010/062594 JP2010062594W WO2011086721A1 WO 2011086721 A1 WO2011086721 A1 WO 2011086721A1 JP 2010062594 W JP2010062594 W JP 2010062594W WO 2011086721 A1 WO2011086721 A1 WO 2011086721A1
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WIPO (PCT)
Prior art keywords
region
semiconductor device
diffusion region
semiconductor layer
thickness
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PCT/JP2010/062594
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French (fr)
Japanese (ja)
Inventor
雅人 滝
博臣 江口
峰司 大川
清春 早川
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トヨタ自動車株式会社
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Publication of WO2011086721A1 publication Critical patent/WO2011086721A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions

Definitions

  • the present invention relates to a semiconductor device including a laminated substrate in which a supporting substrate, a buried insulating film, and a semiconductor layer are laminated.
  • An SOI (Silicon On On Insulator) substrate is known as an example of a laminated substrate.
  • This type of semiconductor device is often a lateral type in which a first main electrode connected to a high-voltage side wiring and a second main electrode connected to a low-voltage side wiring are provided on the surface of a semiconductor layer.
  • a lateral IGBT Insulated Gate Bipolar Transistor
  • a collector electrode and an emitter electrode are provided on the surface of the semiconductor layer
  • an anode electrode and a cathode electrode are provided on the surface of the semiconductor layer.
  • a horizontal diode a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) in which a drain electrode and a source electrode are provided on the surface of a semiconductor layer are included.
  • the support substrate is often used connected to the low voltage side wiring.
  • a semiconductor device using an SOI substrate breakdown occurs near the interface between a buried insulating film and a semiconductor layer, and electron / hole pairs are generated.
  • the generated electrons move along the vertical direction toward the first main electrode connected to the high voltage side wiring.
  • the generated electrons collide with the crystal lattice existing in the movement path, so that a larger amount of electrons are generated and a sudden current increase occurs (avalanche breakdown). If avalanche breakdown occurs, the semiconductor device will eventually be thermally destroyed.
  • Japanese Patent Laid-Open No. 2007-173422 discloses a three-layer structure in which a voltage holding portion in a semiconductor layer includes an n-type back surface semiconductor region, an n ⁇ -type intermediate semiconductor region, and a p-type front surface semiconductor region.
  • a semiconductor device comprising: When this three-layer structure is provided in the voltage holding unit, a phenomenon occurs in which the equipotential lines of the voltage holding unit are bent. Specifically, equipotential lines extending in the vertical direction of the semiconductor layer are bent near the interface between the buried insulating film and the semiconductor layer.
  • the position where the equipotential lines are bent is a region where the positive and negative electric field strengths are reversed when observed in the vertical direction, that is, a region where the electric field strength is zero. If there is a region where the electric field strength is zero, even if breakdown occurs near the interface between the buried insulating film and the semiconductor layer, the distance of movement of the generated electrons is limited to the zero region from the interface. As a result, in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2007-173422, the moving distance of electrons generated by breakdown is limited to be short, and the occurrence of avalanche breakdown is suppressed.
  • the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2007-173422 has excellent breakdown voltage characteristics and is useful in many applications. However, a semiconductor device having more excellent characteristics is desired.
  • the technology disclosed in this specification is intended to realize a high breakdown voltage of a semiconductor device using a multilayer substrate.
  • the semiconductor device disclosed in this specification is characterized by further including a fourth region formed on the three-layer structure of the voltage holding portion. If the fourth region is formed on the three-layer structure of the voltage holding unit, the voltage holding unit has a large thickness, and thus the heat capacity of the voltage holding unit is large. For example, it is known that when a high voltage such as static electricity is applied to a semiconductor device, the temperature of the voltage holding unit rapidly increases. In such a case, in the semiconductor device, since the heat capacity of the voltage holding unit is large, a rapid temperature rise can be suppressed. Moreover, since the thickness of the voltage holding unit is configured to be large, the electric resistance value of the voltage holding unit is reduced, and power loss can be suppressed.
  • the semiconductor device can have high breakdown voltage and low loss characteristics.
  • the principal part sectional drawing of IGBT of an Example is typically shown.
  • the influence of the thickness of the semiconductor layer with respect to the power loss of IGBT of an Example is shown.
  • An expanded principal part sectional view of a voltage holding part is shown typically.
  • the influence of the thickness of the semiconductor layer with respect to ESD tolerance of IGBT of an Example is shown.
  • the principal part sectional drawing of MOSFET of an Example is typically shown.
  • the principal part sectional drawing of the diode of an Example is typically shown.
  • the technology disclosed in this specification is embodied in a semiconductor device having a stacked substrate in which a support substrate, a buried insulating film, and a semiconductor layer are stacked.
  • the semiconductor device further includes a first main electrode, a second main electrode, and a voltage holding unit.
  • the first main electrode is provided on the surface of the semiconductor layer.
  • the second main electrode is provided on the surface of the semiconductor layer and is insulated from the first main electrode.
  • the voltage holding unit is formed in the semiconductor layer and holds a voltage applied between the first main electrode and the second main electrode.
  • the voltage holding unit includes a first conductivity type first region, a first conductivity type second region provided on the first region, and a second conductivity type provided on the second region.
  • the impurity concentration in the first region changes along the horizontal direction.
  • the impurity concentration of the first region may change continuously along the horizontal direction or may change stepwise along the horizontal direction.
  • the voltage holding unit may further include a region other than the first region, the second region, the third region, and the fourth region.
  • the semiconductor device includes a three-layer structure including a first region, a second region, and a third region in the voltage holding unit. For this reason, equipotential lines extending in the thickness direction of the semiconductor layer are bent near the interface between the buried insulating film and the semiconductor layer.
  • the semiconductor device includes a fourth region on the three-layer structure of the voltage holding unit.
  • the heat capacity of a voltage holding part is large.
  • the semiconductor device since the heat capacity of the voltage holding unit is large, a rapid temperature rise can be suppressed.
  • the thickness of the voltage holding unit is configured to be large, the electric resistance value of the voltage holding unit is reduced, and power loss can be suppressed.
  • the semiconductor device can have high breakdown voltage and low loss characteristics.
  • the semiconductor device may further include a fifth region of the second conductivity type formed in the semiconductor layer and connected to the second main electrode.
  • the third region and the fifth region may be in contact with each other. According to this aspect, since the potential of the third region is stabilized, a wide range of the voltage holding unit can be well depleted.
  • the impurity concentration in the first region may increase in a direction away from the fifth region. According to this aspect, the bending phenomenon of the equipotential lines can occur favorably in the voltage holding unit.
  • the impurity concentration in the first region may be lower than the impurity concentration in the second region.
  • the impurity concentration in the fourth region may be lower than the impurity concentration in the first region.
  • the thickness of the fourth region may be larger than the total thickness of the first region, the second region, and the third region. According to this aspect, the present inventors have confirmed that ESD (Electro Static Discharge) resistance is improved. More preferably, the thickness of the fourth region may be 1.5 times or more the total thickness of the first region, the second region, and the third region. According to this aspect, in addition to the ESD tolerance, the power loss can be significantly improved.
  • the semiconductor device may operate in a bipolar manner.
  • the electric resistance value in the fourth region decreases due to conductivity modulation. For this reason, the merit which provides the 4th area
  • a semiconductor device with low power loss can be realized.
  • the first region is an n-type back surface diffusion region
  • the second region is an n-type intermediate region
  • the third region is a p-type intermediate region
  • the fourth region is n. It may be a surface diffusion region of the mold.
  • the back surface diffusion region, the n-type intermediate region diffusion region, the p-type intermediate region diffusion region, and the front surface region diffusion region may be laminated in this order, and a four-layer structure may be formed.
  • the impurity concentration in the back surface diffusion region may change in the lateral direction.
  • the impurity concentration of the n-type intermediate diffusion region, the p-type intermediate diffusion region, and the surface diffusion region may be substantially constant in the lateral direction.
  • the thickness of the four-layer structure is preferably 2 ⁇ m or more, more preferably 2.5 ⁇ m or more.
  • single crystal silicon is used as a semiconductor material, but a compound semiconductor such as gallium nitride, silicon carbide, or gallium arsenide may be used instead of this example.
  • a compound semiconductor such as gallium nitride, silicon carbide, or gallium arsenide may be used instead of this example.
  • components that are substantially common to the embodiments are denoted by common reference numerals, and description thereof is omitted.
  • FIG. 1 schematically shows a cross-sectional view of an essential part of an IGBT (Insulated Gate Bipolar Transistor) 10.
  • the IGBT 10 includes an SOI (Silicon On Insulator) substrate 20 in which a single crystal silicon support substrate 30, a silicon oxide buried insulating film 40, and a single crystal silicon semiconductor layer 50 are stacked.
  • the support substrate 30 contains p-type impurities at a high concentration, and is connected to the low-voltage side wiring.
  • the low voltage side wiring is connected to the negative polarity side of the power supply voltage, and is fixed to the ground potential in one example.
  • the buried insulating film 40 preferably has a thickness in the y-axis direction (hereinafter referred to as the vertical direction) of about 3.0 to 5.0 ⁇ m.
  • the material of the buried insulating film 40 is preferably a material having a low relative dielectric constant.
  • the semiconductor layer 50 contains n-type impurities at a low concentration, and the thickness in the vertical direction is preferably about 2.0 ⁇ m or more, more preferably about 2.5 ⁇ m or more.
  • the vertical thickness of the semiconductor layer 50 is preferably about 5.0 ⁇ m or less in order to suppress an increase in manufacturing cost for element isolation.
  • the resistivity of the semiconductor layer 50 is preferably about 1 to 100 m ⁇ ⁇ cm so that the mechanical strength is maintained.
  • the IGBT 10 includes a collector electrode 74 (an example of a first main electrode), a collector polyplate electrode 78, a LOCOS (Local Oxidation of Silicon) film 69, a gate electrode 84, and an emitter electrode 87 (on the surface of the semiconductor layer 50).
  • the collector electrode 74 is connected to the high voltage side wiring.
  • the high voltage side wiring is connected to the positive polarity side of the power supply voltage.
  • the material of the collector electrode 74 is aluminum in one example.
  • the collector polyplate electrode 78 is provided between the collector electrode 74 and the gate electrode 84, and faces the surface of the semiconductor layer 50 and the LOCOS film 69 through an insulating film of silicon oxide.
  • the lateral width in the x-axis direction (hereinafter referred to as the lateral direction) where the collector polyplate electrode 78 covers the surface of the LOCOS film 69 is about 1 to 5 ⁇ m.
  • the collector polyplate electrode 78 is connected to the high voltage side wiring.
  • the material of the collector polyplate electrode 78 is polysilicon in one example.
  • the LOCOS film 69 preferably has a vertical thickness of about 0.25 to 0.5 ⁇ m.
  • the material of the LOCOS film 69 is, for example, silicon oxide.
  • the gate electrode 84 is provided between the collector polyplate electrode 78 and the emitter electrode 87, and faces the surfaces of the semiconductor layer 50 and the LOCOS film 69 with a silicon oxide gate insulating film 82 interposed therebetween.
  • the lateral width in which the gate electrode 84 covers the surface of the LOCOS film 69 is about 1 to 5 ⁇ m.
  • the material of the gate electrode 84 is polysilicon.
  • the emitter electrode 87 is connected to the low voltage side wiring. In one example, the material of the emitter electrode 87 is aluminum.
  • the IGBT 10 includes a collector region 72, a buffer region 76, a back surface diffusion region 62, an n-type intermediate diffusion region 64, a p-type intermediate diffusion region 66, a surface diffusion region 68, and an emitter region formed in the semiconductor layer 50. 86 and a body region 88.
  • a voltage holding unit 60 between the collector region 72 electrically connected to the collector electrode 74 which is one main electrode and the body region 88 electrically connected to the emitter electrode 87 which is the other main electrode.
  • the region is referred to as a voltage holding unit 60. It can also be said that the voltage holding unit 60 is a region located below the LOCOS film 69.
  • the voltage holding unit 60 is a region where carriers flow, and can also be called a drift region.
  • the collector region 72 is formed in the surface layer portion of the semiconductor layer 50 using an ion implantation technique.
  • the collector region 72 contains p-type impurities at a high concentration and is ohmically connected to the collector electrode 74.
  • the buffer region 76 is formed in the surface layer portion of the semiconductor layer 50 using an ion implantation technique.
  • the buffer region 76 surrounds the collector region 72 and contains n-type impurities.
  • the emitter region 86 is formed in the surface layer portion of the semiconductor layer 50 using an ion implantation technique.
  • the emitter region 86 contains an n-type impurity at a high concentration and is ohmically connected to the emitter electrode 87.
  • the body region 88 (an example of the fifth region) is formed so as to reach the back surface from the front surface of the semiconductor layer 50 using an ion implantation technique.
  • Body region 88 has contact body region 88a and main body region 88b, and contains p-type impurities.
  • Contact body region 88 a is ohmically connected to emitter electrode 87.
  • Main body region 88b is connected to emitter electrode 87 through contact body region 88a.
  • the voltage holding unit 60 includes a back surface diffusion region 62 (an example of a first region), an n-type intermediate region diffusion region 64 (an example of a second region), a p-type intermediate region diffusion region 66 (an example of a third region), and a surface.
  • a partial diffusion region 68 (an example of a fourth region) is provided, and these diffusion regions are stacked in that order.
  • the back surface diffusion region 62 is formed in the vicinity of the interface between the buried insulating film 40 and the semiconductor layer 50 using an ion implantation technique.
  • the peak position (also referred to as a range position) of the introduced dopant concentration is set at the interface between the buried insulating film 40 and the semiconductor layer 50. Is desirable.
  • the peak position of the dopant concentration is about 0.5 ⁇ m or less, more preferably about 0.2 ⁇ m or less from the interface between the buried insulating film 40 and the semiconductor layer 50 toward the surface of the semiconductor layer 50.
  • the back surface diffusion region 62 includes n-type impurities and is composed of eight partial regions 62a to 62h having different impurity concentrations.
  • the impurity concentrations of the partial regions 62a to 62h increase from the body region 88 side toward the collector region 72 side. That is, the impurity concentration of the partial region indicated by reference numeral 62a is the lowest, and the impurity concentration of the partial region indicated by reference numeral 62h is the highest. However, the impurity concentration of the partial region indicated by reference numeral 62 a is higher than the impurity concentration of the surface diffusion region 68. Further, the impurity concentration of the partial region indicated by reference numeral 62 h is lower than the impurity concentration of the n-type intermediate diffusion region 64.
  • the impurity concentration of the partial region indicated by reference numeral 62a is approximately 1 ⁇ 10 15 to 1 ⁇ 10 16
  • the impurity concentration of the partial region indicated by reference numeral 62h is approximately 8 ⁇ 10 15 to 8 ⁇ 10 15 . Is desirable.
  • the n-type intermediate portion diffusion region 64 is formed on the back surface diffusion region 62 using an ion implantation technique. One end of n-type intermediate diffusion region 64 is in contact with body region 88 and the other end is separated from buffer region 76.
  • the n-type intermediate diffusion region 64 contains n-type impurities, and the impurity concentration in the lateral direction is substantially constant. In one example, the impurity concentration of the n-type intermediate diffusion region 64 is preferably about 1 ⁇ 10 16 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the p-type intermediate diffusion region 66 is formed on the n-type intermediate diffusion region 64 using an ion implantation technique. One end of p-type intermediate diffusion region 66 is in contact with body region 88 and the other end is separated from buffer region 76.
  • the p-type intermediate diffusion region 66 contains p-type impurities, and the impurity concentration in the lateral direction is substantially constant. In one example, the impurity concentration of the p-type intermediate diffusion region 66 is desirably about 1 ⁇ 10 16 to 1 ⁇ 10 17 cm ⁇ 3 .
  • a common ion implantation mask can be used in order to reduce the manufacturing cost. For this reason, the formation positions of the p-type intermediate diffusion region 66 and the n-type intermediate diffusion region 64 are common when viewed in plan.
  • the total vertical thickness T60a of the back surface diffusion region 62, the n-type intermediate diffusion region 64, and the p-type intermediate diffusion region 66 is desirably thinner. As the total thickness T60a is thinner, the equipotential line is bent closer to the vicinity of the interface between the buried insulating film 40 and the semiconductor layer 50, as will be described later. It is desirable that the thickness of the back surface diffusion region 62 in the vertical direction is so thin that it can be almost ignored. It is desirable that the vertical thickness of the n-type intermediate diffusion region 64 is about 0.5 ⁇ m or less, more preferably 0.2 ⁇ m or less. It is desirable that the vertical thickness of the p-type intermediate diffusion region 66 is about 0.5 ⁇ m or less, more preferably 0.2 ⁇ m or less.
  • the surface portion diffusion region 68 is a remaining portion after other diffusion regions are formed, and is formed on the p-type intermediate region diffusion region 66. One end of the surface diffusion region 68 is in contact with the body region 88 and the other end is in contact with the buffer region 76.
  • the surface diffusion region 68 contains n-type impurities, and the impurity concentration is preferably about 1 ⁇ 10 15 to 1 ⁇ 10 16 cm ⁇ 3 . It is desirable that the vertical thickness T60b of the surface diffusion region 68 is about 1.0 ⁇ m or more, more preferably about 1.5 ⁇ m or more.
  • the operation of the IGBT 10 will be described.
  • a positive voltage of about several volts is applied to the gate electrode 84, an inversion layer is formed in the surface layer portion of the main body region 88b opposed to the gate electrode 84, and the IGBT 10 is turned on.
  • the ON state of the IGBT 10 electrons are injected from the emitter region 86 into the voltage holding unit 60, holes are injected from the collector region 72 into the voltage holding unit 60, and the conductivity of the voltage holding unit 60 is modulated.
  • FIG. 2 shows the influence of the thickness of the semiconductor layer 50 on the power loss of the IGBT 10.
  • the horizontal axis represents the ratio of the thickness T60b of the front surface diffusion region 68 to the total vertical thickness T60a of the back surface diffusion region 62, the n-type intermediate diffusion region 64, and the p-type intermediate diffusion region 66.
  • the thickness of the back surface diffusion region 62 is almost negligible
  • the thickness of the n-type intermediate diffusion region 64 is 0.5 ⁇ m
  • the thickness of the p-type intermediate diffusion region 66 is 0.5 ⁇ m
  • the total The thickness T60a is fixed at 1.0 ⁇ m.
  • FIG. 2 shows, it turns out that power loss falls, so that thickness ratio (T60b / T60a) becomes large.
  • the thickness ratio (T60b / T60a) is 1.5 or more (the thickness of the semiconductor layer 50 is 2.5 ⁇ m or more), the effect of reducing the power loss is almost saturated. Therefore, it can be seen that it is important to set the thickness ratio (T60b / T60a) to 1.5 or more.
  • the gate electrode 84 When the gate electrode 84 is switched to the ground potential, the inversion layer in the surface layer portion of the main body region 88b disappears, and the IGBT 10 is turned off. In the off state of the IGBT 10, the voltage holding unit 60 is depleted over a wide range.
  • FIG. 3 shows an enlarged cross-sectional view of a main part in which a part of the voltage holding unit 60 is enlarged.
  • FIG. 3 shows the equipotential line distribution when the IGBT 10 is turned off.
  • the IGBT 10 has a three-layer structure including a back surface diffusion region 62, an n-type intermediate region diffusion region 64, and a p-type intermediate region diffusion region 66.
  • equipotential lines extending in the thickness direction of the semiconductor layer 50 are bent in the vicinity of the interface between the buried insulating film 40 and the semiconductor layer 50.
  • the region where the equipotential lines are bent is a region where the electric field intensity becomes zero when observed in the vertical direction.
  • the IGBT 10 Normally, when a high voltage is applied to the IGBT 10, breakdown occurs near the interface between the buried insulating film 40 and the semiconductor layer 50, and electron / hole pairs are generated. The generated electrons move along the vertical direction toward the collector electrode 74. In the IGBT 10, there is a region where the electric field strength is zero, and thus the electron movement distance D 60 is limited to the zero region from the interface between the buried insulating film 40 and the semiconductor layer 50. As a result, the avalanche breakdown is suppressed in the IGBT 10.
  • the IGBT 10 includes a surface portion diffusion region 68 on the three-layer structure of the voltage holding portion 60.
  • the voltage holding unit 60 is formed thick, the heat capacity of the voltage holding unit 60 is large. For this reason, even if a high voltage such as static electricity is applied to the IGBT 10, the temperature of the voltage holding unit 60 is suppressed from rising rapidly, and thermal destruction due to static electricity is significantly suppressed.
  • FIG. 4 shows the influence of the thickness of the semiconductor layer 50 on the ESD tolerance of the IGBT 10.
  • the ESD tolerance is a voltage value when the IGBT 10 is thermally destroyed when a high voltage is forcibly applied between the collector electrode 74 and the emitter electrode 87.
  • the horizontal axis represents the ratio of the thickness T60b of the front surface diffusion region 68 to the total vertical thickness T60a of the back surface diffusion region 62, the n-type intermediate diffusion region 64, and the p-type intermediate diffusion region 66.
  • the thickness of the back surface diffusion region 62 is almost negligible, the thickness of the n-type intermediate diffusion region 64 is 0.5 ⁇ m, the thickness of the p-type intermediate diffusion region 66 is 0.5 ⁇ m, and the total The thickness T60a is fixed at 1.0 ⁇ m.
  • thickness ratio (T60b / T60a) becomes large. This is because the heat capacity of the voltage holding unit 60 increases as the thickness T60b of the surface diffusion region 68 increases.
  • the thickness ratio (T60b / T60a) is 1.0 or more (the thickness of the semiconductor layer 50 is 1.0 ⁇ m or more), the effect of increasing the ESD resistance is saturated. Therefore, it can be seen that it is important to set the thickness ratio (T60b / T60a) to 1.0 or more.
  • the IGBT 10 has the four-layer structure of the back surface diffusion region 62, the n-type intermediate diffusion region 64, the p-type intermediate diffusion region 66, and the surface diffusion region 68 in the voltage holding unit 60. Power loss is reduced and ESD tolerance is greatly improved.
  • the technique applied to the voltage holding unit 60 of the IGBT 10 is also useful for, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 11 shown in FIG.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the p + -type collector region 72 of the IGBT 10 is an n + -type drain region 172, and the drain region 172 is ohmically connected to the drain electrode 174.
  • the emitter region 86 of the IGBT 10 is a source region 186, and the source region 186 is ohmically connected to the source electrode 186.
  • MOSFET 11 also has a four-layer structure, so that power loss is reduced and ESD tolerance is greatly improved.
  • the technique applied to the voltage holding unit 60 of the IGBT 10 is also useful for the diode 13 in FIG. 6, for example.
  • the p + -type collector region 72 of the IGBT 10 is an n + -type cathode region 272, and the cathode region 272 is ohmically connected to the cathode electrode 274.
  • the emitter region 86 and the body region 88 of the IGBT 10 are an anode region 288 composed of a contact anode region 288a and a main anode region 288b, and the anode region 288 is connected to the anode electrode 287. Since the diode 13 has a four-layer structure, the power loss is reduced and the ESD tolerance is greatly improved.

Abstract

Disclosed is an IGBT comprising a voltage retention portion which includes an n-type back surface portion diffusion region, an n-type intermediate portion diffusion region, a p-type intermediate portion diffusion region, and an n-type top surface portion diffusion region. The impurity concentration in the back surface portion diffusion region increases laterally from the body region side toward the collector region side.

Description

半導体装置Semiconductor device
　本出願は、２０１０年１月１２日に出願された日本国特許出願第２０１０－００４３５２号に基づく優先権を主張する。その出願の全ての内容は、この明細書中に参照により援用されている。
　本発明は、支持基板と埋込み絶縁膜と半導体層が積層した積層基板を備える半導体装置に関する。 This application claims priority based on Japanese Patent Application No. 2010-004352 filed on Jan. 12, 2010. The entire contents of that application are incorporated herein by reference.
The present invention relates to a semiconductor device including a laminated substrate in which a supporting substrate, a buried insulating film, and a semiconductor layer are laminated.
　支持基板と埋込み絶縁膜と半導体層が積層した積層基板を利用する半導体装置の開発が進められている。積層基板の一例として、ＳＯＩ（Silicon On Insulator）基板が知られている。この種の半導体装置は、高電圧側配線に接続される第１主電極と低電圧側配線に接続される第２主電極が半導体層の表面上に設けられた横型であることが多い。この種の半導体装置には、例えば、コレクタ電極とエミッタ電極が半導体層の表面上に設けられた横型のＩＧＢＴ(Insulated Gate Bipolar Transistor)、アノード電極とカソード電極が半導体層の表面上に設けられた横型のダイオード、ドレイン電極とソース電極が半導体層の表面上に設けられたＭＯＳＦＥＴ(Metal Oxide Semiconductor Field Effect Transistor)が含まれる。この種の半導体装置では、支持基板も低電圧側配線に接続して用いられることが多い。このため、この種の半導体装置では、第１主電極と第２主電極の間の横方向と、第１主電極と支持基板の間の縦方向のそれぞれに電位差が生じる。この種の半導体装置では、これらの間に生じる電位分布を考慮して設計することにより、高耐圧化が図られている。 Development of a semiconductor device using a laminated substrate in which a supporting substrate, a buried insulating film, and a semiconductor layer are laminated is underway. An SOI (Silicon On On Insulator) substrate is known as an example of a laminated substrate. This type of semiconductor device is often a lateral type in which a first main electrode connected to a high-voltage side wiring and a second main electrode connected to a low-voltage side wiring are provided on the surface of a semiconductor layer. In this type of semiconductor device, for example, a lateral IGBT (Insulated Gate Bipolar Transistor) in which a collector electrode and an emitter electrode are provided on the surface of the semiconductor layer, and an anode electrode and a cathode electrode are provided on the surface of the semiconductor layer. A horizontal diode, a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) in which a drain electrode and a source electrode are provided on the surface of a semiconductor layer are included. In this type of semiconductor device, the support substrate is often used connected to the low voltage side wiring. For this reason, in this type of semiconductor device, a potential difference is generated in each of the horizontal direction between the first main electrode and the second main electrode and the vertical direction between the first main electrode and the support substrate. In this type of semiconductor device, the breakdown voltage is increased by designing in consideration of the potential distribution generated between them.
　一般的に、ＳＯＩ基板を利用した半導体装置では、埋込み絶縁膜と半導体層の界面近傍でブレークダウンが発生し、電子・正孔対が生成する。生成した電子は、高電圧側配線に接続される第１主電極に向けて縦方向に沿って移動する。このとき、生成した電子が移動経路中に存在する結晶格子に衝突することにより、さらに、多量の電子が生成され、急激な電流増加が発生する（なだれ降伏）。なだれ降伏が発生すると、最終的には半導体装置の熱破壊を招いてしまう。 Generally, in a semiconductor device using an SOI substrate, breakdown occurs near the interface between a buried insulating film and a semiconductor layer, and electron / hole pairs are generated. The generated electrons move along the vertical direction toward the first main electrode connected to the high voltage side wiring. At this time, the generated electrons collide with the crystal lattice existing in the movement path, so that a larger amount of electrons are generated and a sudden current increase occurs (avalanche breakdown). If avalanche breakdown occurs, the semiconductor device will eventually be thermally destroyed.
　特開２００７－１７３４２２号公報には、半導体層内の電圧保持部に、ｎ型の裏面部半導体領域とｎ－型の中間部半導体領域とｐ型の表面部半導体領域で構成された３層構造を備えた半導体装置が開示されている。この３層構造が電圧保持部に設けられていると、電圧保持部の等電位線が屈曲するという現象が生じる。具体的には、半導体層の縦方向に伸びる等電位線が、埋込み絶縁膜と半導体層の界面近傍において屈曲する。等電位線が屈曲する位置は、縦方向に観察すると、電界強度の正負が反転する領域であり、すなわち、電界強度が零となる領域である。電界強度が零となる領域が存在すると、埋込み絶縁膜と半導体層の界面近傍でブレークダウンが発生したとしても、生成した電子の移動距離が、前記界面からその零領域までに制限される。これにより、特開２００７－１７３４２２号公報の半導体装置では、ブレークダウンによって生成した電子の移動距離が短く制限され、なだれ降伏の発生が抑えられる。 Japanese Patent Laid-Open No. 2007-173422 discloses a three-layer structure in which a voltage holding portion in a semiconductor layer includes an n-type back surface semiconductor region, an n − -type intermediate semiconductor region, and a p-type front surface semiconductor region. There is disclosed a semiconductor device comprising: When this three-layer structure is provided in the voltage holding unit, a phenomenon occurs in which the equipotential lines of the voltage holding unit are bent. Specifically, equipotential lines extending in the vertical direction of the semiconductor layer are bent near the interface between the buried insulating film and the semiconductor layer. The position where the equipotential lines are bent is a region where the positive and negative electric field strengths are reversed when observed in the vertical direction, that is, a region where the electric field strength is zero. If there is a region where the electric field strength is zero, even if breakdown occurs near the interface between the buried insulating film and the semiconductor layer, the distance of movement of the generated electrons is limited to the zero region from the interface. As a result, in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2007-173422, the moving distance of electrons generated by breakdown is limited to be short, and the occurrence of avalanche breakdown is suppressed.
　特開２００７－１７３４２２号公報の半導体装置は、優れた耐圧特性を有しており、多くの用途において有用である。しかしながら、さらに優れた特性を備えた半導体装置が望まれている。本明細書で開示される技術は、積層基板を利用した半導体装置の高耐圧化を実現することを目的としている。 The semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2007-173422 has excellent breakdown voltage characteristics and is useful in many applications. However, a semiconductor device having more excellent characteristics is desired. The technology disclosed in this specification is intended to realize a high breakdown voltage of a semiconductor device using a multilayer substrate.
　本明細書で開示される半導体装置は、電圧保持部の３層構造上に形成されている第４領域をさらに備えていることを特徴としている。電圧保持部の３層構造上に第４領域が形成されていると、電圧保持部の厚みが大きく構成されているので、電圧保持部の熱容量が大きい。例えば、静電気のような高電圧が半導体装置に印加されると、電圧保持部の温度が急激に上昇することが知られている。このような場合、上記半導体装置では、電圧保持部の熱容量が大きいことから、急激な温度上昇を抑えることができる。また、電圧保持部の厚みが大きく構成されているので、電圧保持部の電気抵抗値が低下しており、電力損失も抑えることができる。上記半導体装置は、高耐圧で低損失な特性を有することができる。 The semiconductor device disclosed in this specification is characterized by further including a fourth region formed on the three-layer structure of the voltage holding portion. If the fourth region is formed on the three-layer structure of the voltage holding unit, the voltage holding unit has a large thickness, and thus the heat capacity of the voltage holding unit is large. For example, it is known that when a high voltage such as static electricity is applied to a semiconductor device, the temperature of the voltage holding unit rapidly increases. In such a case, in the semiconductor device, since the heat capacity of the voltage holding unit is large, a rapid temperature rise can be suppressed. Moreover, since the thickness of the voltage holding unit is configured to be large, the electric resistance value of the voltage holding unit is reduced, and power loss can be suppressed. The semiconductor device can have high breakdown voltage and low loss characteristics.
　本明細書で開示される技術によると、高耐圧で低損失な半導体装置が提供される。 According to the technology disclosed in this specification, a semiconductor device with high breakdown voltage and low loss is provided.
実施例のＩＧＢＴの要部断面図を模式的に示す。The principal part sectional drawing of IGBT of an Example is typically shown. 実施例のＩＧＢＴの電力損失に対する半導体層の厚みの影響を示す。The influence of the thickness of the semiconductor layer with respect to the power loss of IGBT of an Example is shown. 電圧保持部の拡大要部断面図を模式的に示す。An expanded principal part sectional view of a voltage holding part is shown typically. 実施例のＩＧＢＴのＥＳＤ耐量に対する半導体層の厚みの影響を示す。The influence of the thickness of the semiconductor layer with respect to ESD tolerance of IGBT of an Example is shown. 実施例のＭＯＳＦＥＴの要部断面図を模式的に示す。The principal part sectional drawing of MOSFET of an Example is typically shown. 実施例のダイオードの要部断面図を模式的に示す。The principal part sectional drawing of the diode of an Example is typically shown.
　本明細書で開示される技術は、支持基板と埋込み絶縁膜と半導体層が積層した積層基板を有する半導体装置に具現化される。半導体装置はさらに、第１主電極と第２主電極と電圧保持部を備えている。第１主電極は、半導体層の表面上に設けられている。第２主電極は、半導体層の表面上に設けられており、第１主電極から絶縁されている。電圧保持部は、半導体層内に形成されており、第１主電極と第２主電極の間に加わる電圧を保持する。電圧保持部は、第１導電型の第１領域と、その第１領域上に設けられている第１導電型の第２領域と、その第２領域上に設けられている第２導電型の第３領域と、その第３領域上に設けられている第１導電型の第４領域を有している。第１領域の不純物濃度は、横方向に沿って変化する。ここで、第１領域の不純物濃度は、横方向に沿って連続的に変化してもよく、横方向に沿って段階的に変化してもよい。また、電圧保持部は、第１領域と第２領域と第３領域と第４領域以外の領域をさらに備えていてもよい。上記半導体装置は、電圧保持部に第１領域と第２領域と第３領域で構成される３層構造を備えている。このため、半導体層の厚み方向に伸びる等電位線が、埋込み絶縁膜と半導体層の界面近傍において屈曲する。この結果、上記半導体装置では、埋込み絶縁膜と半導体層の界面近傍において、電界強度が零となる領域が形成されており、なだれ降伏の発生が抑えられている。さらに、上記半導体装置は、電圧保持部の３層構造上に第４領域を備えている。これにより、電圧保持部の厚みが大きく構成されているので、電圧保持部の熱容量が大きい。例えば、静電気のような高電圧が半導体装置に印加されると、電圧保持部の温度が急激に上昇することが知られている。このような場合、上記半導体装置では、電圧保持部の熱容量が大きいことから、急激な温度上昇を抑えることができる。また、電圧保持部の厚みが大きく構成されているので、電圧保持部の電気抵抗値が低下しており、電力損失も抑えることができる。上記半導体装置は、高耐圧で低損失な特性を有することができる。 The technology disclosed in this specification is embodied in a semiconductor device having a stacked substrate in which a support substrate, a buried insulating film, and a semiconductor layer are stacked. The semiconductor device further includes a first main electrode, a second main electrode, and a voltage holding unit. The first main electrode is provided on the surface of the semiconductor layer. The second main electrode is provided on the surface of the semiconductor layer and is insulated from the first main electrode. The voltage holding unit is formed in the semiconductor layer and holds a voltage applied between the first main electrode and the second main electrode. The voltage holding unit includes a first conductivity type first region, a first conductivity type second region provided on the first region, and a second conductivity type provided on the second region. It has the 3rd field and the 4th field of the 1st conductivity type provided on the 3rd field. The impurity concentration in the first region changes along the horizontal direction. Here, the impurity concentration of the first region may change continuously along the horizontal direction or may change stepwise along the horizontal direction. The voltage holding unit may further include a region other than the first region, the second region, the third region, and the fourth region. The semiconductor device includes a three-layer structure including a first region, a second region, and a third region in the voltage holding unit. For this reason, equipotential lines extending in the thickness direction of the semiconductor layer are bent near the interface between the buried insulating film and the semiconductor layer. As a result, in the semiconductor device, a region where the electric field strength is zero is formed in the vicinity of the interface between the buried insulating film and the semiconductor layer, and avalanche breakdown is suppressed. Furthermore, the semiconductor device includes a fourth region on the three-layer structure of the voltage holding unit. Thereby, since the thickness of a voltage holding part is comprised large, the heat capacity of a voltage holding part is large. For example, it is known that when a high voltage such as static electricity is applied to a semiconductor device, the temperature of the voltage holding unit rapidly increases. In such a case, in the semiconductor device, since the heat capacity of the voltage holding unit is large, a rapid temperature rise can be suppressed. Moreover, since the thickness of the voltage holding unit is configured to be large, the electric resistance value of the voltage holding unit is reduced, and power loss can be suppressed. The semiconductor device can have high breakdown voltage and low loss characteristics.
　上記半導体装置は、半導体層内に形成されており、第２主電極に接続される第２導電型の第５領域をさらに備えていてもよい。この場合、第３領域と第５領域が接していてもよい。この態様によると、第３領域の電位が安定するので、電圧保持部の広い範囲が良好に空乏化され得る。 The semiconductor device may further include a fifth region of the second conductivity type formed in the semiconductor layer and connected to the second main electrode. In this case, the third region and the fifth region may be in contact with each other. According to this aspect, since the potential of the third region is stabilized, a wide range of the voltage holding unit can be well depleted.
　上記半導体装置では、第１領域の不純物濃度が、第５領域から離れる向きに増加してもよい。この態様によると、電圧保持部において、等電位線の屈曲現象が良好に生じ得る。 In the semiconductor device, the impurity concentration in the first region may increase in a direction away from the fifth region. According to this aspect, the bending phenomenon of the equipotential lines can occur favorably in the voltage holding unit.
　第１領域の不純物濃度は、第２領域の不純物濃度よりも薄くてもよい。第４領域の不純物濃度は、第１領域の不純物濃度よりも薄くてもよい。この態様によると、等電位線の屈曲する位置が、埋込み絶縁膜と半導体層の界面近傍により近くなり得る。ブレークダウンで発生した電子の縦方向の移動距離がより短くなり、なだれ降伏がより抑制され得る。 The impurity concentration in the first region may be lower than the impurity concentration in the second region. The impurity concentration in the fourth region may be lower than the impurity concentration in the first region. According to this aspect, the position where the equipotential line bends can be closer to the vicinity of the interface between the buried insulating film and the semiconductor layer. The longitudinal movement distance of electrons generated in the breakdown becomes shorter, and avalanche breakdown can be further suppressed.
　第４領域の厚みは、第１領域と第２領域と第３領域の合計の厚みよりも厚くてもよい。この態様によると、ＥＳＤ(Electro Static Discharge)耐量が向上することが本発明者により確認されている。より好ましくは、第４領域の厚みは、第１領域と第２領域と第３領域の合計の厚みの１．５倍以上であっても良い。この態様によると、ＥＳＤ耐量に加えて、電力損失も顕著に改善され得る。 The thickness of the fourth region may be larger than the total thickness of the first region, the second region, and the third region. According to this aspect, the present inventors have confirmed that ESD (Electro Static Discharge) resistance is improved. More preferably, the thickness of the fourth region may be 1.5 times or more the total thickness of the first region, the second region, and the third region. According to this aspect, in addition to the ESD tolerance, the power loss can be significantly improved.
　上記半導体装置は、バイポーラで動作してもよい。バイポーラで動作すると、第４領域の電気抵抗値が伝導度変調によって低下する。このため、厚みの大きい第４領域を設けるメリットを良好に享受することができる。電力損失の小さい半導体装置が具現化され得る。 The semiconductor device may operate in a bipolar manner. When operating in a bipolar manner, the electric resistance value in the fourth region decreases due to conductivity modulation. For this reason, the merit which provides the 4th area | region with large thickness can be enjoyed favorably. A semiconductor device with low power loss can be realized.
　上記半導体装置では、第１領域がｎ型の裏面部拡散領域であり、第２領域がｎ型中間部拡散領域であり、第３領域がｐ型中間部拡散領域であり、第４領域がｎ型の表面部拡散領域であってもよい。 In the semiconductor device, the first region is an n-type back surface diffusion region, the second region is an n-type intermediate region, the third region is a p-type intermediate region, and the fourth region is n. It may be a surface diffusion region of the mold.
　上記半導体装置では、裏面部拡散領域とｎ型中間部拡散領域とｐ型中間部拡散領域と表面部拡散領域はその順で積層しており、４層構造を構成してもよい。 In the above semiconductor device, the back surface diffusion region, the n-type intermediate region diffusion region, the p-type intermediate region diffusion region, and the front surface region diffusion region may be laminated in this order, and a four-layer structure may be formed.
　上記半導体装置では、裏面部拡散領域の不純物濃度は、横方向に変化してもよい。ｎ型中間部拡散領域とｐ型中間部拡散領域と表面部拡散領域の不純物濃度は、横方向に略一定であってもよい。 In the semiconductor device, the impurity concentration in the back surface diffusion region may change in the lateral direction. The impurity concentration of the n-type intermediate diffusion region, the p-type intermediate diffusion region, and the surface diffusion region may be substantially constant in the lateral direction.
　上記半導体装置では、４層構造の厚みは、好ましくは２μｍ以上、より好ましくは２．５μｍ以上である。 In the above semiconductor device, the thickness of the four-layer structure is preferably 2 μm or more, more preferably 2.5 μm or more.
　以下、図面を参照して各実施例の半導体装置を説明する。以下の各実施例では、半導体材料に単結晶シリコンが用いられているが、この例に代えて、窒化ガリウム、炭化珪素、ガリウム砒素等の化合物半導体が用いられてもよい。また、各実施例において実質的に共通する構成要素に関しては共通の符号を付し、その説明を省略する。 Hereinafter, the semiconductor device of each embodiment will be described with reference to the drawings. In each of the following embodiments, single crystal silicon is used as a semiconductor material, but a compound semiconductor such as gallium nitride, silicon carbide, or gallium arsenide may be used instead of this example. In addition, components that are substantially common to the embodiments are denoted by common reference numerals, and description thereof is omitted.
　図１に、ＩＧＢＴ(Insulated Gate Bipolar Transistor)１０の要部断面図を模式的に示す。ＩＧＢＴ１０は、単結晶シリコンの支持基板３０と酸化シリコンの埋込み絶縁膜４０と単結晶シリコンの半導体層５０が積層したＳＯＩ(Silicon on Insulator)基板２０を備えている。支持基板３０は、ｐ型の不純物を高濃度に含んでおり、低電圧側配線に接続されている。低電圧側配線は、電源電圧の負極性側に接続されており、一例では接地電位に固定されている。埋込み絶縁膜４０は、ｙ軸方向（以下、縦方向という）の厚みが約３．０～５．０μｍであるのが望ましい。また、埋込み絶縁膜４０の材料は、比誘電率が小さい材料が望ましい。半導体層５０は、ｎ型の不純物を低濃度に含んでおり、縦方向の厚みが約２．０μｍ以上、より好ましくは約２．５μｍ以上であるのが望ましい。なお、半導体層５０の縦方向の厚みは、素子分離のための製造コストが増加するのを抑えるために、約５．０μｍ以下にするのが望ましい。半導体層５０の抵抗率は、機械的強度が保たれるように、約１～１００ｍΩ・ｃｍであるのが望ましい。 FIG. 1 schematically shows a cross-sectional view of an essential part of an IGBT (Insulated Gate Bipolar Transistor) 10. The IGBT 10 includes an SOI (Silicon On Insulator) substrate 20 in which a single crystal silicon support substrate 30, a silicon oxide buried insulating film 40, and a single crystal silicon semiconductor layer 50 are stacked. The support substrate 30 contains p-type impurities at a high concentration, and is connected to the low-voltage side wiring. The low voltage side wiring is connected to the negative polarity side of the power supply voltage, and is fixed to the ground potential in one example. The buried insulating film 40 preferably has a thickness in the y-axis direction (hereinafter referred to as the vertical direction) of about 3.0 to 5.0 μm. The material of the buried insulating film 40 is preferably a material having a low relative dielectric constant. The semiconductor layer 50 contains n-type impurities at a low concentration, and the thickness in the vertical direction is preferably about 2.0 μm or more, more preferably about 2.5 μm or more. The vertical thickness of the semiconductor layer 50 is preferably about 5.0 μm or less in order to suppress an increase in manufacturing cost for element isolation. The resistivity of the semiconductor layer 50 is preferably about 1 to 100 mΩ · cm so that the mechanical strength is maintained.
　ＩＧＢＴ１０は、半導体層５０の表面上に設けられているコレクタ電極７４（第１主電極の一例）とコレクタポリプレート電極７８とＬＯＣＯＳ(Local Oxidation of Silicon)膜６９とゲート電極８４とエミッタ電極８７（第２主電極の一例）を備えている。コレクタ電極７４は、高電圧側配線に接続されている。高電圧側配線は、電源電圧の正極性側に接続されている。コレクタ電極７４の材料は、一例ではアルミニウムである。コレクタポリプレート電極７８は、コレクタ電極７４とゲート電極８４の間に設けられており、酸化シリコンの絶縁膜を介して半導体層５０及びＬＯＣＯＳ膜６９の表面に対向している。コレクタポリプレート電極７８がＬＯＣＯＳ膜６９の表面を被覆するｘ軸方向（以下、横方向という）の横幅は、約１～５μｍである。コレクタポリプレート電極７８は、高電圧側配線に接続されている。コレクタポリプレート電極７８の材料は、一例ではポリシリコンである。ＬＯＣＯＳ膜６９は、縦方向の厚みが約０．２５～０．５μｍであるのが望ましい。ＬＯＣＯＳ膜６９の材料は、一例では酸化シリコンである。ゲート電極８４は、コレクタポリプレート電極７８とエミッタ電極８７の間に設けられており、酸化シリコンのゲート絶縁膜８２を介して半導体層５０及びＬＯＣＯＳ膜６９の表面に対向している。ゲート電極８４がＬＯＣＯＳ膜６９の表面を被覆する横方向の横幅は、約１～５μｍである。ゲート電極８４の材料は、一例ではポリシリコンである。エミッタ電極８７は、低電圧側配線に接続されている。エミッタ電極８７の材料は、一例ではアルミニウムである。 The IGBT 10 includes a collector electrode 74 (an example of a first main electrode), a collector polyplate electrode 78, a LOCOS (Local Oxidation of Silicon) film 69, a gate electrode 84, and an emitter electrode 87 (on the surface of the semiconductor layer 50). An example of a second main electrode). The collector electrode 74 is connected to the high voltage side wiring. The high voltage side wiring is connected to the positive polarity side of the power supply voltage. The material of the collector electrode 74 is aluminum in one example. The collector polyplate electrode 78 is provided between the collector electrode 74 and the gate electrode 84, and faces the surface of the semiconductor layer 50 and the LOCOS film 69 through an insulating film of silicon oxide. The lateral width in the x-axis direction (hereinafter referred to as the lateral direction) where the collector polyplate electrode 78 covers the surface of the LOCOS film 69 is about 1 to 5 μm. The collector polyplate electrode 78 is connected to the high voltage side wiring. The material of the collector polyplate electrode 78 is polysilicon in one example. The LOCOS film 69 preferably has a vertical thickness of about 0.25 to 0.5 μm. The material of the LOCOS film 69 is, for example, silicon oxide. The gate electrode 84 is provided between the collector polyplate electrode 78 and the emitter electrode 87, and faces the surfaces of the semiconductor layer 50 and the LOCOS film 69 with a silicon oxide gate insulating film 82 interposed therebetween. The lateral width in which the gate electrode 84 covers the surface of the LOCOS film 69 is about 1 to 5 μm. In one example, the material of the gate electrode 84 is polysilicon. The emitter electrode 87 is connected to the low voltage side wiring. In one example, the material of the emitter electrode 87 is aluminum.
　ＩＧＢＴ１０は、半導体層５０内に形成されているコレクタ領域７２とバッファ領域７６と裏面部拡散領域６２とｎ型中間部拡散領域６４とｐ型中間部拡散領域６６と表面部拡散領域６８とエミッタ領域８６とボディ領域８８を備えている。ここで、本願明細書では、一方の主電極であるコレクタ電極７４に電気的に接続されるコレクタ領域７２と他方の主電極であるエミッタ電極８７に電気的に接続されるボディ領域８８の間の領域を電圧保持部６０と称する。電圧保持部６０は、ＬＯＣＯＳ膜６９の下方に位置する領域ということもできる。また、電圧保持部６０は、キャリアが流れる領域であり、ドリフト領域ということもできる。 The IGBT 10 includes a collector region 72, a buffer region 76, a back surface diffusion region 62, an n-type intermediate diffusion region 64, a p-type intermediate diffusion region 66, a surface diffusion region 68, and an emitter region formed in the semiconductor layer 50. 86 and a body region 88. Here, in the present specification, between the collector region 72 electrically connected to the collector electrode 74 which is one main electrode and the body region 88 electrically connected to the emitter electrode 87 which is the other main electrode. The region is referred to as a voltage holding unit 60. It can also be said that the voltage holding unit 60 is a region located below the LOCOS film 69. The voltage holding unit 60 is a region where carriers flow, and can also be called a drift region.
　コレクタ領域７２は、イオン注入技術を利用して、半導体層５０の表層部に形成されている。コレクタ領域７２は、ｐ型の不純物を高濃度に含んでおり、コレクタ電極７４にオーミック接続されている。バッファ領域７６は、イオン注入技術を利用して、半導体層５０の表層部に形成されている。バッファ領域７６は、コレクタ領域７２を取囲んでおり、ｎ型の不純物を含んでいる。 The collector region 72 is formed in the surface layer portion of the semiconductor layer 50 using an ion implantation technique. The collector region 72 contains p-type impurities at a high concentration and is ohmically connected to the collector electrode 74. The buffer region 76 is formed in the surface layer portion of the semiconductor layer 50 using an ion implantation technique. The buffer region 76 surrounds the collector region 72 and contains n-type impurities.
　エミッタ領域８６は、イオン注入技術を利用して、半導体層５０の表層部に形成されている。エミッタ領域８６は、ｎ型の不純物を高濃度に含んでおり、エミッタ電極８７にオーミック接続されている。ボディ領域８８（第５領域の一例）は、イオン注入技術を利用して、半導体層５０の表面から裏面に達するように形成されている。ボディ領域８８は、コンタクトボディ領域８８ａとメインボディ領域８８ｂを有しており、ｐ型の不純物を含んでいる。コンタクトボディ領域８８ａは、エミッタ電極８７にオーミック接続されている。メインボディ領域８８ｂは、コンタクトボディ領域８８ａを介してエミッタ電極８７に接続されている。 The emitter region 86 is formed in the surface layer portion of the semiconductor layer 50 using an ion implantation technique. The emitter region 86 contains an n-type impurity at a high concentration and is ohmically connected to the emitter electrode 87. The body region 88 (an example of the fifth region) is formed so as to reach the back surface from the front surface of the semiconductor layer 50 using an ion implantation technique. Body region 88 has contact body region 88a and main body region 88b, and contains p-type impurities. Contact body region 88 a is ohmically connected to emitter electrode 87. Main body region 88b is connected to emitter electrode 87 through contact body region 88a.
　電圧保持部６０は、裏面部拡散領域６２（第１領域の一例）とｎ型中間部拡散領域６４（第２領域の一例）とｐ型中間部拡散領域６６（第３領域の一例）と表面部拡散領域６８（第４領域の一例）を備えており、これらの拡散領域はその順で積層している。 The voltage holding unit 60 includes a back surface diffusion region 62 (an example of a first region), an n-type intermediate region diffusion region 64 (an example of a second region), a p-type intermediate region diffusion region 66 (an example of a third region), and a surface. A partial diffusion region 68 (an example of a fourth region) is provided, and these diffusion regions are stacked in that order.
　裏面部拡散領域６２は、イオン注入技術を利用して、埋込み絶縁膜４０と半導体層５０の界面近傍に形成されている。裏面部拡散領域６２は、イオン注入技術を利用して形成される際に、導入されるドーパント濃度のピーク位置（飛程位置ともいう）が埋込み絶縁膜４０と半導体層５０の界面に設定されるのが望ましい。好ましくは、ドーパント濃度のピーク位置が埋込み絶縁膜４０と半導体層５０の界面から半導体層５０の表面に向けて約０．５μｍ以下、より好ましくは約０．２μｍ以下であるのが望ましい。裏面部拡散領域６２は、ｎ型の不純物を含んでおり、不純物濃度が異なる８つの部分領域６２ａ～６２ｈで構成されている。部分領域６２ａ～６２ｈの不純物濃度は、ボディ領域８８側からコレクタ領域７２側に向けて増加している。すなわち、符号６２ａで示される部分領域の不純物濃度が最も薄く、符号６２ｈで示される部分領域の不純物濃度が最も濃い。ただし、符号６２ａで示される部分領域の不純物濃度は、表面部拡散領域６８の不純物濃度よりも濃い。また、符号６２ｈで示される部分領域の不純物濃度は、ｎ型中間部拡散領域６４の不純物濃度よりも薄い。一例では、符号６２ａで示される部分領域の不純物濃度が約１×１０１５～１×１０１６であり、符号６２ｈで示される部分領域の不純物濃度が約８×１０１５～８×１０１５であるのが望ましい。 The back surface diffusion region 62 is formed in the vicinity of the interface between the buried insulating film 40 and the semiconductor layer 50 using an ion implantation technique. When the back surface diffusion region 62 is formed using an ion implantation technique, the peak position (also referred to as a range position) of the introduced dopant concentration is set at the interface between the buried insulating film 40 and the semiconductor layer 50. Is desirable. Preferably, the peak position of the dopant concentration is about 0.5 μm or less, more preferably about 0.2 μm or less from the interface between the buried insulating film 40 and the semiconductor layer 50 toward the surface of the semiconductor layer 50. The back surface diffusion region 62 includes n-type impurities and is composed of eight partial regions 62a to 62h having different impurity concentrations. The impurity concentrations of the partial regions 62a to 62h increase from the body region 88 side toward the collector region 72 side. That is, the impurity concentration of the partial region indicated by reference numeral 62a is the lowest, and the impurity concentration of the partial region indicated by reference numeral 62h is the highest. However, the impurity concentration of the partial region indicated by reference numeral 62 a is higher than the impurity concentration of the surface diffusion region 68. Further, the impurity concentration of the partial region indicated by reference numeral 62 h is lower than the impurity concentration of the n-type intermediate diffusion region 64. In one example, the impurity concentration of the partial region indicated by reference numeral 62a is approximately 1 × 10 15 to 1 × 10 16 , and the impurity concentration of the partial region indicated by reference numeral 62h is approximately 8 × 10 15 to 8 × 10 15 . Is desirable.
　ｎ型中間部拡散領域６４は、イオン注入技術を利用して、裏面部拡散領域６２上に形成されている。ｎ型中間部拡散領域６４は、一端がボディ領域８８に接触しており、他端がバッファ領域７６から離反している。ｎ型中間部拡散領域６４は、ｎ型の不純物を含んでおり、横方向の不純物濃度は略一定である。一例では、ｎ型中間部拡散領域６４の不純物濃度は、約１×１０１６～１×１０１７ｃｍ－３であるのが望ましい。 The n-type intermediate portion diffusion region 64 is formed on the back surface diffusion region 62 using an ion implantation technique. One end of n-type intermediate diffusion region 64 is in contact with body region 88 and the other end is separated from buffer region 76. The n-type intermediate diffusion region 64 contains n-type impurities, and the impurity concentration in the lateral direction is substantially constant. In one example, the impurity concentration of the n-type intermediate diffusion region 64 is preferably about 1 × 10 16 to 1 × 10 17 cm −3 .
　ｐ型中間部拡散領域６６は、イオン注入技術を利用して、ｎ型中間部拡散領域６４上に形成されている。ｐ型中間部拡散領域６６は、一端がボディ領域８８に接触しており、他端がバッファ領域７６から離反している。ｐ型中間部拡散領域６６は、ｐ型の不純物を含んでおり、横方向の不純物濃度は略一定である。一例では、ｐ型中間部拡散領域６６の不純物濃度は、約１×１０１６～１×１０１７ｃｍ－３であるのが望ましい。 The p-type intermediate diffusion region 66 is formed on the n-type intermediate diffusion region 64 using an ion implantation technique. One end of p-type intermediate diffusion region 66 is in contact with body region 88 and the other end is separated from buffer region 76. The p-type intermediate diffusion region 66 contains p-type impurities, and the impurity concentration in the lateral direction is substantially constant. In one example, the impurity concentration of the p-type intermediate diffusion region 66 is desirably about 1 × 10 16 to 1 × 10 17 cm −3 .
　ｐ型中間部拡散領域６６とｎ型中間部拡散領域６４の製造工程では、製造コストを抑制するために、イオン注入用マスクを共通とすることができる。このため、ｐ型中間部拡散領域６６とｎ型中間部拡散領域６４の形成位置は、平面視したときに共通している。 In the manufacturing process of the p-type intermediate part diffusion region 66 and the n-type intermediate part diffusion region 64, a common ion implantation mask can be used in order to reduce the manufacturing cost. For this reason, the formation positions of the p-type intermediate diffusion region 66 and the n-type intermediate diffusion region 64 are common when viewed in plan.
　裏面部拡散領域６２とｎ型中間部拡散領域６４とｐ型中間部拡散領域６６の合計の縦方向の厚みＴ６０ａは、薄い方が望ましい。合計の厚みＴ６０ａが薄いほど、後述するように、等電位線の屈曲位置が埋込み絶縁膜４０と半導体層５０の界面近傍に近くなる。なお、裏面部拡散領域６２の縦方向の厚みはほぼ無視できるほどに薄いのが望ましい。ｎ型中間部拡散領域６４の縦方向の厚みは、約０．５μｍ以下、より好ましくは０．２μｍ以下であるのが望ましい。ｐ型中間部拡散領域６６の縦方向の厚みは、約０．５μｍ以下、より好ましくは０．２μｍ以下であるのが望ましい。 The total vertical thickness T60a of the back surface diffusion region 62, the n-type intermediate diffusion region 64, and the p-type intermediate diffusion region 66 is desirably thinner. As the total thickness T60a is thinner, the equipotential line is bent closer to the vicinity of the interface between the buried insulating film 40 and the semiconductor layer 50, as will be described later. It is desirable that the thickness of the back surface diffusion region 62 in the vertical direction is so thin that it can be almost ignored. It is desirable that the vertical thickness of the n-type intermediate diffusion region 64 is about 0.5 μm or less, more preferably 0.2 μm or less. It is desirable that the vertical thickness of the p-type intermediate diffusion region 66 is about 0.5 μm or less, more preferably 0.2 μm or less.
　表面部拡散領域６８は、他の拡散領域を形成した後の残部であり、ｐ型中間部拡散領域６６上に形成されている。表面部拡散領域６８は、一端がボディ領域８８に接触しており、他端がバッファ領域７６に接触している。表面部拡散領域６８は、ｎ型の不純物を含んでおり、不純物濃度は約１×１０１５～１×１０１６ｃｍ－３であるのが望ましい。表面部拡散領域６８の縦方向の厚みＴ６０ｂは、約１．０μｍ以上、より好ましくは約１．５μｍ以上であるのが望ましい。 The surface portion diffusion region 68 is a remaining portion after other diffusion regions are formed, and is formed on the p-type intermediate region diffusion region 66. One end of the surface diffusion region 68 is in contact with the body region 88 and the other end is in contact with the buffer region 76. The surface diffusion region 68 contains n-type impurities, and the impurity concentration is preferably about 1 × 10 15 to 1 × 10 16 cm −3 . It is desirable that the vertical thickness T60b of the surface diffusion region 68 is about 1.0 μm or more, more preferably about 1.5 μm or more.
　次に、ＩＧＢＴ１０の動作を説明する。ゲート電極８４に数Ｖ程度の正電圧が印加されると、ゲート電極８４が対向するメインボディ領域８８ｂの表層部に反転層が形成され、ＩＧＢＴ１０がオンする。ＩＧＢＴ１０のオン状態では、エミッタ領域８６から電圧保持部６０に電子が注入され、コレクタ領域７２から電圧保持部６０に正孔が注入され、電圧保持部６０は伝導度変調される。 Next, the operation of the IGBT 10 will be described. When a positive voltage of about several volts is applied to the gate electrode 84, an inversion layer is formed in the surface layer portion of the main body region 88b opposed to the gate electrode 84, and the IGBT 10 is turned on. In the ON state of the IGBT 10, electrons are injected from the emitter region 86 into the voltage holding unit 60, holes are injected from the collector region 72 into the voltage holding unit 60, and the conductivity of the voltage holding unit 60 is modulated.
　図２に、ＩＧＢＴ１０の電力損失に対する半導体層５０の厚みの影響を示す。横軸は、裏面部拡散領域６２とｎ型中間部拡散領域６４とｐ型中間部拡散領域６６の合計の縦方向の厚みＴ６０ａに対する表面部拡散領域６８の厚みＴ６０ｂの比である。なお、図２では、裏面部拡散領域６２の厚みがほぼ無視できるとし、ｎ型中間部拡散領域６４の厚みを０．５μｍとし、ｐ型中間部拡散領域６６の厚みを０．５μｍとし、合計の厚みＴ６０ａを１．０μｍで固定としている。図２に示されるように、厚み比（Ｔ６０ｂ／Ｔ６０ａ）が大きくなるほど、電力損失が低下することが分かる。これは、表面部拡散領域６８の厚みＴ６０ｂが増加することにより、伝導度変調により低抵抗化された表面部拡散領域６８のドリフト抵抗が低下するからである。なお、図２に示されるように、厚み比（Ｔ６０ｂ／Ｔ６０ａ）が１．５以上（半導体層５０の厚みが２．５μｍ以上でもある）になると、電力損失の低下効果がほぼ飽和する。したがって、厚み比（Ｔ６０ｂ／Ｔ６０ａ）を１．５以上にすることが肝要であることが分かる。 FIG. 2 shows the influence of the thickness of the semiconductor layer 50 on the power loss of the IGBT 10. The horizontal axis represents the ratio of the thickness T60b of the front surface diffusion region 68 to the total vertical thickness T60a of the back surface diffusion region 62, the n-type intermediate diffusion region 64, and the p-type intermediate diffusion region 66. In FIG. 2, the thickness of the back surface diffusion region 62 is almost negligible, the thickness of the n-type intermediate diffusion region 64 is 0.5 μm, the thickness of the p-type intermediate diffusion region 66 is 0.5 μm, and the total The thickness T60a is fixed at 1.0 μm. As FIG. 2 shows, it turns out that power loss falls, so that thickness ratio (T60b / T60a) becomes large. This is because as the thickness T60b of the surface portion diffusion region 68 increases, the drift resistance of the surface portion diffusion region 68 that has been reduced in resistance by conductivity modulation decreases. As shown in FIG. 2, when the thickness ratio (T60b / T60a) is 1.5 or more (the thickness of the semiconductor layer 50 is 2.5 μm or more), the effect of reducing the power loss is almost saturated. Therefore, it can be seen that it is important to set the thickness ratio (T60b / T60a) to 1.5 or more.
　ゲート電極８４が接地電位に切換わると、メインボディ領域８８ｂの表層部の反転層が消失し、ＩＧＢＴ１０はオフとなる。ＩＧＢＴ１０のオフ状態では、電圧保持部６０が広い範囲に亘って空乏化される。 When the gate electrode 84 is switched to the ground potential, the inversion layer in the surface layer portion of the main body region 88b disappears, and the IGBT 10 is turned off. In the off state of the IGBT 10, the voltage holding unit 60 is depleted over a wide range.
　図３に、電圧保持部６０の一部を拡大した拡大要部断面図を示す。図３には、ＩＧＢＴ１０がオフしたときの等電位線分布が重ねて示されている。図３に示されるように、ＩＧＢＴ１０は、裏面部拡散領域６２とｎ型中間部拡散領域６４とｐ型中間部拡散領域６６で構成される３層構造を備えている。このため、半導体層５０の厚み方向に伸びる等電位線が、埋込み絶縁膜４０と半導体層５０の界面近傍において屈曲する。この等電位線が屈曲する領域は、縦方向に観測したときに電界強度が零になる領域である。通常、ＩＧＢＴ１０に高電圧が加わると、埋込み絶縁膜４０と半導体層５０の界面近傍でブレークダウンが発生し、電子・正孔対が発生する。生成した電子は、コレクタ電極７４に向けて縦方向に沿って移動する。ＩＧＢＴ１０では、電界強度が零となる領域が存在しているので、電子の縦方向の移動距離Ｄ６０は、埋込み絶縁膜４０と半導体層５０の界面から零領域までに制限される。この結果、ＩＧＢＴ１０ではなだれ降伏の発生が抑えられている。 FIG. 3 shows an enlarged cross-sectional view of a main part in which a part of the voltage holding unit 60 is enlarged. FIG. 3 shows the equipotential line distribution when the IGBT 10 is turned off. As shown in FIG. 3, the IGBT 10 has a three-layer structure including a back surface diffusion region 62, an n-type intermediate region diffusion region 64, and a p-type intermediate region diffusion region 66. For this reason, equipotential lines extending in the thickness direction of the semiconductor layer 50 are bent in the vicinity of the interface between the buried insulating film 40 and the semiconductor layer 50. The region where the equipotential lines are bent is a region where the electric field intensity becomes zero when observed in the vertical direction. Normally, when a high voltage is applied to the IGBT 10, breakdown occurs near the interface between the buried insulating film 40 and the semiconductor layer 50, and electron / hole pairs are generated. The generated electrons move along the vertical direction toward the collector electrode 74. In the IGBT 10, there is a region where the electric field strength is zero, and thus the electron movement distance D 60 is limited to the zero region from the interface between the buried insulating film 40 and the semiconductor layer 50. As a result, the avalanche breakdown is suppressed in the IGBT 10.
　さらに、ＩＧＢＴ１０は、電圧保持部６０の３層構造上に表面部拡散領域６８を備えている。これにより、電圧保持部６０が厚く構成されているので、電圧保持部６０の熱容量が大きい。このため、静電気のような高い電圧がＩＧＢＴ１０に印加されたとしても、電圧保持部６０の温度が急激に上昇することが抑制されており、静電気による熱破壊が顕著に抑制される。 Furthermore, the IGBT 10 includes a surface portion diffusion region 68 on the three-layer structure of the voltage holding portion 60. Thereby, since the voltage holding unit 60 is formed thick, the heat capacity of the voltage holding unit 60 is large. For this reason, even if a high voltage such as static electricity is applied to the IGBT 10, the temperature of the voltage holding unit 60 is suppressed from rising rapidly, and thermal destruction due to static electricity is significantly suppressed.
　図４に、ＩＧＢＴ１０のＥＳＤ耐量に対する半導体層５０の厚みの影響を示す。ＥＳＤ耐量は、コレクタ電極７４とエミッタ電極８７の間に強制的に高電圧を印加したときに、ＩＧＢＴ１０が熱破壊されるときの電圧値である。横軸は、裏面部拡散領域６２とｎ型中間部拡散領域６４とｐ型中間部拡散領域６６の合計の縦方向の厚みＴ６０ａに対する表面部拡散領域６８の厚みＴ６０ｂの比である。なお、図４では、裏面部拡散領域６２の厚みがほぼ無視できるとし、ｎ型中間部拡散領域６４の厚みを０．５μｍとし、ｐ型中間部拡散領域６６の厚みを０．５μｍとし、合計の厚みＴ６０ａを１．０μｍで固定としている。図４に示されるように、厚み比（Ｔ６０ｂ／Ｔ６０ａ）が大きくなるほど、ＥＳＤ耐量が向上することが分かる。これは、表面部拡散領域６８の厚みＴ６０ｂが増加することにより、電圧保持部６０の熱容量が増加するからである。なお、図４に示されるように、厚み比（Ｔ６０ｂ／Ｔ６０ａ）が１．０以上（半導体層５０の厚みが１．０μｍ以上でもある）になると、ＥＳＤ耐量の増加効果が飽和する。したがって、厚み比（Ｔ６０ｂ／Ｔ６０ａ）を１．０以上にすることが肝要であることが分かる。 FIG. 4 shows the influence of the thickness of the semiconductor layer 50 on the ESD tolerance of the IGBT 10. The ESD tolerance is a voltage value when the IGBT 10 is thermally destroyed when a high voltage is forcibly applied between the collector electrode 74 and the emitter electrode 87. The horizontal axis represents the ratio of the thickness T60b of the front surface diffusion region 68 to the total vertical thickness T60a of the back surface diffusion region 62, the n-type intermediate diffusion region 64, and the p-type intermediate diffusion region 66. In FIG. 4, the thickness of the back surface diffusion region 62 is almost negligible, the thickness of the n-type intermediate diffusion region 64 is 0.5 μm, the thickness of the p-type intermediate diffusion region 66 is 0.5 μm, and the total The thickness T60a is fixed at 1.0 μm. As FIG. 4 shows, it turns out that ESD tolerance improves, so that thickness ratio (T60b / T60a) becomes large. This is because the heat capacity of the voltage holding unit 60 increases as the thickness T60b of the surface diffusion region 68 increases. As shown in FIG. 4, when the thickness ratio (T60b / T60a) is 1.0 or more (the thickness of the semiconductor layer 50 is 1.0 μm or more), the effect of increasing the ESD resistance is saturated. Therefore, it can be seen that it is important to set the thickness ratio (T60b / T60a) to 1.0 or more.
　上記したように、ＩＧＢＴ１０は、電圧保持部６０に、裏面部拡散領域６２とｎ型中間部拡散領域６４とｐ型中間部拡散領域６６と表面部拡散領域６８の４層構造を有することにより、電力損失が低減され、ＥＳＤ耐量が大きく向上する。 As described above, the IGBT 10 has the four-layer structure of the back surface diffusion region 62, the n-type intermediate diffusion region 64, the p-type intermediate diffusion region 66, and the surface diffusion region 68 in the voltage holding unit 60. Power loss is reduced and ESD tolerance is greatly improved.
　ＩＧＢＴ１０の電圧保持部６０に適用された技術は、例えば、図５のＭＯＳＦＥＴ(Metal Oxide Semiconductor Field Effect Transistor)１１にも有用である。ＭＯＳＦＥＴ１１では、ＩＧＢＴ１０のｐ＋型のコレクタ領域７２がｎ＋型のドレイン領域１７２であり、そのドレイン領域１７２がドレイン電極１７４にオーミック接続している。また、ＩＧＢＴ１０のエミッタ領域８６がソース領域１８６であり、そのソース領域１８６がソース電極１８６にオーミック接続している。ＭＯＳＦＥＴ１１でも、４層構造を有することにより、電力損失が低減され、ＥＳＤ耐量が大きく向上する。 The technique applied to the voltage holding unit 60 of the IGBT 10 is also useful for, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 11 shown in FIG. In the MOSFET 11, the p + -type collector region 72 of the IGBT 10 is an n + -type drain region 172, and the drain region 172 is ohmically connected to the drain electrode 174. Further, the emitter region 86 of the IGBT 10 is a source region 186, and the source region 186 is ohmically connected to the source electrode 186. MOSFET 11 also has a four-layer structure, so that power loss is reduced and ESD tolerance is greatly improved.
　さらに、ＩＧＢＴ１０の電圧保持部６０に適用された技術は、例えば、図６のダイオード１３にも有用である。ダイオード１３では、ＩＧＢＴ１０のｐ＋型のコレクタ領域７２がｎ＋型のカソード領域２７２であり、そのカソード領域２７２がカソード電極２７４にオーミック接続している。また、ＩＧＢＴ１０のエミッタ領域８６とボディ領域８８が、コンタクトアノード領域２８８ａとメインアノード領域２８８ｂで構成されるアノード領域２８８であり、そのアノード領域２８８がアノード電極２８７に接続されている。ダイオード１３でも、４層構造を有することにより、電力損失が低減され、ＥＳＤ耐量が大きく向上する。 Furthermore, the technique applied to the voltage holding unit 60 of the IGBT 10 is also useful for the diode 13 in FIG. 6, for example. In the diode 13, the p + -type collector region 72 of the IGBT 10 is an n + -type cathode region 272, and the cathode region 272 is ohmically connected to the cathode electrode 274. The emitter region 86 and the body region 88 of the IGBT 10 are an anode region 288 composed of a contact anode region 288a and a main anode region 288b, and the anode region 288 is connected to the anode electrode 287. Since the diode 13 has a four-layer structure, the power loss is reduced and the ESD tolerance is greatly improved.
　以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
　本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時の請求項に記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数の目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

Claims (7)

  1. 　半導体装置であって、
    　支持基板と埋込み絶縁膜と半導体層が積層した積層基板と、
    　前記半導体層の表面上に設けられている第１主電極と、
    　前記半導体層の表面上に設けられており、前記第１主電極から絶縁されている第２主電極と、
    　前記半導体層内に形成されており、前記第１主電極と前記第２主電極の間に加わる電圧を保持する電圧保持部と、を備えており、
    　前記電圧保持部は、
    　　第１導電型の第１領域と、その第１領域上に設けられている第１導電型の第２領域と、その第２領域上に設けられている第２導電型の第３領域と、その第３領域上に設けられている第１導電型の第４領域を有しており、
    　前記第１領域の不純物濃度は、横方向に沿って変化する半導体装置。     A semiconductor device,
    A laminated substrate in which a supporting substrate, a buried insulating film, and a semiconductor layer are laminated;
    A first main electrode provided on a surface of the semiconductor layer;
    A second main electrode provided on the surface of the semiconductor layer and insulated from the first main electrode;
    A voltage holding unit that is formed in the semiconductor layer and holds a voltage applied between the first main electrode and the second main electrode;
    The voltage holding unit is
    A first conductivity type first region; a first conductivity type second region provided on the first region; a second conductivity type third region provided on the second region; A fourth region of the first conductivity type provided on the third region;
    The semiconductor device in which the impurity concentration of the first region varies along the horizontal direction.
  2. 　前記半導体層内に形成されており、前記第２主電極に接続される第２導電型の第５領域をさらに備えており、
    　前記第３領域と前記第５領域が接している請求項１に記載の半導体装置。     A fifth region of a second conductivity type formed in the semiconductor layer and connected to the second main electrode;
    The semiconductor device according to claim 1, wherein the third region is in contact with the fifth region.
  3. 　前記第１領域の不純物濃度は、前記第５領域から離れる向きに増加する請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the impurity concentration of the first region increases in a direction away from the fifth region.
  4. 　前記第１領域の不純物濃度は、前記第２領域の不純物濃度よりも薄く、
    　前記第４領域の不純物濃度は、前記第１領域の不純物濃度よりも薄い請求項１～３のいずれか一項に記載の半導体装置。     The impurity concentration of the first region is thinner than the impurity concentration of the second region,
    The semiconductor device according to any one of claims 1 to 3, wherein an impurity concentration in the fourth region is lower than an impurity concentration in the first region.
  5. 　前記第４領域の厚みは、前記第１領域と前記第２領域と前記第３領域の合計の厚みよりも厚い請求項１～４のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4, wherein a thickness of the fourth region is larger than a total thickness of the first region, the second region, and the third region.
  6. 　前記第４領域の厚みは、前記第１領域と前記第２領域と前記第３領域の合計の厚みの１．５倍以上である請求項５に記載の半導体装置。 6. The semiconductor device according to claim 5, wherein a thickness of the fourth region is 1.5 times or more of a total thickness of the first region, the second region, and the third region.
  7. 　バイポーラで動作することを特徴とする請求項１～６のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device operates in a bipolar manner.
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JP2001015741A (en) * 1999-06-30 2001-01-19 Toshiba Corp Field effect transistor
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JP2007173422A (en) * 2005-12-21 2007-07-05 Toyota Motor Corp Semiconductor device, and method of manufacturing same
JP2008186921A (en) * 2007-01-29 2008-08-14 Mitsubishi Electric Corp Semiconductor device

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JP2001015741A (en) * 1999-06-30 2001-01-19 Toshiba Corp Field effect transistor
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JP2007173422A (en) * 2005-12-21 2007-07-05 Toyota Motor Corp Semiconductor device, and method of manufacturing same
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