JP3744175B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Silicon carbide semiconductor device and manufacturing method thereof Download PDF

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JP3744175B2
JP3744175B2 JP03112598A JP3112598A JP3744175B2 JP 3744175 B2 JP3744175 B2 JP 3744175B2 JP 03112598 A JP03112598 A JP 03112598A JP 3112598 A JP3112598 A JP 3112598A JP 3744175 B2 JP3744175 B2 JP 3744175B2
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semiconductor layer
semiconductor
silicon carbide
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semiconductor region
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JPH10290010A (en
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有一 竹内
孝昌 鈴木
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【０００１】
【産業上の利用分野】
本発明は炭化珪素半導体装置、たとえば、大電力用縦型絶縁ゲート型電界効果トランジスタに関する。
【０００２】
【従来技術】
近年、電力用トランジスタとして炭化珪素単結晶材料を使用して作製される縦型パワーＭＯＳＦＥＴが提案されている。これは基板表面から半導体基板に溝を形成し、溝側面をチャネル領域とするものである。電力用トランジスタにおいてはゲート電圧がオフ時のソースとドレイン間のリーク電流が少なく、かつ、オン時にはソースとドレイン間の抵抗（以下、オン抵抗という）が小さいことが必要であり、このような要求に対して、六方晶炭化珪素の電子物性の長所を生かし、高電圧印加時のリーク電流の低減とオン抵抗の低減が効果的に図れる電力用トランジスタとして例えば、特開平７−１３１０１６号公報や特開平７−３２６７５５号公報に記載のものが提案されている。
【０００３】
【発明が解決しようとする課題】
しかしながら、特開平７−１３１０１６号公報や特開平７−３２６７５５号公報の溝ゲート型パワーＭＯＳＦＥＴにおいては、必ずしもチャネル移動度が向上するとはいえず、依然としてオン抵抗が高いという問題があった。また、ゲート絶縁膜の寿命においてシリコンＭＯＳＦＥＴに比べて短いという問題があった。
【０００４】
そこで、本発明の目的は、炭化珪素からなる縦型絶縁ゲート型電解効果トランジスタにおいて高信頼性のあるゲート絶縁膜を有するトランジスタ及びその製造方法を提供するものであり、さらにはチャネル移動度を改善しオン抵抗を効果的に低減することのできるトランジスタ及びその製造方法を提供するものである。
【０００５】
【課題を解決するための手段】
請求項１に記載の発明は、縦型絶縁ゲート型電界効果トランジスタの溝の側面にて囲まれるとともにチャネル部となる島状の半導体領域を形成し、その島状半導体領域を囲う溝側面にゲート絶縁膜を形成した炭化珪素半導体装置をその要旨とする。つまり島状半導体領域はゲート絶縁膜により囲われることになる。
【０００６】
そして、請求項１に記載の発明は、島状半導体領域の平面形状を多角形とし、かつ、その多角形のいずれの内角も１８０度未満であることをその要旨とする。また、請求項１あるいは請求項３に記載の発明は、前記多角形の辺、すなわち溝側面が、略［１１−００］方向に平行であり、かつ、ゲート絶縁膜はウエット雰囲気の熱酸化で形成された絶縁膜であることをその要旨とする。
【０００７】
請求項２に記載の発明は、請求項１に記載の発明における多角形が、各内角が略等しい六角形であることをその要旨とする。以下、本願発明者らの実験及びその結果に基づく考察により本願発明をより詳細に説明する。まず、信頼性の高いゲート絶縁膜を得るという課題に対して、カーボン原子を起源とする界面準位密度を低下させることができれば、高信頼性のあるゲート絶縁膜が得られ、ゲート絶縁膜の寿命をものばすことができると考えた。
【０００８】
本発明者らは、炭化珪素単結晶基板から構成される縦型絶縁ゲート型電界効果トランジスタの溝側面の表面形状が三角形、四角形、六角形、円形等のＭＯＳＦＥＴを設計し、その内側に溝を形成したものと、その外側に溝を形成したものを作製、評価した。その結果、外側に溝を形成したものの方が相対的にゲート絶縁膜の寿命も大きいことがわかった。
【０００９】
この理由について図１４及び図１５を用いて説明する。図１４（ａ）、図１５（ａ）は炭化珪素からなる縦型絶縁ゲート型電界効果パワーＭＯＳＦＥＴの平面図であり、表面にはソース領域が形成され、かつその側面にチャネル領域が形成されるｐ型炭化珪素半導体層３（図１５では島状半導体領域１２）と溝７及びゲート絶縁膜８が図示されている。また、図１４（ｂ）、図１５（ｂ）は図１４（ａ）、図１５（ａ）のそれぞれの一部拡大図である。図１４においてはｐ型炭化珪素半導体層３に四角い溝７を形成し、図１５においては溝７を形成することで島状半導体領域１２を形成している。すなわち、図１４に示すものが内側に溝を形成したものに該当し、図１５に示すものが外側に溝を形成したものに該当する。
【００１０】
図１４（ａ）の一部拡大図である図１４（ｂ）に示すように内側に溝を形成したものにおいては、チャネル面とチャネル面が交差する角部Ａの酸化膜内で、ゲート絶縁膜形成時の熱酸化で発生するカーボン原子の拡散が抑えられ、カーボン原子の密度が大きい領域が存在し、チャネル面とチャネル面が交差する角部では、カーボン原子を起源とする界面準位密度が極めて大きくなり、ゆえにゲート絶縁膜の信頼性の低下を引き起こすものと結論した。
【００１１】
一方、図１５（ａ）の一部拡大図である図１５（ｂ）に示すように外側に溝を形成したものにおいては、チャネル面とチャネル面が交差する角部の酸化膜内で、ゲート絶縁膜形成時の熱酸化で発生するカーボン原子の拡散が抑制されることはなく、カーボン原子の密度が特に大きい領域も存在しない。そのため、熱酸化で発生するカーボン原子の集中によるゲート絶縁膜の信頼性の低下は発生しないものと結論した。
【００１２】
尚、内側に溝を形成した場合と、外側に溝を形成した場合とでゲート絶縁膜形成時の熱酸化で発生するカーボン原子の拡散が異なる理由としては、図１４（ｂ）、図１５（ｂ）の矢印にて示す熱酸化の際のカーボン原子が拡散していく経路が図１４（ｂ）の内側に溝を形成したものにおいては特にコーナー部にて密になり、一方、図１５（ｂ）の外側に溝を形成したものにおいてはその経路が密になることがないためと考えられる。すなわち、内側に溝を形成する場合には凹部となる領域が形成され、熱酸化の際にカーボン原子が容易に拡散せず、一方、外側に溝を形成する場合には凹部となる領域が形成されず凸部になっており、熱酸化の際にカーボン原子が容易に拡散するといえる。
【００１３】
以上説明したように、溝を外側に形成することでゲート絶縁膜の信頼性を高めることができる。
また、チャネル移動度が依然として低いという課題に対して、本発明者らはトランジスタの電気特性に及ぼすトランジスタ溝側面の表面形状依存性、チャネル面の結晶面方位依存性、及び、ゲート絶縁膜形成条件依存性について検討、実験した。
【００１４】
主表面を（０００１−）カーボン面とする縦型絶縁ゲート型電界効果トランジスタのチャネル面の面方位すなわち溝側面を５度ずつ変化させたＭＯＳＦＥＴを作製し、チャネル移動度を評価した。その結果、ゲート絶縁膜がウエット雰囲気の熱酸化で形成されたＭＯＳＦＥＴではチャネル移動度は６０度の周期性を示し、チャネル面の面方位が［１１−００］に平行である場合にチャネル移動度は極大を示した。また、界面準位密度を見積もったところ、［１１−００］に平行である場合に極小を示した。図１６に本発明者らの評価から得られた界面準位密度の面方位依存性を示す。ここで、ゲート絶縁膜がドライ雰囲気の熱酸化で形成されたＭＯＳＦＥＴでは、ウエット雰囲気で形成されたＭＯＳＦＥＴよりチャネル移動度は低く、界面準位密度も大きく、強い面方位依存性を示さなかった。
【００１５】
この結果はチャネル移動度低下の要因の１つとして六方晶炭化珪素半導体の結晶構造に起因する界面準位密度が重要であることを示している。
本願発明者らの考察では、炭化珪素半導体にて形成されたＭＯＳＦＥＴの界面準位密度の起源は、単原子より構成されるシリコン半導体の場合とは異なり、チャネル面に存在するカーボン原子が重要な役割を担っており、シリコン半導体から形成されたＭＯＳＦＥＴよりも一桁以上大きな値を示す界面準位密度はカーボン原子に起因するものであるとの結論に達した。その理由は、六方晶炭化珪素において（０００１）シリコン面に比べ（０００１−）カーボン面で界面準位密度が大きいこと、さらに実験で得られた図１６の界面準位密度の分布が、結晶構造から数学的に計算される単位面積当たりのカーボン原子密度とよい相関があったからである。
【００１６】
そこで、チャネル面、及びゲート酸化膜内に存在するカーボン原子の密度を最大限に減少させ、カーボン原子を起源とする界面準位密度を低下させることで炭化珪素にて形成したＭＯＳＦＥＴのチャネル移動度向上を図ることができると考えた。それには、チャネル面を［１１−００］に平行とし、ゲート絶縁膜をウエット雰囲気の熱酸化で形成することが有効であると本発明者らの実験で確認された。また、図１５に示す外側に溝を形成するものにおいても、上述したようにカーボン原子がゲート絶縁膜中に取り残されて密となる領域が存在しないため、カーボン原子に起因する界面準位密度を低下させてチャネル移動度の向上を図ることができると言える。
【００１７】
従って、請求項１あるいは請求項３に記載の発明によれば、縦型絶縁ゲート型電界効果トランジスタの溝の側面にて囲まれ、かつチャネル部となる島状の半導体領域を形成し、つまり、外側に溝を形成して島状半導体領域の溝側面にゲート絶縁膜を形成するようにしているため、熱酸化でゲート絶縁膜を形成する際に、内側に溝を形成する場合に比べ、炭化珪素の酸化で発生したカーボン原子を容易に雰囲気中に拡散することができ、これによってカーボン原子の不拡散による界面準位密度の増大が解消され、チャネル移動度の向上とゲート酸化膜寿命の向上を図ることができる。
【００１８】
そして、請求項１に記載の発明によれば、前記島状半導体領域を多角形としてあるので、容易な平面形状設計が可能となる。加えて、前記多角形のいずれの内角も１８０度未満としてあるので、カーボン原子の不拡散による界面準位密度の増大の解消も可能となる。請求項１あるいは請求項３に記載の発明によれば、前記多角形の辺、すなわち前記溝側面は略［１１−００］方向に平行であるので、炭化珪素結晶構造に基づくカーボン原子密度が最小となる面にＭＯＳ界面を形成することができ、本発明者らの実験結果が示すように、効果的に界面準位密度を低下することができる。
【００１９】
請求項２に記載の発明によれば、請求項１に記載の発明の作用に加え、前記側面の平面形状は、各内角が略等しい六角形としたので、六角形の各辺において内角をなす角度は略１２０度となる。よって、縦型絶縁ゲート型電界効果トランジスタのオフ時にソース・ドレイン間に高電圧が印加された場合に、側面の形状が六角形の溝にて形成された半導体部で電界集中によるアバランシェブレークダウンは発生しにくい。すなわち、請求項１に示すように前記多角形の辺を所定の方向に揃えるためには三角形や菱形もあり得るがこのような形状では鋭角になる部分が生じ電界集中によってアバランシェブレークダウンが生じやすいが、六角形では鋭角になる領域が存在しないためアバランシェブレークダウンが発生しにくい。従って、ソース・ドレイン間耐圧設計においては、高抵抗半導体層と第２導電型の半導体層の不純物濃度及びその膜厚で決まる耐圧を考えればよいので、高耐圧設計が可能となる。
【００２０】
尚、本明細書においては、六方晶系の単結晶炭化珪素の面および方向軸を表す場合、本来ならば図面に記載されているように、所要の数字の上にバーを付した表現をとるべきであるが、表現手段に制約があるために、前記所要の数字の上にバーを付す表現の代わりに、前記所要数字の後に「−」を付して表現している。
【００２１】
【発明の実施の形態】
以下、この発明の実施の形態を図面に従って説明する。
図１に本実施の形態におけるｎチャネルタイプの縦型絶縁ゲート型電界効果トランジスタ（以下、縦型パワーＭＯＳＦＥＴという）を示す。
低抵抗半導体層としてのｎ+ 型炭化珪素半導体基板１は、六方晶炭化珪素が用いられている。このｎ+ 型炭化珪素半導体基板１上に、高抵抗半導体層としてのｎ- 型炭化珪素半導体層２とｐ型炭化珪素半導体層３が順次積層されている。
【００２２】
このように、ｎ+ 型炭化珪素半導体基板１とｎ- 型炭化珪素半導体層２とｐ型炭化珪素半導体層３とから単結晶炭化珪素よりなる半導体基板４が構成されており、その上面を略（０００１−）カーボン面としている。
ｐ型炭化珪素半導体層３内の表層部における所定領域には、半導体領域としてのｎ+ 型ソース領域５が形成されている。さらに、ｐ型炭化珪素半導体層３内の表層部における所定領域には低抵抗ｐ型炭化珪素領域６が形成されている。
【００２３】
又、ｎ+ 型ソース領域５の所定領域に溝７が形成され、この溝７は、ｎ+ 型ソース領域５とｐ型炭化珪素半導体層３を貫通しｎ- 型炭化珪素半導体層２に達している。
溝７は半導体基板４の表面に垂直な側面７ａおよび半導体基板４の表面に平行な底面７ｂを有する。溝７の側面７ａにより囲まれた六角形状の領域（図１では六角形の一部のみ示す）が島状半導体領域１２となる。つまり、島状半導体領域１２はｎ- 型炭化珪素半導体層２上に形成されたｐ型炭化珪素半導体層３とこのｐ型炭化珪素半導体層３に形成されたｎ+ 型ソース領域５及び低抵抗ｐ型炭化珪素領域６を備え、他の島状半導体領域１２から分離されている複数の領域のことを言う。又、本実施形態では溝７の側面７ａは略［１１−００］方向に延設されている。さらに、溝７の側面７ａの平面形状は、各内角が略等しい六角形である。つまり、図２の基板４の平面図において、六角形の６つの辺をＳ１、Ｓ２、Ｓ３、Ｓ４、Ｓ５、Ｓ６で示し、辺Ｓ１とＳ２となす角度（内角）、辺Ｓ２とＳ３となす角度（内角）、辺Ｓ３とＳ４となす角度（内角）、辺Ｓ４とＳ５となす角度（内角）、辺Ｓ５とＳ６となす角度（内角）、辺Ｓ６とＳ１となす角度（内角）は略１２０゜となっている。このように島状半導体領域１２を形成することでその平面形状に凹部となる領域が形成されない。
【００２４】
さらに、溝７内での側面７ａの表面と溝７の底面７ｂにはゲート絶縁膜８が形成されている。溝７内におけるゲート絶縁膜８の内側には、ゲート電極層９が充填されている。ゲート電極層９は絶縁膜１０にて覆われている。ｎ+ 型ソース領域５の表面およびと低抵抗ｐ型炭化珪素領域６の表面には第一の電極層としてのソース電極層１１が形成されている。ｎ+ 型炭化珪素半導体基板１の表面（半導体基板４の裏面）には、第２の電極層としてのドレイン電極層１３が形成されている。
【００２５】
このように縦型パワーＭＯＳＦＥＴは、チャネル形成面が［１１−００］方向に平行となっており、図２に示すように六角形の島状半導体領域１２の外側に溝が配置されている。
次に、縦型パワーＭＯＳＦＥＴの製造工程を、図３〜図８を用いて説明する。
まず、図３に示すように、主表面が略（０００１−）カーボン面であるｎ+ 型炭化珪素半導体基板１を用意し、その表面にｎ- 型炭化珪素半導体層２をエピタキシャル成長し、さらにｎ- 型炭化珪素半導体層２上にｐ型炭化珪素半導体層３をエピタキシャル成長する。このようにして、ｎ+ 型炭化珪素半導体基板１とｎ- 型炭化珪素半導体層２とｐ型炭化珪素半導体層３とからなる半導体基板４が形成される。
【００２６】
次に、図４に示すように、ｐ型炭化珪素半導体層３の表層部の所定領域に、ｎ+ 型ソース領域５を例えば窒素のイオン注入により形成する。さらに、ｐ型炭化珪素半導体層３の表層部の別の所定領域に低抵抗ｐ型炭化珪素領域６を例えばアルミニウムのイオン注入により形成する。
そして、図５に示すようにドライエッチング法、例えばＲＩＥ（Reactive Ionetching)により、ｎ+ 型ソース領域５及びｐ型炭化珪素半導体層３をともに貫通してｎ- 型炭化珪素半導体層２に達する溝７を形成する。この時、溝７の側面７ａが［１１−００］方向に平行となるように溝７を形成し、島状半導体領域１２を形成する。それゆえ、図２に示すように縦型パワーＭＯＳＦＥＴの平面図における島状半導体領域１２の形状が主表面において六角形となる。
【００２７】
引き続き、図６に示すように、半導体基板４および溝７の側面７ａと溝７の底面７ｂにゲート絶縁膜８を形成する。このとき、ゲート絶縁膜８はウエット雰囲気の熱酸化で形成する。このウエット酸化はパイロジェニック法と呼ばれる方法で行い、成膜条件としては上記溝７が形成された半導体基板４を熱酸化炉内に配置し炉内の温度を１１００℃まで上昇させ、水素（Ｈ2 ）と酸素（Ｏ2 ）とを４：３の割合で流入し、水素と酸素とを燃焼させて水蒸気をつくり、水蒸気と酸素と熱酸化膜を形成した。本実施形態では酸化膜の成長速度を２５ｎｍ／ｈとし、１００ｎｍまで成長させた。これに対してドライ酸化は酸素のみを供給して酸化膜を形成する方法である。そして、図７に示すように、溝７内のゲート絶縁膜８の内側に、ゲート電極層９を充填する。さらに、図８に示すように、ゲート電極層９の上面に絶縁膜１０を形成する。その後、図１に示すように、絶縁膜１０上を含むソース領域５と低抵抗ｐ型炭化珪素領域６の上にソース電極層１１を形成する。又、ｎ+ 型炭化珪素半導体基板１の表面に、ドレイン電極層１２を形成して、溝ゲート型パワーＭＯＳＦＥＴを完成する。
【００２８】
以上のように、本実施形態においては溝７の側面７ａにより島状半導体領域１２が囲まれるように、かつ図２に示すように平面図において島状半導体領域１２に凹部が形成されないような形状とし、溝７の側面７ａにゲート絶縁膜８を形成しているため、信頼性の高いゲート絶縁膜８を得ることができる。さらに界面準位密度を低減でき、チャネル移動度を向上させてオン抵抗を低減させることもできる。
【００２９】
また、本実施形態においては縦型ＭＯＳＦＥＴのチャネルを形成する溝７の側面７ａを［１１−００］方向に平行となるように形成し、かつこのような溝７の側面７ａに対してウエット酸化にてゲート絶縁膜８を形成しているため図１６に示すように界面準位を最も低減させることができ、これによってチャネル移動度を向上させることができ、オン抵抗を効果的に低減できるトランジスタを提供できる。
【００３０】
これまで述べた構成の他にも、例えば、ｎ+ 型ソース領域５と低抵抗ｐ型炭化珪素領域６に形成されるソース電極は、異なる材料でもよい。又、低抵抗ｐ型炭化珪素領域６は省略も可能であり、この場合ソース電極層１１はｎ+ 型ソース領域５とｐ型炭化珪素半導体層３に接するように形成される。又、ソース電極層１１は、少なくともｎ+ 型ソース領域５の表面に形成されていればよい。
【００３１】
さらに、上述した例では、ｎチャネル縦型ＭＯＳＦＥＴに適用した場合について説明したが、図１においてｐ型とｎ型を入れ替えた、ｐチャネル縦型ＭＯＳＦＥＴにおいても、同じ効果が得られる。
さらに、図１では、溝７は基板表面に対し側面７ａがほぼ９０゜となっているが、図９に示すように、溝７の側面７ａと基板表面のなす角度は必ずしも９０゜に近くなくてもよい。又、溝７は底面を有しないＶ字型でもよい。さらに図１０に示すように溝７の側面７ａは平面でなくてもよく、滑らかな曲面でもよい。尚、溝７の側面７ａと基板表面のなす角度は、チャネル移動度が大きくなるように設計することにより、より良い効果が得られる。
【００３２】
又、図１１に示すように、ゲート電極９の上部が、ｎ+ 型ソース領域５の上方に延びる形状であってもよい。
又、本実施例では島状半導体領域１２の表面形状を六角形としたが、図１２に示すように滑らかな楕円形や円形であっても、また、図１３に示すように三角形状であっても、外側に溝を形成するようにすれば、本発明の効果が期待できる。
【図面の簡単な説明】
【図１】縦型パワーＭＯＳＦＥＴの斜視図。
【図２】基板の平面図。
【図３】縦型パワーＭＯＳＦＥＴの製造工程を説明する断面図。
【図４】縦型パワーＭＯＳＦＥＴの製造工程を説明する断面図。
【図５】縦型パワーＭＯＳＦＥＴの製造工程を説明する断面図。
【図６】縦型パワーＭＯＳＦＥＴの製造工程を説明する断面図。
【図７】縦型パワーＭＯＳＦＥＴの製造工程を説明する断面図。
【図８】縦型パワーＭＯＳＦＥＴの製造工程を説明する断面図。
【図９】応用例の縦型パワーＭＯＳＦＥＴの断面図。
【図１０】応用例の縦型パワーＭＯＳＦＥＴの断面構造模式図。
【図１１】応用例の縦型パワーＭＯＳＦＥＴの断面構造模式図。
【図１２】応用例を説明する基板の平面図。
【図１３】応用例を説明する基板の平面図。
【図１４】（ａ）は従来の半導体装置を説明する平面図。
（ｂ）は（ａ）の一部拡大図。
【図１５】（ａ）は本発明の半導体装置の概念を説明する平面図。
（ｂ）は（ａ）の一部拡大図。
【図１６】六方晶炭化珪素半導体における界面準位密度の面方位依存性を示す特性図。
【符号の説明】
１ ｎ+ 型炭化珪素半導体基板
２ ｎ- 型炭化珪素半導体層
３ ｐ型炭化珪素半導体層
４ 半導体基板
５ 半ｎ+ 型ソース領域
７ 溝
７ａ 側面
７ｂ 底面
８ ゲート絶縁膜
９ ゲート電極層
１０ 絶縁膜
１１ ソース電極層
１３ ドレイン電極層[0001]
[Industrial application fields]
The present invention relates to a silicon carbide semiconductor device, for example, a vertical insulated gate field effect transistor for high power.
[0002]
[Prior art]
In recent years, a vertical power MOSFET manufactured using a silicon carbide single crystal material as a power transistor has been proposed. In this method, a groove is formed in the semiconductor substrate from the substrate surface, and the groove side surface is used as a channel region. In a power transistor, it is necessary that the leakage current between the source and the drain when the gate voltage is off is small, and that the resistance between the source and the drain (hereinafter referred to as on-resistance) is small when the gate voltage is on. On the other hand, as a power transistor capable of effectively reducing leakage current and reducing on-resistance when a high voltage is applied, taking advantage of the electronic properties of hexagonal silicon carbide, for example, Japanese Patent Laid-Open No. 7-13016 and A thing described in Kaihei 7-326755 is proposed.
[0003]
[Problems to be solved by the invention]
However, the groove gate type power MOSFETs disclosed in Japanese Patent Application Laid-Open Nos. 7-1301616 and 7-326755 do not necessarily improve the channel mobility, and have a problem that the on-resistance is still high. There is also a problem that the lifetime of the gate insulating film is shorter than that of the silicon MOSFET.
[0004]
Therefore, an object of the present invention is to provide a transistor having a highly reliable gate insulating film in a vertical insulated gate field effect transistor made of silicon carbide, and a method for manufacturing the same, and further improve channel mobility. A transistor capable of effectively reducing on-resistance and a method of manufacturing the same are provided.
[0005]
[Means for Solving the Problems]
According to the first aspect of the present invention, an island-shaped semiconductor region which is surrounded by a side surface of a trench of a vertical insulated gate field effect transistor and becomes a channel portion is formed, and a gate is formed on the side surface of the trench surrounding the island-shaped semiconductor region. The gist is a silicon carbide semiconductor device in which an insulating film is formed. That is, the island-shaped semiconductor region is surrounded by the gate insulating film.
[0006]
The gist of the invention described in claim 1 is that the planar shape of the island-like semiconductor region is a polygon, and any interior angle of the polygon is less than 180 degrees. In the invention according to claim 1 or 3 , the side of the polygon, that is, the side surface of the groove is substantially parallel to the [11-00] direction, and the gate insulating film is thermally oxidized in a wet atmosphere. The gist is that the insulating film is formed.
[0007]
According to a second aspect of the invention, a polygon in the invention of claim 1, and its gist that each internal angle is approximately equal hexagonal. Hereinafter, the present invention will be described in more detail based on experiments by the inventors of the present application and consideration based on the results. First, in response to the problem of obtaining a highly reliable gate insulating film, if the interface state density originating from carbon atoms can be reduced, a highly reliable gate insulating film can be obtained. We thought that the life could be extended.
[0008]
The inventors of the present invention designed a MOSFET whose surface shape on the groove side surface of a vertical insulated gate field effect transistor composed of a silicon carbide single crystal substrate is triangular, quadrangular, hexagonal, circular, etc. What was formed and what formed the groove | channel on the outer side were produced and evaluated. As a result, it was found that the gate insulating film having a relatively long groove has a longer lifetime.
[0009]
The reason for this will be described with reference to FIGS. 14 (a) and 15 (a) are plan views of a vertical insulated gate field effect power MOSFET made of silicon carbide. A source region is formed on the surface and a channel region is formed on the side surface thereof. P type silicon carbide semiconductor layer 3 (island semiconductor region 12 in FIG. 15), trench 7 and gate insulating film 8 are shown. FIGS. 14B and 15B are partially enlarged views of FIGS. 14A and 15A. In FIG. 14, a rectangular groove 7 is formed in the p-type silicon carbide semiconductor layer 3, and in FIG. 15, the island-shaped semiconductor region 12 is formed by forming the groove 7. That is, the one shown in FIG. 14 corresponds to the one in which the groove is formed inside, and the one shown in FIG. 15 corresponds to the one in which the groove is formed outside.
[0010]
As shown in FIG. 14B, which is a partially enlarged view of FIG. 14A, in the case where the groove is formed on the inner side, the gate insulation is formed in the oxide film at the corner A where the channel surface and the channel surface intersect. Diffusion of carbon atoms generated by thermal oxidation during film formation is suppressed, there is a region where the density of carbon atoms is large, and the interface state density originating from carbon atoms is present at the corner where the channel surface intersects the channel surface. It was concluded that this would become extremely large, and hence cause a decrease in the reliability of the gate insulating film.
[0011]
On the other hand, in the case where grooves are formed on the outside as shown in FIG. 15B, which is a partially enlarged view of FIG. 15A, the gate is formed within the oxide film at the corner where the channel surface and the channel surface intersect. Diffusion of carbon atoms generated by thermal oxidation during the formation of the insulating film is not suppressed, and there is no region where the density of carbon atoms is particularly high. Therefore, it was concluded that the reliability of the gate insulating film did not deteriorate due to the concentration of carbon atoms generated by thermal oxidation.
[0012]
Incidentally, the reason why the diffusion of carbon atoms generated by thermal oxidation at the time of forming the gate insulating film differs between when the groove is formed on the inner side and when the groove is formed on the outer side is as follows. The path through which carbon atoms diffuse during the thermal oxidation indicated by the arrow b) becomes dense particularly in the corner portion in the case where grooves are formed inside FIG. 14B, while FIG. This is probably because the path is not dense in the case where grooves are formed outside b). That is, when a groove is formed on the inner side, a region that becomes a recess is formed, and carbon atoms do not diffuse easily during thermal oxidation, while when a groove is formed on the outer side, a region that becomes a recess is formed. It is not a convex part, and it can be said that carbon atoms diffuse easily during thermal oxidation.
[0013]
As described above, the reliability of the gate insulating film can be improved by forming the groove on the outside.
In addition, in response to the problem that the channel mobility is still low, the present inventors have determined that the transistor trench side surface shape dependence, the channel plane crystal plane orientation dependence, and the gate insulating film formation conditions on the electrical characteristics of the transistor The dependence was examined and experimented.
[0014]
A MOSFET with the channel surface orientation of the vertical insulated gate field effect transistor having the main surface of the (0001-) carbon surface, that is, the groove side surface changed by 5 degrees was fabricated, and the channel mobility was evaluated. As a result, in the MOSFET in which the gate insulating film is formed by thermal oxidation in a wet atmosphere, the channel mobility exhibits a periodicity of 60 degrees, and the channel mobility is obtained when the plane orientation of the channel plane is parallel to [11-00]. Showed the maximum. Further, when the interface state density was estimated, it was found to be minimal when parallel to [11-00]. FIG. 16 shows the plane orientation dependence of the interface state density obtained from the evaluation of the present inventors. Here, in a MOSFET in which a gate insulating film is formed by thermal oxidation in a dry atmosphere, channel mobility is lower than that of a MOSFET formed in a wet atmosphere, the interface state density is large, and strong plane orientation dependence is not exhibited.
[0015]
This result shows that the interface state density due to the crystal structure of the hexagonal silicon carbide semiconductor is important as one of the causes of the decrease in channel mobility.
In the inventors' consideration, the origin of the interface state density of the MOSFET formed of the silicon carbide semiconductor is different from the case of the silicon semiconductor composed of a single atom, and the carbon atom existing on the channel surface is important. It was concluded that the interface state density, which plays a role and shows a value that is one order of magnitude larger than that of a MOSFET formed from a silicon semiconductor, is attributed to carbon atoms. The reason is that in hexagonal silicon carbide, the interface state density is higher on the (0001-) carbon surface than on the (0001) silicon surface, and the distribution of the interface state density in FIG. This is because there was a good correlation with the carbon atom density per unit area calculated mathematically from
[0016]
Therefore, the channel mobility of MOSFETs made of silicon carbide is reduced by maximally reducing the density of carbon atoms existing in the channel surface and in the gate oxide film and lowering the interface state density originating from the carbon atoms. We thought that improvement could be aimed at. For this purpose, it has been confirmed by experiments of the present inventors that it is effective to make the channel surface parallel to [11-00] and to form the gate insulating film by thermal oxidation in a wet atmosphere. Further, even in the case where the groove is formed on the outer side shown in FIG. 15, there is no dense region where carbon atoms are left behind in the gate insulating film as described above, so the interface state density due to the carbon atoms is reduced. It can be said that the channel mobility can be improved by lowering.
[0017]
Therefore, according to the invention described in claim 1 or claim 3 , the island-shaped semiconductor region which is surrounded by the side surface of the groove of the vertical insulated gate field effect transistor and becomes the channel portion is formed. Since the groove is formed on the outer side and the gate insulating film is formed on the side surface of the island-shaped semiconductor region, when the gate insulating film is formed by thermal oxidation, compared with the case where the groove is formed on the inner side. Carbon atoms generated by silicon oxidation can be easily diffused into the atmosphere, which eliminates the increase in interface state density due to non-diffusion of carbon atoms, and improves channel mobility and gate oxide film lifetime. Can be achieved.
[0018]
Then, according to the invention described in claim 1, since the pre-Symbol island-shaped semiconductor regions are a polygon, it is possible to easily planar shape design. In addition, since any internal angle of the polygon is less than 180 degrees, an increase in interface state density due to non-diffusion of carbon atoms can be eliminated. According to the invention described in claim 1 or claim 3 , since the sides of the polygon, that is, the groove side surfaces are substantially parallel to the [11-00] direction, the carbon atom density based on the silicon carbide crystal structure is minimized. The MOS interface can be formed on the surface to be, and the interface state density can be effectively reduced as the experimental results of the present inventors show.
[0019]
According to the invention described in claim 2 , in addition to the action of the invention described in claim 1 , since the planar shape of the side surface is a hexagon having substantially the same interior angle, an interior angle is formed at each side of the hexagon. The angle is approximately 120 degrees. Therefore, when a high voltage is applied between the source and drain when the vertical insulated gate field effect transistor is turned off, the avalanche breakdown due to electric field concentration in the semiconductor part whose side shape is formed by a hexagonal groove is Hard to occur. That is, as shown in claim 1 , there may be a triangle or a rhombus to align the sides of the polygon in a predetermined direction, but in such a shape, an acute angle portion occurs and an avalanche breakdown is likely to occur due to electric field concentration. However, an avalanche breakdown is unlikely to occur in the hexagon because there is no region having an acute angle. Accordingly, in the design of the withstand voltage between the source and the drain, it is only necessary to consider the withstand voltage determined by the impurity concentration and the film thickness of the high resistance semiconductor layer and the second conductivity type semiconductor layer.
[0020]
In this specification, when expressing the plane and the direction axis of hexagonal single-crystal silicon carbide, it is originally expressed by adding a bar on a required number as shown in the drawing. However, because there are restrictions on the expression means, instead of the expression of adding a bar on the required number, “−” is added after the required number.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an n-channel type vertical insulated gate field effect transistor (hereinafter referred to as a vertical power MOSFET) in this embodiment.
The n + type silicon carbide semiconductor substrate 1 as the low resistance semiconductor layer is made of hexagonal silicon carbide. On this n + type silicon carbide semiconductor substrate 1, an n − type silicon carbide semiconductor layer 2 and a p type silicon carbide semiconductor layer 3 as a high resistance semiconductor layer are sequentially laminated.
[0022]
Thus, the semiconductor substrate 4 made of single crystal silicon carbide is composed of the n + type silicon carbide semiconductor substrate 1, the n − type silicon carbide semiconductor layer 2, and the p type silicon carbide semiconductor layer 3. The (0001-) carbon surface.
An n + type source region 5 as a semiconductor region is formed in a predetermined region in the surface layer portion in p type silicon carbide semiconductor layer 3. Further, a low resistance p-type silicon carbide region 6 is formed in a predetermined region of the surface layer portion in p-type silicon carbide semiconductor layer 3.
[0023]
Groove 7 is formed in a predetermined region of n + type source region 5, and this groove 7 penetrates n + type source region 5 and p type silicon carbide semiconductor layer 3 and reaches n − type silicon carbide semiconductor layer 2. ing.
The groove 7 has a side surface 7 a perpendicular to the surface of the semiconductor substrate 4 and a bottom surface 7 b parallel to the surface of the semiconductor substrate 4. A hexagonal region (only a part of the hexagon is shown in FIG. 1) surrounded by the side surface 7 a of the groove 7 is an island-shaped semiconductor region 12. That is, the island-shaped semiconductor region 12 includes a p-type silicon carbide semiconductor layer 3 formed on the n − -type silicon carbide semiconductor layer 2, an n + -type source region 5 formed on the p-type silicon carbide semiconductor layer 3, and a low resistance. It refers to a plurality of regions provided with p-type silicon carbide region 6 and separated from other island-like semiconductor regions 12. In the present embodiment, the side surface 7a of the groove 7 extends substantially in the [11-00] direction. Furthermore, the planar shape of the side surface 7a of the groove 7 is a hexagonal shape in which the inner angles are substantially equal. That is, in the plan view of the substrate 4 in FIG. 2, the six sides of the hexagon are indicated by S1, S2, S3, S4, S5, S6, the angle (inner angle) between the sides S1 and S2, and the sides S2 and S3. Angle (inner angle), angle between sides S3 and S4 (inner angle), angle between sides S4 and S5 (inner angle), angle between sides S5 and S6 (inner angle), angle between sides S6 and S1 (inner angle) are approximately 120 °. By forming the island-shaped semiconductor region 12 in this way, a region that becomes a recess in the planar shape is not formed.
[0024]
Further, a gate insulating film 8 is formed on the surface of the side surface 7 a and the bottom surface 7 b of the groove 7 in the groove 7. A gate electrode layer 9 is filled inside the gate insulating film 8 in the trench 7. The gate electrode layer 9 is covered with an insulating film 10. A source electrode layer 11 as a first electrode layer is formed on the surface of n + -type source region 5 and the surface of low-resistance p-type silicon carbide region 6. A drain electrode layer 13 as a second electrode layer is formed on the surface of n + type silicon carbide semiconductor substrate 1 (the back surface of semiconductor substrate 4).
[0025]
Thus, in the vertical power MOSFET, the channel forming surface is parallel to the [11-00] direction, and a groove is disposed outside the hexagonal island-shaped semiconductor region 12 as shown in FIG.
Next, a manufacturing process of the vertical power MOSFET will be described with reference to FIGS.
First, as shown in FIG. 3, an n + type silicon carbide semiconductor substrate 1 whose main surface is a substantially (0001−) carbon surface is prepared, and an n − type silicon carbide semiconductor layer 2 is epitaxially grown on the surface, and n - a p-type silicon carbide semiconductor layer 3 is epitaxially grown on the -type silicon carbide semiconductor layer 2. Thus, semiconductor substrate 4 formed of n + type silicon carbide semiconductor substrate 1, n − type silicon carbide semiconductor layer 2 and p type silicon carbide semiconductor layer 3 is formed.
[0026]
Next, as shown in FIG. 4, n + type source region 5 is formed in a predetermined region of the surface layer portion of p type silicon carbide semiconductor layer 3 by ion implantation of nitrogen, for example. Further, low resistance p-type silicon carbide region 6 is formed in another predetermined region of the surface layer portion of p-type silicon carbide semiconductor layer 3 by ion implantation of, for example, aluminum.
Then, a dry etching method as shown in FIG. 5, for example, by RIE (Reactive Ion Etching), through the n + -type source region 5 and p-type silicon carbide semiconductor layer 3 both n - groove reaching the -type silicon carbide semiconductor layer 2 7 is formed. At this time, the groove 7 is formed so that the side surface 7a of the groove 7 is parallel to the [11-00] direction, and the island-shaped semiconductor region 12 is formed. Therefore, as shown in FIG. 2, the shape of the island-shaped semiconductor region 12 in the plan view of the vertical power MOSFET is a hexagonal shape on the main surface.
[0027]
Subsequently, as shown in FIG. 6, a gate insulating film 8 is formed on the semiconductor substrate 4, the side surface 7 a of the groove 7, and the bottom surface 7 b of the groove 7. At this time, the gate insulating film 8 is formed by thermal oxidation in a wet atmosphere. This wet oxidation is performed by a method called a pyrogenic method. As a film forming condition, the semiconductor substrate 4 on which the groove 7 is formed is placed in a thermal oxidation furnace, the temperature in the furnace is increased to 1100 ° C., and hydrogen (H 2 ) and oxygen (O 2 ) were introduced at a ratio of 4: 3, hydrogen and oxygen were burned to produce water vapor, and water vapor, oxygen and a thermal oxide film were formed. In this embodiment, the growth rate of the oxide film is 25 nm / h, and the oxide film is grown to 100 nm. In contrast, dry oxidation is a method of forming an oxide film by supplying only oxygen. Then, as shown in FIG. 7, the gate electrode layer 9 is filled inside the gate insulating film 8 in the trench 7. Further, as shown in FIG. 8, an insulating film 10 is formed on the upper surface of the gate electrode layer 9. Thereafter, as shown in FIG. 1, source electrode layer 11 is formed on source region 5 and low-resistance p-type silicon carbide region 6 including insulating film 10. Further, the drain electrode layer 12 is formed on the surface of the n + type silicon carbide semiconductor substrate 1 to complete the trench gate type power MOSFET.
[0028]
As described above, in this embodiment, the shape is such that the island-shaped semiconductor region 12 is surrounded by the side surface 7a of the groove 7 and no recess is formed in the island-shaped semiconductor region 12 in the plan view as shown in FIG. Since the gate insulating film 8 is formed on the side surface 7a of the trench 7, the gate insulating film 8 with high reliability can be obtained. Further, the interface state density can be reduced, the channel mobility can be improved, and the on-resistance can be reduced.
[0029]
In the present embodiment, the side surface 7a of the groove 7 forming the channel of the vertical MOSFET is formed to be parallel to the [11-00] direction, and wet oxidation is performed on the side surface 7a of the groove 7. Since the gate insulating film 8 is formed in the transistor, the interface state can be most reduced as shown in FIG. 16, thereby improving the channel mobility and effectively reducing the on-resistance. Can provide.
[0030]
In addition to the configurations described so far, for example, the source electrodes formed in the n + -type source region 5 and the low-resistance p-type silicon carbide region 6 may be made of different materials. The low resistance p-type silicon carbide region 6 may be omitted. In this case, the source electrode layer 11 is formed so as to be in contact with the n + -type source region 5 and the p-type silicon carbide semiconductor layer 3. The source electrode layer 11 only needs to be formed on at least the surface of the n + -type source region 5.
[0031]
Furthermore, in the above-described example, the case where the present invention is applied to an n-channel vertical MOSFET has been described. However, the same effect can be obtained in a p-channel vertical MOSFET in which the p-type and the n-type are interchanged in FIG.
Further, in FIG. 1, the side surface 7a of the groove 7 is approximately 90 ° with respect to the substrate surface. However, as shown in FIG. 9, the angle formed between the side surface 7a of the groove 7 and the substrate surface is not necessarily close to 90 °. May be. The groove 7 may be V-shaped without a bottom surface. Furthermore, as shown in FIG. 10, the side surface 7a of the groove 7 may not be a flat surface, but may be a smooth curved surface. The angle formed between the side surface 7a of the groove 7 and the substrate surface can be improved by designing the channel mobility so as to increase.
[0032]
As shown in FIG. 11, the upper portion of the gate electrode 9 may have a shape extending above the n + -type source region 5.
In this embodiment, the surface shape of the island-like semiconductor region 12 is a hexagonal shape, but it may be a smooth ellipse or circle as shown in FIG. 12 or a triangle as shown in FIG. However, the effect of the present invention can be expected if grooves are formed outside.
[Brief description of the drawings]
FIG. 1 is a perspective view of a vertical power MOSFET.
FIG. 2 is a plan view of a substrate.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a vertical power MOSFET.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a vertical power MOSFET.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a vertical power MOSFET.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a vertical power MOSFET.
FIG. 7 is a cross-sectional view illustrating a manufacturing process of a vertical power MOSFET.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of a vertical power MOSFET.
FIG. 9 is a cross-sectional view of a vertical power MOSFET of an application example.
FIG. 10 is a schematic sectional view of a vertical power MOSFET according to an application example.
FIG. 11 is a schematic sectional view of a vertical power MOSFET according to an application example.
FIG. 12 is a plan view of a substrate for explaining an application example.
FIG. 13 is a plan view of a substrate for explaining an application example;
14A is a plan view illustrating a conventional semiconductor device. FIG.
(B) is a partially enlarged view of (a).
FIG. 15A is a plan view illustrating the concept of a semiconductor device of the invention.
(B) is a partially enlarged view of (a).
FIG. 16 is a characteristic diagram showing the plane orientation dependence of the interface state density in a hexagonal silicon carbide semiconductor.
[Explanation of symbols]
1 n + type silicon carbide semiconductor substrate 2 n − type silicon carbide semiconductor layer 3 p type silicon carbide semiconductor layer 4 semiconductor substrate 5 half n + type source region 7 groove 7a side surface 7b bottom surface 8 gate insulating film 9 gate electrode layer 10 insulating film 11 Source electrode layer 13 Drain electrode layer

Claims (3)

第１導電型の低抵抗半導体層と第１導電型の高抵抗半導体層と第２導電型の半導体層とが順次積層され、単結晶炭化珪素よりなる半導体基板と、
前記半導体層の表層部の所定領域に形成された第１導電型の半導体領域と、
前記半導体層の主表面から前記半導体領域と前記半導体層を共に貫通し前記高抵抗半導体層に達して前記半導体領域及び前記半導体層を露出させる側面と前記高抵抗半導体層を露出させる底面とを有する溝と、
前記半導体層及び前記半導体領域とを有し、前記溝の側面に囲まれるように形成された島状半導体領域と、
少なくとも前記島状半導体領域を囲っている前記溝の側面に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極層と、
前記主表面のうち少なくとも前記島状半導体領域における前記半導体領域の表面に形成された第１の電極と、
前記低抵抗半導体層の裏面に形成された第２の電極とを備えた炭化珪素半導体装置であって、
前記島状半導体領域は、その平面形状が多角形であり、かつ、前記多角形のいずれの内角も１８０度未満であるとともに、
前記多角形の辺は、略［１１−００］に平行であり、前記ゲート絶縁膜はウエット雰囲気の熱酸化にて形成された熱酸化膜であることを特徴とする炭化珪素半導体装置。A first conductive type low resistance semiconductor layer, a first conductive type high resistance semiconductor layer, and a second conductive type semiconductor layer are sequentially stacked, and a semiconductor substrate made of single crystal silicon carbide;
A semiconductor region of a first conductivity type formed in a predetermined region of a surface layer portion of the semiconductor layer;
The semiconductor layer has a side surface that penetrates both the semiconductor region and the semiconductor layer from the main surface of the semiconductor layer and reaches the high resistance semiconductor layer to expose the semiconductor region and the semiconductor layer, and a bottom surface that exposes the high resistance semiconductor layer. Groove,
The semiconductor layer and the semiconductor region, an island-shaped semiconductor region formed so as to be surrounded by a side surface of the groove;
A gate insulating film formed on a side surface of the trench surrounding at least the island-shaped semiconductor region;
A gate electrode layer formed on the gate insulating film;
A first electrode formed on a surface of the semiconductor region in at least the island-shaped semiconductor region of the main surface;
A silicon carbide semiconductor device comprising a second electrode formed on the back surface of the low-resistance semiconductor layer ,
The island-shaped semiconductor region has a polygonal planar shape, and any interior angle of the polygon is less than 180 degrees,
The polygonal side is substantially parallel to [11-00], and the gate insulating film is a thermal oxide film formed by thermal oxidation in a wet atmosphere . 前記多角形は、各内角が略等しい六角形である請求項１に記載の炭化珪素半導体装置。The silicon carbide semiconductor device according to claim 1 , wherein each of the polygons is a hexagon having substantially equal inner angles. 第１導電型の低抵抗半導体層と第１導電型の高抵抗半導体層と第２導電型の半導体層とを順次積層し、単結晶炭化珪素よりなる半導体基板を用意する第１工程と、
前記半導体層の表層部の所定領域に第１導電型の半導体領域を形成する第２工程と、
前記半導体層の主表面から前記半導体領域と前記半導体層を共に貫通し前記高抵抗半導体層に達して前記半導体領域及び前記半導体層を露出させる側面と前記高抵抗半導体層を露出させる底面とを有する溝を形成し、前記半導体層及び前記半導体領域とを有して前記溝の側面に囲まれる島状半導体領域を形成する第３工程と、
少なくとも前記島状半導体領域を囲っている前記溝の側面にゲート絶縁膜を形成する第４工程と、
前記ゲート絶縁膜上にゲート電極層を形成する第５工程と、
前記主表面のうち少なくとも前記島状半導体領域における前記半導体領域の表面に第１の電極を形成し、前記低抵抗半導体層の裏面に第２の電極を形成する第６工程とを備えた炭化珪素半導体装置の製造方法であって、
前記第３工程において、前記溝の側面は略［１１−００］方向に平行に形成され、かつ前記第４工程において、前記ゲート絶縁膜はウエット雰囲気の熱酸化にて形成されるものであることを特徴とする炭化珪素半導体装置の製造方法。 A first step of sequentially stacking a first conductivity type low-resistance semiconductor layer, a first conductivity type high-resistance semiconductor layer, and a second conductivity type semiconductor layer to prepare a semiconductor substrate made of single-crystal silicon carbide;
A second step of forming a first conductivity type semiconductor region in a predetermined region of the surface layer portion of the semiconductor layer;
The semiconductor layer has a side surface that penetrates both the semiconductor region and the semiconductor layer from the main surface of the semiconductor layer and reaches the high resistance semiconductor layer to expose the semiconductor region and the semiconductor layer, and a bottom surface that exposes the high resistance semiconductor layer. A third step of forming a groove and forming an island-shaped semiconductor region having the semiconductor layer and the semiconductor region and surrounded by a side surface of the groove;
A fourth step of forming a gate insulating film on a side surface of the trench surrounding at least the island-shaped semiconductor region;
A fifth step of forming a gate electrode layer on the gate insulating film;
A silicon carbide comprising: a sixth step of forming a first electrode on the surface of the semiconductor region in at least the island-shaped semiconductor region of the main surface and forming a second electrode on the back surface of the low-resistance semiconductor layer A method for manufacturing a semiconductor device, comprising:
In the third step, the side surface of the groove is formed substantially parallel to the [11-00] direction, and in the fourth step, the gate insulating film is formed by thermal oxidation in a wet atmosphere. A method for manufacturing a silicon carbide semiconductor device , comprising:
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