JPH10229190A - Silicon carbide semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device and manufacture thereof which improves channel mobility to effectively reduce the on-resistance. SOLUTION: This device comprises an n<+> and n<-> -type Si carbide semiconductor or layers 1, 2 and p-type semiconductor layer 3, and its main surface is a (0001-) carbon plane and is composed of a hexagonal single-crystal silicon carbide. On the surface of the semiconductor layer 3, n<+> -type source regions 5 are formed with trenches 7 passing from the main surface to the semiconductor layer 2 through the regions 5 and layer 3 and side faces thereof, formed parallel to the (11-00) plane. A gate-insulating film is formed by wet thermal oxidation. This improves the channel mobility and reduces the on-resistance of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a silicon carbide semiconductor device, for example, a high power vertical insulated gate field effect transistor.

[0002]

2. Description of the Related Art Recently, a vertical power MOSF manufactured using a silicon carbide single crystal material as a power transistor has been developed.
ET has been proposed. In this method, a groove is formed in a semiconductor substrate from the substrate surface, and the side surface of the groove is used as a channel region. In a power transistor, it is necessary that the leak current between the source and the drain when the gate voltage is off is small and the resistance between the source and the drain when the gate voltage is on (hereinafter referred to as on-resistance) is small. On the other hand, as a power transistor which can effectively reduce the leak current and the on-resistance when a high voltage is applied, taking advantage of the electronic properties of hexagonal silicon carbide, for example, Japanese Unexamined Patent Publication No.
JP-A-131016 and JP-A-7-326755 have been proposed.

[0003]

However, in the trench gate type power MOSFETs disclosed in JP-A-7-131016 and JP-A-7-326755, the channel mobility is not necessarily improved, and the on-resistance still remains. There was a problem of high. Therefore, an object of the present invention is to provide a transistor capable of improving channel mobility and effectively reducing on-resistance, and a method for manufacturing the same.

[0004]

According to a first aspect of the present invention, there is provided a semiconductor substrate comprising a vertical insulated gate field effect transistor groove gate channel surface, that is, a hexagonal single crystal silicon carbide. A side surface of a groove formed therein from a main surface of the semiconductor device is substantially in the [11-00] direction, and a gate insulating film provided on the side surface of the groove is formed by thermal oxidation in a wet atmosphere. And its manufacturing method as its gist.

According to a second aspect of the present invention, there is provided a silicon carbide semiconductor device according to the first aspect, wherein the planar shape of the groove side surface is a hexagon having substantially the same interior angle.
Hereinafter, the present invention will be described in more detail based on experiments performed by the present inventors and considerations based on the results. In order to solve the problem that the channel mobility is still low, the present inventors discuss the dependence of the transistor shape on the surface shape of the side surface of the transistor groove, the crystal plane orientation of the channel surface, and the dependence of the gate insulating film formation conditions on the electrical characteristics of the transistor. We examined and experimented.

A MOSFT in which the plane orientation of the channel plane, that is, the groove side surface of the vertical insulated gate field effect transistor whose main surface is a (0001-) carbon plane is changed by 5 degrees.
ET was prepared and the channel mobility was evaluated. as a result,
The gate insulating film is formed by thermal oxidation in a wet atmosphere.
In the OSFET, the channel mobility showed a periodicity of 60 degrees, and the channel mobility showed a maximum when the plane orientation of the channel plane was parallel to [11-00]. In addition, when the interface state density was estimated, it was found to be minimal when it was parallel to [11-00]. FIG. 14 shows the plane orientation dependence of the interface state density obtained from the evaluation of the present inventors. Here, a MOS in which a gate insulating film is formed by thermal oxidation in a dry atmosphere
For FET, MOSFET formed in wet atmosphere
The channel mobility was lower, the interface state density was higher, and no strong plane orientation dependence was exhibited.

This result is one of the causes of the decrease in channel mobility.
First, the interface state density resulting from the crystal structure of the hexagonal silicon carbide semiconductor is important. The present inventors consider that MOSF formed of a silicon carbide semiconductor
The origin of the interface state density of ET is different from the case of a silicon semiconductor composed of a single atom, in which carbon atoms existing on the channel surface play an important role, and are one more than those of a MOSFET formed from a silicon semiconductor. It was concluded that the interface state density, which is greater than an order of magnitude, was attributed to carbon atoms. The reason is that hexagonal silicon carbide has a higher interface state density on the (0001-) carbon plane than on the (0001) silicon plane, and the distribution of the interface state density in FIG. This is because there was a good correlation with the carbon atom density per unit area calculated mathematically from

Therefore, the density of carbon atoms existing in the channel surface and in the gate oxide film is reduced to the maximum, and the interface state density originating from carbon atoms is reduced to reduce the density of the MOSFET formed of silicon carbide. We thought that channel mobility could be improved. It has been confirmed by experiments of the present inventors that it is effective to make the channel surface parallel to [11-00] and to form the gate insulating film by thermal oxidation in a wet atmosphere.

Therefore, according to the first or third aspect of the present invention, since the channel surface of the vertical insulated gate field effect transistor is substantially parallel to [11-00], the silicon carbide crystal structure Since the channel interface of the MOSFET can be formed on the surface where the carbon atom density is minimized, and the gate insulating film is an insulating film formed by thermal oxidation in a wet atmosphere, As shown by the experimental results, the interface state density can be effectively reduced. If the interface state density derived from carbon atoms can be reduced, a highly reliable gate insulating film can be obtained, and the life of the gate insulating film can be extended.

According to the second aspect of the present invention, the first aspect is provided.
In addition to the effect of the invention described in (1), since the planar shape of the side surface is a hexagon having substantially the same interior angle, the angle forming the interior angle on each side of the hexagon is approximately 120 degrees. Therefore, when a high voltage is applied between the source and the drain when the vertical insulated gate field effect transistor is turned off, avalanche breakdown due to electric field concentration occurs in the semiconductor portion formed by the hexagonal groove on the side surface. Does not occur. That is, a triangle or a rhombus may be used to align the sides of the polygon in a predetermined direction as described in claim 3. However, in such a shape, an acute angle portion is generated, and avalanche breakdown easily occurs due to electric field concentration. However, in the case of a hexagon, no avalanche breakdown occurs because there is no acute angle region. Therefore, in the source-drain breakdown voltage design, the breakdown voltage determined by the impurity concentration and the film thickness of the high-resistance semiconductor layer and the first semiconductor layer may be considered, so that a high breakdown voltage design is possible.

In this specification, when the plane and the direction axis of the hexagonal single-crystal silicon carbide are expressed, a bar is added to a required numeral as originally described in the drawings. Although the expression should be taken, due to the restriction of the expression means, instead of the expression in which a bar is added above the required number, the required number is represented by adding "-" after the required number.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an n-channel type vertical insulated gate field effect transistor (hereinafter referred to as a vertical power MOSFET) in this embodiment. Hexagonal silicon carbide (SiC) is used for n ⁺ -type silicon carbide semiconductor substrate 1 as a low-resistance semiconductor layer. On this n ⁺ type silicon carbide semiconductor substrate 1, n as a high resistance semiconductor layer
^- type silicon carbide semiconductor layer 2 and the p-type silicon carbide semiconductor layer 3 are sequentially laminated.

Thus, n ⁺ type silicon carbide semiconductor substrate 1
And n ⁻ -type silicon carbide semiconductor layer 2 and first p-type silicon carbide semiconductor layer 3 constitute a semiconductor substrate 4 made of single-crystal silicon carbide, and its upper surface is substantially a (0001-) carbon surface. An n ⁺ -type source region 5 as a semiconductor region is formed in a predetermined region in a surface portion in p-type silicon carbide semiconductor layer 3. Further, p-type silicon carbide semiconductor layer 3
A low-resistance p-type silicon carbide region 6 is formed in a predetermined region in a surface layer portion.

A groove 7 is formed in a predetermined region of the n ⁺ type source region 5.
This trench 7 penetrates n ⁺ type source region 5 and p type silicon carbide semiconductor layer 3 to reach n − type silicon carbide semiconductor layer 2. The groove 7 is a side surface 7 perpendicular to the surface of the semiconductor substrate 4.
a and a bottom surface 7 b parallel to the surface of the semiconductor substrate 4. The side surface 7a of the groove 7 extends substantially in the [11-00] direction. Further, the planar shape of the side surface 7a of the groove 7 is a hexagon whose interior angles are substantially equal. That is, in the plan view of the substrate 4 of FIG. 2, the six sides of the hexagon are represented by S1, S2, S
3, S4, S5, S6, the angle between the sides S1 and S2 (interior angle), the angle between the sides S2 and S3 (interior angle), the angle between the sides S3 and S4 (inner angle), the angle between the sides S4 and S5 (Inner angle), angle between sides S5 and S6 (inner angle), sides S6 and S1
(Inner angle) is approximately 120 °.

Further, the side surface 7a in the groove 7 and the bottom surface 7 of the groove 7
The gate insulating film 8 is formed on b. The inside of the gate insulating film 8 in the trench 7 is filled with a gate electrode layer 9. Gate electrode layer 9 is covered with insulating film 10. A source electrode layer 11 as a first electrode layer is formed on the surface of n ⁺ type source region 5 and the surface of low-resistance p-type silicon carbide region 6. n ⁺ -type silicon carbide semiconductor substrate 1
A drain electrode layer 12 as a second electrode layer is formed on the front surface (back surface of the semiconductor substrate 4).

As described above, the trench gate type power MOSFET
Indicates that the channel forming surface is in the [11-00] direction.
You. Next, the manufacturing process of the trench gate type power MOSFET
Will be described with reference to FIGS. First, shown in FIG.
Thus, n whose main surface is a substantially (0001-) carbon surface
⁺Type silicon carbide semiconductor substrate 1 is prepared and n^-Type
A silicon carbide semiconductor layer 2 is epitaxially grown, and n
^-P-type silicon carbide semiconductor layer 3 on p-type silicon carbide semiconductor layer 2
It grows epitaxially. Thus, n⁺Type carbonization
Silicon semiconductor substrate 1 and n ^--Type silicon carbide semiconductor layer 2 and p-type carbon
A semiconductor substrate 4 composed of a silicon nitride semiconductor layer 3 is formed.
You.

Next, as shown in FIG.
In a predetermined region of the surface portion of the conductor layer 3, n ⁺Mold source region 5
For example, it is formed by ion implantation of nitrogen. Furthermore, p-type
Low resistance p is applied to another predetermined region of the surface layer portion of silicon carbide semiconductor layer 3.
Type silicon carbide region 6 for ion implantation of aluminum, for example.
Formed. Then, as shown in FIG.
RIE (Reactive Ionetching)
n⁺Source region 5 and p-type silicon carbide semiconductor layer 3
Through n^-Groove 7 reaching type silicon carbide semiconductor layer 2 is formed.
To achieve. At this time, the side surface 7a of the groove 7 is oriented in the [11-00] direction.
The groove 7 is formed so as to be parallel to. Therefore, in FIG.
As shown from the top, the shape of the groove is hexagonal on the main surface
It takes shape.

Subsequently, as shown in FIG. 6, a gate insulating film 8 is formed on the surfaces of the semiconductor substrate 4 and the n-type silicon carbide semiconductor thin film layer 7 and the bottom surface 7b of the groove 7. At this time, the gate insulating film 8 is formed by thermal oxidation in a wet atmosphere. This wet oxidation is performed by a method called a pyrogenic method. As a film forming condition, the semiconductor substrate 4 on which the groove 7 is formed is placed in a thermal oxidation furnace, the temperature in the furnace is increased to 1100 ° C., and hydrogen (H ₂ ) and oxygen (O ₂ ) flow at a ratio of 4: 3 and burn hydrogen and oxygen to produce steam,
A thermal oxide film was formed with water vapor and oxygen. In this embodiment, the growth rate of the oxide film is 25 nm / h, and the oxide film is grown up to 100 nm. On the other hand, dry oxidation is a method of forming an oxide film by supplying only oxygen.

Then, as shown in FIG. 7, the inside of the gate insulating film 8 in the trench 7 is filled with, for example, polycrystalline silicon as an electrode material for forming the gate electrode layer 9. Further, as shown in FIG. 8, an insulating film 10 is formed on the upper surface of the gate electrode layer 9 by a vapor deposition method (for example, Chemical Vapor Deposition). Thereafter, as shown in FIG. 1, source region 5 including on insulating film 10 and low-resistance p-type silicon carbide region 6 are formed.
A source electrode layer 1 made of, for example, nickel (Ni)
Form one. Further, a drain electrode layer 12 made of, for example, nickel is formed on the surface of the n ⁺ type silicon carbide semiconductor substrate 1 to complete a trench gate type power MOSFET.

As described above, in this embodiment, the side surface 7a of the groove 7 forming the channel of the vertical MOSFET is formed so as to be parallel to the [11-00] direction, and the side surface of such a groove 7 is formed. Since the gate insulating film 8 is formed by wet oxidation with respect to 7a, the interface state can be reduced most as shown in FIG. 14, whereby the channel mobility can be improved and the on-resistance can be reduced. A transistor that can be effectively reduced can be provided.

In addition to the configuration described above, for example, n
^The source electrode formed on ⁺ type source region 5 and low resistance p-type silicon carbide layer 5 may be made of different materials. The low-resistance p-type silicon carbide layer 5 can be omitted. In this case, the source electrode layer 11 is formed so as to be in contact with the n ⁺ -type source region 5 and the first p-type silicon carbide semiconductor layer 3. Also, the source electrode layer 1
1 may be formed at least on the surface of the n ⁺ type source region 5.

Further, in the above example, the n-channel vertical type M
The case where the present invention is applied to an OSFET has been described. However, in FIG.
The same effect can be obtained in the FET. Further, in FIG. 1, the side surface 7a of the groove 7 is substantially 90 ° with respect to the substrate surface, but as shown in FIG. 9, the angle between the side surface 7a of the groove 7 and the substrate surface is not necessarily close to 90 °. Is also good. or,
The groove 7 may be V-shaped without a bottom surface. Further, as shown in FIG. 10, the side surface 7a of the groove 7 may not be a flat surface, but may be a smooth curved surface. A better effect can be obtained by designing the angle between the side surface 7a of the groove 7 and the substrate surface so as to increase the channel mobility.

Further, as shown in FIG. 11, the upper portion of gate electrode 9 may have a shape extending above n ⁺ type source region 5. Further, as shown in FIG. 12, the planar shape of the side surface of the groove 15 (specifically, the shape on the gate electrode layer 10 side) is
It may be a hexagon whose inner angles are substantially equal. That is, FIG.
In the plan view of the substrate 4 of FIG.
1, S12, S13, S14, S15, S16,
Angle (inner angle) between sides S11 and S12, sides S12 and S1
3, the angle between the sides S13 and S14 (the interior angle), the angle between the sides S14 and S15 (the interior angle), the side S
An angle (inner angle) between 15 and S16 and an angle (inner angle) between sides S16 and S11 are approximately 120 degrees.

[Brief description of the drawings]

FIG. 1 is a trench gate type power MOSFET according to a first embodiment.
FIG.

FIG. 2 is a plan view of a substrate.

FIG. 3 is a sectional view showing a manufacturing process of the trench gate type power MOSFET.

FIG. 4 is a sectional view showing a manufacturing process of the trench gate type power MOSFET.

FIG. 5 is a sectional view showing a manufacturing process of the trench gate type power MOSFET.

FIG. 6 is a sectional view showing the manufacturing process of the trench gate type power MOSFET.

FIG. 7 is a sectional view showing the manufacturing process of the trench gate type power MOSFET.

FIG. 8 is a sectional view showing the manufacturing process of the trench gate type power MOSFET.

FIG. 9 is a schematic sectional view of a trench gate type power MOSFET of an application example.

FIG. 10 is a schematic sectional view of a trench gate type power MOSFET of an application example.

FIG. 11 is a schematic sectional view of a trench gate type power MOSFET of an application example.

FIG. 12 is a plan view of a substrate for describing an application example.

FIG. 13 is a plan view of a substrate for describing an application example.

FIG. 14 is a characteristic diagram showing a plane orientation dependency of an interface state density in a hexagonal silicon carbide semiconductor.

[Explanation of symbols]

Reference Signs List 1 n ⁺ -type silicon carbide semiconductor substrate 2 n ^-- type silicon carbide semiconductor layer 3 p-type silicon carbide semiconductor layer 4 semiconductor substrate 5 n ⁺ -type source region 7 groove 7 a side surface 7 b bottom surface 8 gate insulating film 9 gate electrode layer 10 insulating film 11 Source electrode layer 12 Drain electrode layer

Claims (3)

[Claims] 1. A semiconductor substrate made of hexagonal single-crystal silicon carbide in which a low-resistance semiconductor layer of a first conductivity type, a high-resistance semiconductor layer of a first conductivity type, and a semiconductor layer of a second conductivity type are sequentially stacked. A first conductivity type semiconductor region formed in a predetermined region of a surface layer portion of the semiconductor layer; and a semiconductor layer and a semiconductor layer penetrating from the main surface of the semiconductor substrate to the high resistance semiconductor layer. A groove having a side surface that is substantially parallel to the [11-00] direction; and a groove formed at least on the surface of the side surface of the groove.
A gate insulating film formed by thermal oxidation in a wet atmosphere; a gate electrode layer formed on the gate insulating film; a first electrode formed on at least a surface of the semiconductor region; A silicon carbide semiconductor device, comprising: a second electrode formed on a back surface. 2. The silicon carbide semiconductor device according to claim 1, wherein the planar shape of the side surface of the groove is a hexagon whose interior angles are substantially equal. 3. A semiconductor substrate made of hexagonal single-crystal silicon carbide by sequentially laminating a first-conductivity-type low-resistance semiconductor layer, a first-conductivity-type high-resistance semiconductor layer, and a second-conductivity-type semiconductor layer. A second step of forming a first conductivity type semiconductor region in a predetermined region of a surface portion of the semiconductor layer; and a step of penetrating the semiconductor region and the semiconductor layer from a main surface of the semiconductor substrate. Forming a groove reaching the high-resistance semiconductor layer and having a side surface substantially parallel to the [11-00] direction; and thermally oxidizing at least a surface of the side surface of the groove in a wet atmosphere. A fourth step of forming a gate oxide film on the gate insulating film, a fifth step of forming a gate electrode layer on the gate insulating film, and forming a first electrode on at least a surface of the semiconductor region and the low-resistance semiconductor layer. The second electrode on the back of The method of manufacturing a silicon carbide semiconductor device characterized by comprising a sixth step of forming.