JP2000124308A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that has a wiring structure for preventing burnout between wiring and the increase in resistance, even if a wiring layer is formed at a position that is deviated from a connection hole. SOLUTION: A semiconductor device is provided with a first insulation layer 6, that is formed on a semiconductor substrate 1 and has a connection hole 7 reaching the surface of the semiconductor substrate 1, an embedded conductive layer 8 that is embedded into the connection hole 7, a wiring layer 12 that is formed on the interlayer insulation layer 6 and the embedded conductive layer 8, an insulator layer 16 that is formed on the surface of the wiring layer 12, and a second insulation layer that is formed on the insulator layer 16 and the first insulation layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a wiring structure in a semiconductor integrated circuit and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, elements have been miniaturized as semiconductor integrated circuits have become more highly integrated. As a result, a wiring structure for interconnecting elements has been miniaturized at the same time, and the size of the wiring width and the diameter of the connection hole have been reduced to about the same level. For example, in a 256M DRAM, both the wiring width and the connection hole diameter are 0.3 μm, and strict alignment accuracy is required. Therefore, there is a problem of poor connection due to misalignment between the wiring and the connection hole.

FIG. 12 is a sectional view showing a part of a semiconductor device having a conventional wiring structure. In the figure, 1 is a semiconductor substrate, 2 is an isolation insulating film for separating and insulating each element region formed on the main surface of the semiconductor substrate 1, and 3 is a gate insulating film formed in the element region on the semiconductor substrate 1. 4, a gate electrode formed with the gate insulating film 3 interposed therebetween; 5, an impurity diffusion layer formed on the main surface of the semiconductor substrate 1 so as to sandwich the gate electrode; 6, an interlayer insulating film; A contact hole reaching the surface of the impurity diffusion layer 5; a buried conductive layer 8 made of tungsten embedded in the contact hole; 9 a side surface and a bottom surface of the connection hole 7 or a surface of the interlayer insulating film 9; The barrier layer formed of a composite film of a titanium compound and titanium is formed, 10 is an aluminum wiring layer formed of an aluminum or aluminum alloy film formed on the buried conductive layer 8 and the barrier layer 9, and 11 is aluminum. An upper metal film made of titanium or a titanium compound formed on the wiring layer 10, a wiring layer 12 composed of the barrier layer 9, the aluminum wiring layer 10 and the upper metal film 11, a gate insulating film 3, and a gate electrode 30 A transistor composed of 4 and the impurity diffusion layer 5, and 70 is an interlayer insulating film formed on the wiring layer 12.

In the wiring structure configured as described above, the wiring layer 12 and the impurity diffusion layer 5 formed on the main surface of the semiconductor substrate 1 form the connection hole 7 in which the buried conductive layer 8 is buried. Electrically connected via the This wiring structure
Generally called plug wiring, by embedding the buried conductive layer 8 in the connection hole 7, the aspect ratio of the connection hole 7 can be reduced and the coverage of the wiring layer 12 can be improved, so that a wiring structure suitable for miniaturization. In recent years, it has been widely used.

Next, a method for manufacturing a semiconductor device having the conventional wiring structure will be described. 13 (a) to 13 (d) and FIGS. 14 (e) to 14 (g) are partial process sectional views showing only the wiring structure portion 200 of the semiconductor device shown in FIG. 12 in an enlarged manner. It is assumed that the isolation insulating film 2 and the transistor 30 have already been formed by a well-known manufacturing method, and the steps of forming these are omitted.

First, referring to FIG. 13A, an interlayer insulating film 6 having a connection hole 7 reaching the surface of the semiconductor substrate 1 is formed on the semiconductor substrate 1. Next, referring to FIG. 13B, in order to secure a sufficient contact between the wiring layer and the semiconductor substrate in the connection hole 7, a titanium alloy and a titanium alloy are formed on the inner wall of the connection hole 7 and the interlayer insulating film 6. A barrier layer 9 composed of a multilayer film is formed. Next, referring to FIG. 13C, a buried conductive layer 8 made of tungsten is formed on the barrier layer 9 so as to be buried in the connection hole 7, and then the whole surface is etched back. To form a buried conductive layer 8 in which tungsten is buried only in the connection hole 7.

Referring to FIG. 13D, an aluminum wiring layer 10 made of aluminum or an aluminum alloy film and an upper metal layer made of titanium or a titanium compound are formed on the buried conductive layer 8 and the barrier layer 9. Layer 1
1 are sequentially formed, and the wiring layer 12 is formed together with the barrier layer 9. Next, referring to FIG.
The wiring layer 12 is etched using the dry etching technique using the resist film 13 formed thereon using the photolithography technique as a mask, thereby forming the wiring layer 12 and the impurity diffusion layer 5 formed on the main surface of the semiconductor substrate 1. Are patterned so as to be electrically connected via the connection hole 7 in which the buried conductive layer 8 is buried.

Next, referring to FIG. 14F, the resist film 13 remaining after the etching is removed by a plasma treatment (ashing treatment) of a gas containing oxygen. However, since the resist film 13 is altered and hardened by the previous etching process, it cannot be sufficiently removed only by such an ashing process, and remains as a resist residue 15 on the surface or side surface of the wiring layer 12. Sometimes.

Therefore, usually, in order to remove the resist residue 15, a semiconductor substrate is immersed in a cleaning solution containing a strong alkaline organic solvent or the like. Note that, in the ashing process, overashing of about 50% to 100% is usually performed with respect to the maximum thickness of the remaining resist film 13 in order to enhance removability. Therefore, after the resist film 13 is removed, the surface of the wiring layer 12 is exposed to plasma for a certain period of time. As a result, an oxide layer 14 formed by oxidizing the upper metal layer 11 together with the resist residue 15 by oxygen gas plasma is formed on the surface. Is formed.

Finally, referring to FIG. 14 (g), the wiring layer 12 and the wiring layer formed thereon are insulated on the wiring layer 12, or the wiring layer 12 is protected from the outside air. Insulating film 70 is formed. As described above, a semiconductor device having a conventional wiring structure is formed.

[0011]

Since the conventional wiring structure in a semiconductor device is constructed as described above, FIG.
In the step of patterning the wiring layer 12 shown in FIG. 4E, the wiring layer 12 is displaced from the connection hole 7 as shown in FIG. When the semiconductor substrate is immersed in a cleaning solution in order to remove the resist residue 15, when the buried conductive layer 8 is dissolved or disappears as shown in FIG. However, there is a problem that a connection failure such as disconnection or resistance rise occurs.

The dissolution of the buried conductive layer is considered to occur for the following reasons. Referring again to FIGS. 14E and 14F, in the step of removing resist film 13, the surface of wiring layer 12 is exposed to oxygen gas plasma for a certain time during overashing as described above. The surface is oxidized to form an oxide layer 14 made of a metal oxide of the upper metal film 11. At the same time, the oxygen radicals generated in the oxygen gas plasma have high reactivity and high electronegativity, so that they take electrons from the surface of the wiring layer 12 and charge the wiring layer 12 positively. Accordingly, the potential of the buried conductive layer 8 in contact with the wiring layer 12 increases.

On the other hand, a strong alkaline cleaning solution for removing the resist residue has a high dissolving power of the resist and removes the resist residue efficiently. In addition, for a single metal such as tungsten, the etching property is usually weak,
Simply immersion in the cleaning solution hardly etches. However, when the pH of the cleaning solution is high and the oxidation-reduction potential is high, tungsten has a property of dissolving in a solution. Therefore, when the potential of tungsten is in a high state, the tungsten metal is electrochemically actuated. But it dissolves easily.

Therefore, as shown in FIG. 15, the wiring layer 12 is shifted from the connection hole 7 and a part of the surface of the
When the semiconductor substrate is immersed in a cleaning solution for removing resist residues while the semiconductor substrate 7 is exposed, the oxidation-reduction potential of the buried conductive layer 8 in the cleaning solution is increased due to charging of the wiring layer 12. As shown in FIG. 16, the embedded conductive layer 8 is acceleratedly dissolved or disappears from a part 17 of the surface of the embedded conductive layer 8 by the electrochemical action.

The electric charge accumulated in the wiring layer is normally spontaneously discharged in the cleaning solution. However, the surface or side surfaces of the wiring layer are formed on the surface or side surfaces of the oxide layer 14 formed during the ashing process or the deposition film during etching. Insulators are attached, and these insulators prevent accumulated electric charges from being discharged into the cleaning solution, and keep the potential of the buried conductive layer 8 high at all times during immersion in the cleaning solution. ing. Although an alkaline organic solvent is used as the cleaning solution, it has been confirmed that the embedded conductive layer can be dissolved by a neutral or weakly acidic organic solvent or an inorganic cleaning solution.

Further, since a wiring layer usually has a high reflectance, when a resist film is formed thereon by photolithography, the resist film is deteriorated, and a desired wiring layer cannot be obtained. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. A first object is to displace a wiring layer from a connection hole and expose a part of the surface of a buried conductive layer. An object of the present invention is to provide a semiconductor device having a wiring structure in which the wiring is not broken or the resistance does not increase even if the wiring is formed in a proper state.

A second object is to provide a highly reliable wiring structure which can prevent the charging of the wiring layer, does not dissolve or disappear the buried conductive layer due to the treatment of the cleaning liquid, and does not deteriorate the wiring layer. And a semiconductor device having the same.

A third object of the present invention is to provide a method of manufacturing a semiconductor device having a highly reliable wiring structure which can prevent charging of a wiring layer and does not dissolve or disappear the buried conductive layer due to treatment with a cleaning solution. What you get.

A fourth object of the present invention is to manufacture a semiconductor device having a highly reliable wiring structure which can eliminate the charge of the charged wiring layer and does not dissolve or disappear the buried conductive layer due to the treatment of the cleaning liquid. Get the way.

[0021]

In a semiconductor device according to the present invention, a first insulating layer having a connection hole formed on a semiconductor substrate, a buried conductive layer embedded in the connection hole, and a first insulating layer are provided. A wiring layer formed on the insulating layer and the buried conductive layer and made of a different material from the buried conductive layer; an insulating layer formed on the wiring layer surface only in contact with the wiring layer; the insulating layer; and the first insulating layer And a second insulating layer formed thereon.

Further, a part of the surface of the buried conductive layer is exposed from the wiring layer.

Further, the insulator layer is made of a fluoride of titanium or aluminum.

Further, the insulator layer is made of any one oxide selected from the group consisting of tungsten, a tungsten alloy, ruthenium and platinum.

Further, the insulator layer is made of silicon nitride oxide.

Further, the insulator layer has a thickness of 10 to 500 °.

Further, a method of manufacturing a semiconductor device according to the present invention includes the steps of forming a first insulating layer having a connection hole on a semiconductor substrate, forming a buried conductive layer in the connection hole, and Forming a wiring layer on the insulating layer and the buried conductive layer, forming an insulator layer on the wiring layer, forming a mask layer on the insulator layer, and etching using the mask layer as a mask. A step of patterning an insulator layer and a wiring layer, a step of removing a mask layer remaining after the etching step by plasma treatment using oxygen gas, a step of cleaning the semiconductor substrate after the removing step, and a step of cleaning the semiconductor layer after the cleaning step. Forming a second insulating layer on the first insulating layer.

Further, the method further includes a step of forming the surface of the wiring layer or the surface of the metal layer formed on the wiring layer by insulating treatment.

Further, the insulation treatment includes a plasma treatment using an oxidizing gas containing oxygen or water vapor.

The insulation treatment may be performed by using ozone gas or
This includes a heat treatment performed in an atmosphere of an oxidizing gas containing oxygen or water vapor.

Further, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a first insulating layer having a connection hole on a semiconductor substrate, forming a buried conductive layer in the connection hole, and Forming a wiring layer on the insulating layer and the buried conductive layer, forming a mask layer containing an inorganic insulator on the wiring layer, etching the wiring layer using the mask layer as a mask, and patterning the wiring layer And a step of removing the mask layer by plasma treatment using oxygen gas, a step of cleaning the semiconductor substrate after the removing step, and forming a second insulating layer on the insulator layer and the first insulating layer after the cleaning step And a process.

Further, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film having a connection hole on a semiconductor substrate, a step of forming a buried conductive layer in the connection hole, Forming a wiring layer on the embedded conductive layer, forming a mask layer on the wiring layer, etching the wiring layer using the mask layer as a mask, patterning the wiring layer, and using the mask layer with oxygen gas. The method includes a step of performing plasma processing, a step of performing plasma processing using a gas containing an alcohol gas on the surface of the wiring layer from which the mask layer has been removed, and a step of cleaning the semiconductor substrate after the removing step.

Further, a method of manufacturing a semiconductor device according to the present invention includes the steps of forming a first insulating layer having a connection hole on a semiconductor substrate, forming a buried conductive layer in the connection hole, and Forming a wiring layer on the insulating layer and the buried conductive layer, forming a conductive layer made of any one selected from the group consisting of tungsten, tungsten alloy, ruthenium, and platinum on the wiring layer; Forming a mask layer, etching the wiring layer and the conductive layer using the mask layer as a mask, patterning the wiring layer and the conductive layer, and removing and removing the mask layer by plasma treatment using oxygen gas. The method includes a step of cleaning the semiconductor substrate after the step and a step of forming a second insulating layer on the insulator layer and the first insulating layer after the removing step.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a structural sectional view showing a part of a semiconductor device to which a wiring structure according to a first embodiment of the present invention is applied. In the figure, 1 is a semiconductor substrate, 2 is an isolation insulating film for separating and insulating each element region formed on the main surface of the semiconductor substrate 1, 3 is a gate insulating film formed on the semiconductor substrate in the element region, Reference numeral 4 denotes a gate electrode formed with the gate insulating film 3 interposed therebetween, 5 denotes an impurity diffusion layer formed on the main surface of the semiconductor substrate 1 with the gate electrode interposed therebetween, and 6 denotes a first diffusion layer formed on the gate electrode 4. An interlayer insulating film as an insulating layer; 7, a connection hole formed on the interlayer insulating film 6, reaching the surface of the impurity diffusion layer 5; 8, a buried conductive layer made of tungsten embedded in the connection hole;
Is a barrier layer composed of a titanium compound and titanium composite film formed on the side and bottom surfaces of the connection hole 7 or on the surface of the interlayer insulating film 6; 10 is aluminum formed on the buried conductive layer 8 and the barrier layer 9; An aluminum wiring layer made of an aluminum alloy film, 11 is an upper metal film made of titanium or a titanium compound formed on the aluminum wiring layer 10, and 12 is made up of a barrier layer 9, an aluminum wiring layer 10, and an upper metal film 11. Wiring layer, 1
Reference numeral 6 denotes an insulator layer formed only on the surface of the wiring layer 12, 30 denotes a transistor including the gate insulating film 3, the gate electrode 4 and the impurity diffusion layer 5, 70 denotes an interlayer insulating film 6 and a wiring layer 12 is an insulating film as a second insulating layer formed on the insulating film 12.

In the wiring structure of the semiconductor device configured as described above, the wiring layer 12 is formed on the surface of the semiconductor substrate via the connection hole 7 formed in the interlayer insulating film 6 and the buried conductive layer 8 is buried. Electrically connected to the impurity diffusion layer 5 of the transistor 30 thus formed. The wiring layer 12 thus interconnects the transistors in each element region. In addition, the insulating layer 16 formed on the surface of the wiring layer 12 provides a stable connection wiring without disconnection or increase in resistance.

Next, a method of manufacturing a semiconductor device having such a wiring structure will be described. 2 (a) to 2 (c), 3 (d) to 3 (f), and FIG. 4 (g) are enlarged partial steps showing a method of forming only the wiring structure 100 of the semiconductor device shown in FIG. It is sectional drawing. Here, it is assumed that the isolation insulating film 2 and the transistor 30 have already been formed by a normal manufacturing method, and these forming steps are omitted. First, referring to FIG. 2A, an interlayer insulating film 6 is formed on a semiconductor substrate 1 by a CVD method to a thickness of 5000 °.
The semiconductor substrate 1 is formed by etching using a resist film (not shown) formed thereon as a mask.
A connection hole 7 reaching the surface of is formed.

Next, referring to FIG. 2B, in order to secure a sufficient contact between the wiring layer and the semiconductor substrate in the connection hole 7, a barrier is formed on the inner surface of the connection hole 7 and on the interlayer insulating layer 6. As the layer 9, a multilayer film made of a titanium compound and titanium is formed to a thickness of 1000 ° by a sputtering method. Next, referring to FIG. 2 (c), tungsten is formed as a buried conductive layer 6 on barrier layer 9 to a thickness of 5000 ° by a CVD method so as to fill connection holes 7, and then the entire surface is etched. The buried conductive layer 8 buried only in the connection hole 7 is formed by using the back method. As the buried conductive layer 8, a tungsten alloy or polysilicon other than tungsten may be used.

Next, referring to FIG. 3D, an aluminum alloy film containing aluminum or silicon or copper and an upper metal film 11 are formed on the buried conductive layer 8 and the barrier layer 9 as an aluminum wiring layer 10. Titanium or an alloy or compound thereof is sequentially formed to a thickness of 4000 ° and 300 ° by a sputtering method. Further, a silicon oxide film is formed thereon as the insulator layer 16 to a thickness of 200 ° by a method such as a CVD method.
This insulator layer 16 is used to secure film formation stability, in-plane uniformity on a semiconductor substrate or an antistatic effect to be described later, and a resist film serving as a mask layer on the insulator layer 16 using a photolithography technique. It is preferable that the film is formed in a thickness range of 10 ° or more and 500 ° or less in consideration of a reflectance or the like which becomes a problem when forming the film.

Next, referring to FIG.
6, a resist film 13 is formed as a mask layer, and the insulating layer 16, the upper metal film 11, the aluminum wiring layer 10 and the barrier layer 9 are etched using the resist film 13 as a mask, so that the wiring layer 12 and the semiconductor substrate 1 are buried. Wiring layer 1 so as to be electrically connected through connection hole 7 in which embedded conductive layer 8 is embedded.
2 is patterned. However, here, in order to facilitate the description of the present invention, a case is shown in which the wiring layer 12 is shifted from the connection hole 7 and is patterned with a part 17 of the surface of the buried conductive layer 8 exposed. For example, 256M
In a highly integrated circuit such as a DRAM, both the wiring width and the diameter of the connection hole are about 0.3 μm, and strict alignment accuracy is required, and the above-described shift may actually occur at a considerable rate.

Next, referring to FIG. 3F, the resist film 13 remaining after the etching is removed by a plasma treatment (ashing treatment) of a gas containing oxygen. In this ashing process, overashing of about 50% to 100% is performed on the maximum thickness of the remaining resist film 13 in order to enhance the removability. However, the resist film 13 is deteriorated and hardened by the plasma of the previous etching process or this ashing process, and is not sufficiently removed only by such ashing process, so that the surface of the insulator layer 16 and the wiring layer 1 are not removed.
2 may be left as a resist residue 15 on the side surface.

Therefore, the semiconductor substrate is immersed in a cleaning liquid to remove the resist residue 15. As the cleaning liquid, usually, an alkaline organic solvent or a neutral or weakly acidic organic solvent, or an inorganic cleaning liquid is used.In particular, as the alkaline organic solvent, an amine-based organic solvent is usually used. Used. This organic solvent contains an alkanolamine such as hydroxylamine or monoethanolamine as a main component, has a high solvent dissolving power, and has an action of slightly etching metals such as aluminum and titanium. Further, amines show strong alkalinity when mixed with water, and the pH value of the cleaning liquid often shows 10 or more, but the etching property is weak for a single metal such as tungsten, for example, at 60 ° C. for 30 minutes. The etching amount in the immersion treatment of the stripping solution is 30 ° or less. However, when the oxidation-reduction potential of tungsten is high, even a metal such as tungsten easily dissolves due to the electrochemical action in the cleaning solution.

Finally, referring to FIG. 4G, wiring layer 1
On the wiring layer 12 as a second insulating layer, the wiring layer 12 is further insulated from a wiring layer formed thereon;
Is formed to protect the semiconductor device from outside air.

In the above description, an example in which a silicon oxide film is used as the insulator layer 16 is shown. However, the present invention is not limited to this. A silicon nitride film, silicon nitride oxide, a silicon oxide film containing fluorine, and a wiring An insulating film that insulates the ashing plasma from the wiring layer, such as titanium oxide or aluminum oxide, which is an oxide of titanium or aluminum, or titanium fluoride or aluminum fluoride, which is a fluoride of titanium or aluminum. If it is, charging of the wiring layer can be prevented. In particular, since the fluoride is bonded to fluorine having a higher electronegativity than oxygen, it is difficult to remove electrons from the wiring layer, and the effect of preventing the wiring layer from being charged is high.

When a silicon oxynitride film is used as the insulating layer 16, this film also functions as an antireflection film for reducing the reflectance. FIGS. 5 and 6 show the relationship between the thickness and the reflectance of the silicon nitride oxide film and the relationship between the refractive index and the reflectance, respectively, when KrF excimer laser light (wavelength: 248 nm) is used as the exposure light source. It is. FIG. 5 shows that the film thickness is between 200 ° and 500 °, and FIG. 6 shows that the reflectance is low within a certain range of the refractive index. As a result, the reflectivity can be reduced, so that the resist film formed on the insulator layer does not deteriorate, and therefore, a desired wiring layer without deterioration can be formed.

Furthermore, in the above description, the case where the insulating film is formed by the CVD method has been described.
Not limited to this, a plasma CVD method, spin coating such as spin-on-glass, or a sputtering method (PVD) using an insulator as a target can be used.

In the method of forming the wiring structure as described above, the insulator layer 16 formed on the surface of the wiring layer 12 electrically connects the oxygen gas plasma and the wiring layer 12 during the ashing process for removing the resist film 13. Since the insulating layer is electrically insulated, it is possible to prevent the surface of the wiring layer 12 from being exposed to oxygen plasma during the ashing process, thereby preventing electrons from being deprived from the surface by oxygen radicals having high electronegativity and being positively charged. The potential of the buried conductive layer 8 does not increase.

Therefore, even if the wiring layer 12 is formed so as to be displaced from the connection hole 7 and a part 17 of the surface of the buried conductive layer 8 is exposed, it is immersed in a cleaning solution for removing the resist residue thereafter. However, since the potential of the buried conductive layer 8 is not high, the effect of preventing the buried conductive layer 8 from dissolving or disappearing due to the electrochemical action is exerted, such as disconnection between wirings and increase in resistance. A wiring structure without connection failure can be obtained, and a highly reliable semiconductor device can be obtained. In particular, when a silicon nitride oxide film is used as the insulating layer 16, this film serves as an antireflection film, so that a highly reliable semiconductor device with no deterioration of the wiring layer can be obtained.

Embodiment 2 In the first embodiment,
The insulator layer 16 formed on the wiring layer 12 of the wiring structure is C
Although this embodiment is directly formed by the VD method or the like, the present embodiment relates to a method of forming an insulator layer by insulating the surface of the wiring layer 12 or the surface of a metal film newly formed on the wiring layer 12. Things. Hereinafter, the wiring structure portion 100 according to the second embodiment of the semiconductor device shown in FIG.
Will be described with reference to the partial process sectional views shown in FIGS. 7A and 7B. In both figures, the same reference numerals as those in FIGS. 2 to 4 indicate the same or corresponding parts.

First, referring to FIG. 7A, after forming up to the wiring layer 12 in the same manner as in the first embodiment, titanium is formed on the wiring layer 12 as a metal film 18 by sputtering at a thickness of 200 °. To a film thickness of This metal film 18
Problems in securing film formation stability, in-plane uniformity on a semiconductor substrate or an antistatic effect to be described later, and when forming a resist film or the like serving as a mask layer on the insulator layer 16 using photolithography technology. It is preferable to form the film in the range of 10 ° to 500 ° in consideration of the reflectance and the like. Note that a metal film such as aluminum or silicon may be used instead of titanium.

Next, referring to FIG.
Is exposed to plasma using an oxidizing gas such as oxygen or water vapor for a certain period of time to oxidize the metal film 18 by radicals of the oxidizing gas in the plasma to form a metal oxide film of titanium as the insulator layer 16. Hereinafter, FIG. 3 of the first embodiment
As shown in (e), the resist film 1 is formed on the insulator layer 16.
3 is formed, and the insulating layer 16 and the wiring layer 12 are etched using the mask as a mask.
Is patterned. FIG. 3 of the first embodiment
As shown in (f), the remaining resist film 13 is removed by ashing. After that, the semiconductor substrate is immersed in a cleaning liquid such as an amine-based organic solvent to remove the remaining resist residue 15. Finally, an insulating film 70 is formed on the wiring layer 12 and the interlayer insulating film 6, as shown in FIG. As described above, the wiring structure according to the present embodiment is formed.

In addition, as a method of insulating, in addition to the method described above, a method of performing heat treatment at about 300 ° C. in an atmosphere of an oxidizing gas such as ozone gas, oxygen, or water vapor, or a dipping treatment in an aqueous solution containing ozone gas or oxygen And a method of performing a heat treatment at about 300 ° C. in an atmosphere of a fluorinated gas containing a fluorine gas.

In the above description, the case where the metal layer 18 is newly formed on the wiring layer 12 is shown. However, without forming such a metal layer, the surface of the wiring layer 12 is formed by the method described above. Direct insulation treatment may be performed.

In the method of forming the wiring structure according to the second embodiment configured as described above, the wiring layer 12
Insulator layer 1 formed by insulating the metal film 18 formed on the surface of the substrate or the upper metal film 11 of the wiring layer 12.
6 electrically insulates the oxygen gas plasma from the wiring layer 12 during the ashing process for removing the resist film 13, so that the surface of the wiring layer 12 is exposed to the oxygen plasma during the ashing process and has a high electronegativity. Electrons can be prevented from being deprived of electrons from the surface by oxygen radicals and charged positively, and the potential of the embedded conductive layer 8 does not increase. Therefore, even if the wiring layer 12 is shifted from the connection hole 7, for example,
Even if the semiconductor substrate in a state where a part 17 of the surface of the buried conductive layer 8 is exposed is immersed in a cleaning liquid, the buried conductive layer 8 does not dissolve or disappear due to the electrochemical action, and the wiring A stable wiring structure free from connection failure such as disconnection between wires and a rise in resistance can be obtained, and a highly reliable semiconductor device can be obtained.

Embodiment 3 FIG. In the second embodiment, the insulator layer for preventing electrification of the wiring layer is formed by insulating the metal film. However, in the second embodiment, a resist film serving as a mask for patterning the wiring layer or an organic antireflection film is further provided. An inorganic insulator is mixed into the film to form an insulator layer simultaneously with the ashing process. Hereinafter, Embodiment 3
(A) and (b) of FIG.
Description will be made with reference to a partial process sectional view shown in FIG. In these figures, the same reference numerals as those in FIGS. 2 to 4 indicate the same or corresponding parts.

First, referring to FIG. 8A, after forming up to the wiring layer 12 using the same method as in the first embodiment,
On the wiring layer 12, a resist film 13 mixed with an inorganic insulator 19 such as silicon oxide is formed as a mask layer for etching the wiring layer 12. The mixing of the inorganic insulator 19 into the resist film 13 is performed by directly ion-implanting the inorganic insulator 19 after patterning the resist film 13 as shown in FIG. The resist film 13 may be formed using the resist. In addition, as the inorganic insulator 19, aluminum, titanium and their oxides, tungsten and its oxides, silicon oxide,
Silicon nitride, silicon nitride oxide, a mixture thereof, or the like may be used.

Next, referring to FIG. 8B, the wiring layer 12 is etched and patterned using the resist film 13 mixed with the inorganic insulator 19 as a mask. FIG. 8B shows the same as Embodiments 1 and 2,
This shows a state where the wiring layer 12 is shifted from the connection hole 7 and a part 17 is exposed on the surface of the buried conductive layer 8. Next, FIG.
Referring to (c), the resist film 13 remaining after the etching of the wiring layer 12 is removed by ashing using plasma of a gas containing oxygen. At this time, the resist film 1
The inorganic insulator 19 mixed in 3 remains on the surface of the wiring layer 12 together with the resist residue 15 as an insulator layer 16 without being removed, and electrically insulates the oxygen gas plasma from the wiring layer 12 during overashing. Play a role. Thereafter, in order to remove the resist residue 15, the semiconductor substrate 1 is immersed in a cleaning liquid such as an amine-based organic solvent. Finally, as shown in FIG.
Then, an insulating film 70 is formed on the interlayer insulating film 6. The wiring structure according to the third embodiment is formed as described above.

In the above description, the case where an inorganic insulator is mixed in the resist film is shown. However, when a resist film is formed, an organic anti-reflection film for preventing reflection is used below the resist film. May be mixed with an inorganic insulating material in the organic antireflection film instead of the resist film. In this case, if the inorganic insulator is a silicon oxide film,
Assuming that the density is 2 g / cm ³ and the density of the organic anti-reflection film is 1 g / cm ³ , the thickness of the insulator layer is required to be 10 ° or more in order to ensure insulation as antistatic during ashing. The thickness of the organic antireflection film is 1
If it is 000 °, the content of the silicon oxide film in the organic antireflection film is 2% or more. Further, the organic antireflection film in which the inorganic insulator is mixed may be formed on a resist film depending on the use.

In the method of forming the wiring structure according to the third embodiment configured as described above, the wiring layer 12
The insulator layer 16 made of the inorganic insulator 19 formed on the surface of the substrate electrically insulates the oxygen gas plasma and the wiring layer 12 during the ashing process for removing the resist film. 12 can be prevented from being exposed to oxygen plasma to remove electrons from the surface due to oxygen radicals having high electronegativity and being positively charged, and the potential of the buried conductive layer 8 does not increase. . Therefore, even if the wiring layer 12 is displaced from the connection hole 7 and the semiconductor substrate in a state where a part 17 of the surface of the embedded conductive layer 8 is exposed is immersed in the cleaning liquid, the embedded conductive layer 8 does not dissolve or disappear. Therefore, a stable wiring structure free from connection failures such as disconnection between wires and increase in resistance can be obtained, and a highly reliable semiconductor device can be obtained.

Embodiment 4 FIG. In the above embodiment, in the step of removing the resist film, the wiring layer 12 is prevented from being charged by the oxygen gas plasma. However, in this embodiment, the charged charge of the wiring layer 12 is reduced. It relates to a method for removing static electricity.

First, referring to FIG. 14 (f) showing a conventional method for forming a wiring structure, a wiring layer 12 has a resist residue 15 adhered to the surface and side surfaces thereof, and has a high oxygen content when the resist film is removed. Electrons are deprived by oxygen radicals in the plasma and are positively charged. As described above, when the semiconductor substrate is immersed in a cleaning solution to remove the resist residue 15 in such a state, the potential of the buried conductive layer 8 is also increased because the wiring layer 12 is charged. When the wiring layer 12 is formed so as to be shifted from the connection hole 7 as shown in FIG. 15 and a part 17 of the surface of the buried conductive layer 8 is exposed, as shown in FIG. The embedded conductive layer 8 is easily dissolved by the electrochemical action.

Therefore, in the present embodiment, the charged wiring layer 12 is exposed to a plasma of a gas containing methyl alcohol for a certain period of time before the immersion treatment of the cleaning solution for removing the resist residue is performed to remove the charged charges. Remove static electricity in advance. Similar effects can be obtained by using a general alcohol gas such as methanol or IPA in addition to methyl alcohol as a gas for static elimination. And
After performing such a charge elimination process, the resist residue 15 is removed again by immersion treatment with a cleaning solution such as an amine-based organic solvent.

Embodiment 4 configured as described above
In the method for forming a wiring structure according to the above, since the wiring layer 12 charged in the step of removing the resist film after patterning the wiring layer 12 is exposed to plasma using a gas containing an alcohol gas to remove electricity, , Wiring layer 12
And the contact hole 7 is displaced to expose a part 17 of the surface of the buried conductive layer 8, and even if a immersion treatment with a cleaning solution for removing the resist residue 15 is performed, No dissolution or disappearance occurs. Therefore, it is possible to obtain a stable wiring structure with no connection failure such as disconnection between wirings or an increase in resistance, and to obtain a highly reliable semiconductor device.

Embodiment 5 FIG. The present embodiment relates to another method for removing charges from the charged wiring layer 12. Hereinafter, a method for forming a wiring structure according to the fifth embodiment will be described with reference to partial process cross-sectional views shown in FIGS. In these figures, the same reference numerals as those in FIGS. 2 to 4 indicate the same or corresponding parts.

First, referring to FIG. 10 (a), after forming up to wiring layer 12 using the same method as in the first embodiment, tungsten is formed on wiring layer 12 as conductive layer 20 by sputtering. It is formed appropriately to a thickness of 10 ° to 500 °. As the conductive layer 20, a metal having a high conductivity such as a tungsten alloy, such as a tungsten alloy, is used in addition to tungsten. Next, referring to FIG. 10B, a resist film 13 is formed on conductive layer 20, and using this as a mask, conductive layer 20 and wiring layer 12 are etched to pattern conductive layer 20 and wiring layer 12. . However, the figure shows a state in which the wiring layer 12 is shifted from the connection hole 7 and a part 17 of the surface of the buried conductive layer 8 is exposed.

Next, referring to FIG. 10C, the resist film 13 remaining by the etching is removed by ashing using plasma containing oxygen. At this time, the resist residue 15 is attached to the surface of the conductive layer 20 and the side surface of the wiring layer 12, and the wiring layer 12 is positively charged by oxygen gas plasma during overashing.
Further, the conductive layer 20 is oxidized by the plasma, and a tungsten metal oxide (not shown) is formed on the surface thereof. This metal oxide has the property of having higher conductivity than other metal oxides. As the conductive layer 20 having such properties, a tungsten alloy or ruthenium may be used. Then, in order to remove the resist residue 15, an immersion treatment with a cleaning liquid such as an amine-based organic solvent is performed. Finally, as shown in FIG. 4G, an insulating film 70 is formed on the wiring layer 12 and the interlayer insulating film 6.
The wiring structure according to the fifth embodiment is formed as described above.

Embodiment 5 configured as described above
According to the method for forming a wiring structure according to the above, even if the wiring layer 12 is charged during the ashing process, the metal oxide of the conductive layer 20 formed by oxidation by the ashing process exhibits a high conductivity. Therefore, the charges accumulated through the metal oxide in the cleaning solution for removing the resist residue 15 are discharged instantaneously. Therefore, the oxidation-reduction potential of the buried conductive layer 8 also instantaneously decreases, so that even if the wiring layer 12 is displaced from the connection hole 7 and a part 17 of the surface of the buried conductive layer 8 is exposed, Dissolution or disappearance of the embedded conductive layer 8 due to electrochemical action does not occur. Therefore, it is possible to obtain a stable wiring structure with no connection failure such as disconnection between wires or increase in resistance,
A highly reliable semiconductor device can be obtained.

In the above embodiment, the wiring structure of the present invention has been described only for the case of single-layer wiring.
The present invention can also be applied as a part of a multilayer wiring structure as shown in FIG.
In FIG. 11, the wiring structure 150 of the present invention is formed on the semiconductor substrate 1 and has a multilayer structure together with the wiring layer 120 connected to the semiconductor substrate 1 through the connection hole of the interlayer insulating film 60 including the transistor 30. It has a wiring structure. Further, the wiring structure of the present invention may be applied to all layers in a multilayer wiring structure (not shown). Further, the wiring structure of the present invention is not limited to semiconductor integrated circuits such as DRAMs and SRAMs, and can be applied to various semiconductor devices.

[0068]

Since the present invention is configured as described above, it has the following effects.

Since the insulator layer formed in contact with the surface of the wiring layer prevents the charging of the wiring layer during the ashing process and does not increase the potential of the buried conductive layer, a cleaning solution for removing the resist residue Even if the immersion treatment is performed, the embedded conductive layer is prevented from being dissolved or disappeared, a wiring structure free from connection failure such as disconnection between wirings or an increase in resistance can be obtained, and a highly reliable semiconductor device can be obtained.

Further, since fluoride is used for the insulator layer formed in contact with the surface of the wiring layer, the antistatic effect of the wiring layer can be enhanced, and a more reliable semiconductor device can be obtained. Can be.

Further, since silicon nitride oxide is used for the insulator layer formed in contact with the surface of the wiring layer, reflection at the time of forming a resist film can be prevented, and A highly reliable semiconductor device without deterioration can be obtained.

Further, by forming the insulator layer so as to be in contact with the surface of the wiring layer, the charging of the wiring layer can be prevented, and the reliability of the embedded conductive layer without dissolving or disappearing by the cleaning liquid can be improved. A method for manufacturing a semiconductor device having a high wiring structure can be obtained.

Further, since the charge of the wiring layer charged by the plasma treatment with the alcohol gas can be eliminated, a method of manufacturing a semiconductor device having a highly reliable wiring structure in which the embedded conductive layer is not dissolved or disappeared by the cleaning liquid. Can be obtained.

Further, by forming the conductive layer so as to be in contact with the surface of the wiring layer, the charge of the charged wiring layer can be eliminated, so that the embedded conductive layer is not dissolved or disappeared by the cleaning liquid. A method for manufacturing a semiconductor device having a highly reliable wiring structure can be obtained.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a semiconductor device having a wiring structure according to a first embodiment;

FIG. 2 is a partial process sectional view illustrating the method for forming the wiring structure according to the first embodiment;

FIG. 3 is a partial process sectional view illustrating the method for forming the wiring structure according to the first embodiment;

FIG. 4 is a partial process sectional view illustrating the method for forming the wiring structure according to the first embodiment;

FIG. 5 is a diagram showing a relationship between the thickness of a silicon nitride oxide film and the reflectance according to the first embodiment;

FIG. 6 is a graph showing a relationship between the refractive index and the reflectance of the silicon nitride oxide film of Embodiment 1;

FIG. 7 is a partial process sectional view illustrating the method for forming the wiring structure according to the second embodiment;

FIG. 8 is a partial process sectional view illustrating the method for forming the wiring structure according to the third embodiment;

FIG. 9 is a partial process sectional view illustrating the method of forming the wiring structure according to the third embodiment;

FIG. 10 is a partial process sectional view illustrating the method of forming the wiring structure according to the fifth embodiment;

FIG. 11 is a configuration sectional view of a semiconductor device in which the wiring structure according to the first to fifth embodiments is applied to a multilayer wiring structure;

FIG. 12 is a configuration sectional view of a semiconductor device having a conventional wiring structure.

FIG. 13 is a partial cross-sectional process view showing a conventional method for forming a wiring structure.

FIG. 14 is a partial cross-sectional process view showing a conventional method for forming a wiring structure.

FIG. 15 is a cross-sectional view of a configuration for explaining charging of a wiring in a conventional wiring structure.

FIG. 16 is a configuration sectional view for explaining dissolution of a buried conductive layer in a conventional wiring structure.

[Explanation of symbols]

1 semiconductor substrate, 6 interlayer insulating film, 7 connection hole,
Reference Signs List 8 embedded conductive layer 12 wiring layer, 13 resist film, 16 insulator layer, 18 metal layer 19 inorganic insulator, 20 conductive layer

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) SS08 SS11 SS15 SS21 SS25 SS26 SS27 VV16 WW02 XX00 XX09 XX15 XX21

Claims (13)

[Claims] 1. A semiconductor device having a wiring structure using a buried conductive layer, comprising: a first insulating layer having a connection hole formed on a semiconductor substrate; A conductive layer; a wiring layer formed on the first insulating layer and the buried conductive layer, made of a material different from the buried conductive layer; and an insulator layer formed only on the surface of the wiring layer. And a second insulating layer formed on the insulator layer and the first insulating layer. 2. The semiconductor device according to claim 1, wherein the wiring layer covers a part of the surface of the buried conductive layer. 3. The semiconductor device according to claim 1, wherein the insulator layer is made of titanium or aluminum fluoride. 4. The semiconductor device according to claim 1, wherein the insulator layer is made of any one oxide selected from the group consisting of tungsten, a tungsten alloy, ruthenium, and platinum.
13. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the insulating layer is an insulating film made of silicon nitride oxide. 6. The semiconductor device according to claim 1, wherein the insulator layer has a thickness of 10 ° to 500 °. 7. A method of manufacturing a semiconductor device having a wiring structure using a buried conductive layer, comprising: forming a first insulating layer having a connection hole on a semiconductor substrate; Forming an embedded conductive layer; forming an interconnect layer on the first insulating layer and the buried conductive layer; forming an insulator layer on the interconnect layer; A step of forming a mask layer, a step of patterning the insulator layer and the wiring layer by etching using the mask layer as a mask, and a step of plasma-treating the mask layer remaining after the etching step using an oxygen gas. A semiconductor device comprising: a removing step; a step of cleaning the semiconductor substrate after the removing step; and a step of forming a second insulating layer on the insulator layer and the first insulating layer after the cleaning step. of Production method. 8. The step of forming an insulator layer on a wiring layer includes the step of forming a surface of the wiring layer or a surface of a metal layer formed on the wiring layer by insulating treatment. The manufacturing method of the semiconductor device described in the above. 9. The method for manufacturing a semiconductor device according to claim 7, wherein the insulation treatment includes a plasma treatment using an oxidizing gas containing oxygen or water vapor. 10. The method for manufacturing a semiconductor device according to claim 7, wherein the insulation treatment includes a heat treatment performed in an atmosphere of an oxidizing gas containing ozone gas or an oxidizing gas containing oxygen or water vapor. 11. A method of manufacturing a semiconductor device having a wiring structure using a buried conductive layer, comprising: forming a first insulating layer having a connection hole on a semiconductor substrate; Forming a wiring layer on the first insulating layer and the buried conductive layer; forming a mask layer containing an inorganic insulator on the wiring layer; Etching the wiring layer using the mask layer as a mask and patterning the wiring layer; removing the mask layer by plasma treatment using oxygen gas; and cleaning the semiconductor substrate after the removing step. A method of manufacturing a semiconductor device, comprising: a step of forming a second insulating layer on the insulator layer and the first insulating layer after the cleaning step. 12. A method of manufacturing a semiconductor device having a wiring structure using a buried conductive layer, comprising: forming a first insulating layer having a connection hole on a semiconductor substrate; Forming a wiring layer on the first insulating layer and the buried conductive layer; forming a mask layer on the wiring layer; and forming the wiring layer on the mask layer. Etching with the mask as a mask and patterning the wiring layer; removing the mask layer by plasma treatment using oxygen gas; and a gas containing an alcohol gas on the wiring layer surface from which the mask layer has been removed. Performing a plasma treatment using: a step of cleaning the semiconductor substrate after the removing step; and a step of forming a second insulating layer on the insulator layer and the first insulating layer after the cleaning. Half A method for manufacturing a conductor device. 13. A method for manufacturing a semiconductor device having a wiring structure using a buried conductive layer, comprising: forming a first insulating layer having a connection hole on a semiconductor substrate; Forming a wiring layer on the first insulating layer and the buried conductive layer; and forming any of tungsten, tungsten alloy, ruthenium, and platinum on the wiring layer. Forming a conductive layer made of any one of the above, forming a mask layer on the conductive layer, etching the wiring layer and the conductive layer using a mask layer as a mask, and forming the wiring layer and the conductive layer Patterning, removing the mask layer by plasma treatment using oxygen gas, cleaning the semiconductor substrate after the removing step, and removing the insulating layer and the Forming a second insulating layer on the first insulating layer.