JP2000114449A - Semiconductor device and its lead frame and manufacture thereof - Google Patents
Semiconductor device and its lead frame and manufacture thereofInfo
- Publication number
- JP2000114449A JP2000114449A JP28095298A JP28095298A JP2000114449A JP 2000114449 A JP2000114449 A JP 2000114449A JP 28095298 A JP28095298 A JP 28095298A JP 28095298 A JP28095298 A JP 28095298A JP 2000114449 A JP2000114449 A JP 2000114449A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- lead frame
- convex portion
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置とその
リードフレーム及びその製造方法に係わり、特に、安定
したワイヤーボンディングを可能にし、歩留まりを向上
せしめた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a lead frame thereof, and a method of manufacturing the same, and more particularly, to a semiconductor device which enables stable wire bonding and improves the yield.
【０００２】[0002]
【従来の技術】図３に示すように、従来のリードフレー
ムを用いたＢＧＡ型半導体装置は、リードフレーム１０
にリード先端部を除きハーフエッチ８を行い、リード先
端部に凸部３を形成し、この凸部のみがパッケージ裏面
に露出するように樹脂封止し、凸部３に半田ボール１を
取り付け、ＢＧＡ型樹脂封止型半導体装置としていた。2. Description of the Related Art As shown in FIG. 3, a BGA type semiconductor device using a conventional lead frame is
Then, half-etching 8 is performed except for the leading end of the lead, a convex portion 3 is formed at the leading end of the lead, and resin sealing is performed so that only the convex portion is exposed on the back surface of the package. It was a BGA resin-sealed semiconductor device.
【０００３】この場合、ボンディング部裏面はハーフエ
ッチ８されており、リードフレームの断面から見るとボ
ンディング部裏面がリードフレームの最下面とはなって
いない。従って、ボンディングを行う際には、ボンディ
ング部裏面とヒータープレートとの間に隙間ができない
ように、ヒータープレートのボンディング部裏面に当た
る部分を盛り上げるような加工が必要であった。In this case, the back surface of the bonding portion is half-etched 8, and when viewed from the cross section of the lead frame, the back surface of the bonding portion is not the lowermost surface of the lead frame. Therefore, when performing bonding, it is necessary to perform processing to raise a portion of the heater plate corresponding to the back surface of the bonding portion so that no gap is formed between the back surface of the bonding portion and the heater plate.
【０００４】しかし、ヒータープレートの加工精度によ
り、リードフレーム側のハーフエッチされた部分とヒー
タープレートの間に隙間が発生することがあり、このよ
うな場合、ボンディング性を低下させていた。However, a gap may be formed between the half-etched portion on the lead frame side and the heater plate depending on the processing accuracy of the heater plate, and in such a case, the bonding property is reduced.
【０００５】[0005]
【発明が解決しようとする課題】本発明の目的は、上記
した従来技術の欠点を改良し、特に、安定したワイヤー
ボンディングを可能にした新規な半導体装置とそのリー
ドフレーム及びその製造方法を提供するものである。SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art and, in particular, to provide a novel semiconductor device capable of performing stable wire bonding, a lead frame thereof, and a method of manufacturing the same. Things.
【０００６】[0006]
【課題を解決するための手段】本発明は上記した目的を
達成するため、基本的には、以下に記載されたような技
術構成を採用するものである。即ち、本発明に係わる半
導体装置の第１態様は、半田ボールを搭載するためリー
ドフレームに形成した第１の凸部をパッケージ裏面に露
出するようにした半導体装置において、前記リードフレ
ームに半田ボールを搭載しない第２の凸部を形成し、こ
の凸部を前記パッケージ裏面に露出するように構成した
ことを特徴するものであり、叉、第２態様は、前記第２
の凸部は、前記パッケージ裏面の外周部に配設されるこ
とを特徴とするものであり、叉、第３態様は、前記第１
の凸部と第２の凸部との板厚は等しいことを特徴とする
ものであり、叉、第４態様は、前記第１の凸部と第２の
凸部とが接続していることを特徴とするものであり、
叉、第５態様は、前記第２の凸部は、パッケージ裏面の
外周部の一辺に少なくとも二つ形成されていることを特
徴とするものであり、叉、第６態様は、前記パッケージ
の側面から前記リードフレームのリードが導出され、こ
の導出されたリードがパッケージに沿って成形され、且
つ、リードの端部がパッケージ上面に配設されているこ
とを特徴とするものである。SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, a first aspect of a semiconductor device according to the present invention is a semiconductor device in which a first convex portion formed on a lead frame for mounting a solder ball is exposed on the back surface of the package. A second projection which is not mounted is formed, and the projection is configured to be exposed on the back surface of the package.
Are disposed on the outer periphery of the back surface of the package, and the third aspect is the first aspect.
The thickness of the convex portion is equal to the thickness of the second convex portion, and the fourth aspect is that the first convex portion and the second convex portion are connected to each other. It is characterized by,
According to a fifth aspect, at least two of the second protrusions are formed on one side of an outer peripheral portion of a back surface of the package, and a sixth aspect is a side surface of the package. , Leads of the lead frame are led out, the leads are formed along the package, and the ends of the leads are arranged on the upper surface of the package.
【０００７】叉、本発明に係わるリードフレームの態様
は、半導体チップを搭載するリードフレームであって、
半田ボールを搭載するランドとなる第１の凸部と、前記
第１の凸部を囲むように形成された第２の凸部とを少な
くとも含むことを特徴とするものである。叉、本発明に
係わるリードフレームの製造方法の態様は、半導体チッ
プを搭載するリードフレームをエッチングにより製造す
る方法であって、前記エッチングを行う際、半田ボール
を搭載するランドとなる第１の凸部を形成すると共に、
前記第１の凸部を囲むように第２の凸部を形成すること
を特徴とするものである。An aspect of the lead frame according to the present invention is a lead frame on which a semiconductor chip is mounted,
It is characterized by including at least a first convex portion serving as a land on which a solder ball is mounted, and a second convex portion formed so as to surround the first convex portion. An aspect of the method for manufacturing a lead frame according to the present invention is a method for manufacturing a lead frame on which a semiconductor chip is mounted by etching, wherein the first protrusion serving as a land on which a solder ball is mounted upon performing the etching. Forming a part,
A second projection is formed so as to surround the first projection.
【０００８】[0008]
【発明の実施の形態】本発明に係わる半導体装置は、半
田ボールを搭載するためリードフレームに形成した第１
の凸部をパッケージ裏面に露出するようにした半導体装
置において、前記リードフレームに半田ボールを搭載し
ない第２の凸部を形成し、この凸部を前記パッケージ裏
面に露出するように構成したものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention has a first structure formed on a lead frame for mounting solder balls.
In the semiconductor device in which the convex portion is exposed on the back surface of the package, a second convex portion on which no solder ball is mounted is formed on the lead frame, and the convex portion is exposed on the back surface of the package. is there.
【０００９】従って、リードフレームは、ヒータプレー
ト上に平らに載置され、しかも、リードフレームは、第
１の凸部と、この第１の凸部を囲むように形成された第
２の凸部とで支持される。この為、リードフレームにワ
イヤーボンディングする際、安定した状態でボンディン
グすることができ、歩留まりが向上する。Therefore, the lead frame is placed flat on the heater plate, and the lead frame has a first convex portion and a second convex portion formed so as to surround the first convex portion. Supported by Therefore, when performing wire bonding to the lead frame, bonding can be performed in a stable state, and the yield is improved.
【００１０】[0010]
【実施例】以下に、本発明に係わる半導体装置とそのリ
ードフレーム及びその製造方法の具体例を図面を参照し
ながら詳細に説明する。 （第１の具体例）図１（ａ），（ｂ）は、本発明に係わ
る半導体装置の具体例の構造を示す図であって、これら
の図には、半田ボール１を搭載するためリードフレーム
２に形成した第１の凸部３をパッケージ４裏面４ａに露
出するようにした半導体装置５において、前記リードフ
レーム２に半田ボールを搭載しない第２の凸部６を形成
し、この凸部６を前記パッケージ裏面４ａに露出するよ
うに構成した半導体装置が示され、叉、前記第２の凸部
６は、前記パッケージ裏面４ａの外周部４ｂに配設され
る半導体装置が示され、叉、前記第１の凸部３と第２の
凸部６との板厚ｔは等しい半導体装置が示され、叉、前
記第１の凸部３と第２の凸部６とが接続している半導体
装置が示され、叉、前記第２の凸部６は、パッケージ裏
面４ａの外周部４ｂの一辺に少なくとも二つ形成されて
いる半導体装置が示されている。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor device according to the present invention; FIG. (First Specific Example) FIGS. 1A and 1B are views showing the structure of a specific example of a semiconductor device according to the present invention. In these figures, leads for mounting solder balls 1 are shown. In the semiconductor device 5 in which the first convex portion 3 formed on the frame 2 is exposed on the back surface 4a of the package 4, a second convex portion 6 on which no solder ball is mounted on the lead frame 2 is formed. 6 shows a semiconductor device configured to expose the package back surface 4a to the package back surface 4a, and shows the semiconductor device disposed on the outer peripheral portion 4b of the package back surface 4a as the second convex portion 6. A semiconductor device having the same thickness t between the first convex portion 3 and the second convex portion 6 is shown, and the first convex portion 3 and the second convex portion 6 are connected. A semiconductor device is shown, and the second convex portion 6 is provided on an outer peripheral portion 4 of a package back surface 4a. The semiconductor device that is at least two formed is shown in the side.
【００１１】以下に、図１を用いて、本発明を更に詳細
に説明する。図１には、リードフレーム２上に絶縁性接
着剤１１を用いて半導体チップ１２を固定し、更に、半
導体チップ１２とリードフレーム２とをワイヤ１３で接
続し、全体を樹脂１４で封止し、リードフレーム２の第
１の凸部３をパッケージ裏面４ａに露出して半田ボール
１を取付けると共に、第２の凸部６もパッケージ裏面４
ａに露出した状態の半導体装置が示されている。Hereinafter, the present invention will be described in more detail with reference to FIG. In FIG. 1, a semiconductor chip 12 is fixed on a lead frame 2 using an insulating adhesive 11, and further, the semiconductor chip 12 and the lead frame 2 are connected by wires 13, and the whole is sealed with a resin 14. The first convex portion 3 of the lead frame 2 is exposed on the package back surface 4a, and the solder ball 1 is mounted.
The semiconductor device exposed to a is shown.
【００１２】特に、本発明のリードフレーム２の片面に
ハーフエッチ８を施し、１本のリード（内部リード）に
対して２つの凸部を設けている。第１の凸部３は、リー
ド先端側に設けられ、第２の凸部６は、パッケージ裏面
外周部４ｂに設けられている。叉、リード先端側の第１
の凸部３には半田ボール１を取り付け、ＢＧＡ型樹脂封
止半導体装置を形成している。In particular, a half-etch 8 is provided on one surface of the lead frame 2 of the present invention, and two protrusions are provided for one lead (internal lead). The first protrusion 3 is provided on the lead tip side, and the second protrusion 6 is provided on the outer peripheral portion 4b of the package rear surface. Also, the first on the lead tip side
The solder balls 1 are attached to the convex portions 3 of the semiconductor device, thereby forming a BGA type resin-sealed semiconductor device.
【００１３】この半導体装置の組立工程（ボンディング
工程）においては、パッケージ裏面外周部４ｂの第２の
凸部６をボンディング部７の裏面に配置することで、単
純な構造（平坦）のヒータープレートを用いることがで
きるようになり、ボンディング部裏面４ａとヒータープ
レート（図示せず）の間に隙間ができることがなくな
り、この為、安定したボンディング特性が得られる。In the semiconductor device assembling step (bonding step), the heater plate having a simple structure (flat) is formed by disposing the second convex portion 6 of the outer peripheral portion 4b of the package on the back surface of the bonding portion 7. As a result, no gap is formed between the back surface 4a of the bonding portion and the heater plate (not shown), so that stable bonding characteristics can be obtained.
【００１４】図１（ｂ）に、樹脂封止型半導体装置の端
子面を示している。リード先端部の第１の凸部（ラン
ド）３に半田ボール１を付けない場合は、ＬＧＡ（Ｌａ
ｎｄ Ｇｒｉｄ Ａｌｌｅｙ）型樹脂封止型半導体装置
となり、実装基板の設計によっては、パッケージ裏面外
周部４ｂにある第２の凸部６を電極端子として用い、Ｑ
ＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎ−ｌｅａｄ Ｐａｃ
ｋａｇｅ）やＳＯＮ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｎ
ｏｎ−ｌｅａｄ Ｐａｃｋａｇｅ）と同様に扱うことの
できる樹脂封止型半導体装置とすることができる。 （第２の具体例）図２に本発明の第２の具体例の断面図
を示す。FIG. 1B shows a terminal surface of the resin-sealed semiconductor device. When the solder ball 1 is not attached to the first convex portion (land) 3 at the tip of the lead, LGA (La
nd Grid Ally) type resin-encapsulated semiconductor device. Depending on the design of the mounting substrate, the second convex portion 6 on the outer peripheral portion 4b on the back surface of the package may be used as an electrode terminal.
FN (Quad Flat Non-lead Pac)
kage) and SON (Small Outline N)
A resin-encapsulated semiconductor device that can be handled in the same manner as in on-lead package) can be obtained. (Second Specific Example) FIG. 2 is a sectional view of a second specific example of the present invention.
【００１５】パッケージ４の側面４ｃからリード２１が
導出されており、そのリード２１がパッケージ４に沿う
ように形成され、パッケージ上面４ｄまで延びている。
その延ばされたリード端部２１ａのパッケージ上面４ｄ
での位置は、ちょうどパッケージ裏面外周部４ｂの第２
の凸部６の位置と一致するようになっている。このよう
に、リード２１がパッケージ上面４ｄまで延びているこ
とにより、パッケージを図２（ｂ）に示すように積層す
ることが可能となる。A lead 21 extends from the side surface 4c of the package 4, and the lead 21 is formed along the package 4 and extends to the package upper surface 4d.
The package upper surface 4d of the extended lead end 21a
Is exactly the second position of the outer peripheral portion 4b of the package back surface.
And the position of the convex portion 6. Since the leads 21 extend to the package upper surface 4d in this manner, the packages can be stacked as shown in FIG. 2B.
【００１６】[0016]
【発明の効果】本発明に係わる半導体装置とそのリード
フレーム及びその製造方法は、上述のように構成したの
で、以下の効果を奏する。 （１）ボンディング部の裏面に突起があることにより、
安定したボンディング性が得られ、特に、ボンディング
ワイヤーがリードフレームから剥離するような不具合を
防止することが出来る。The semiconductor device, its lead frame, and its manufacturing method according to the present invention have the following effects because they are configured as described above. (1) Because there is a projection on the back surface of the bonding part,
Stable bonding properties can be obtained, and in particular, problems such as peeling of the bonding wire from the lead frame can be prevented.
【００１７】（２）パッケージ裏面端部とパッケージ上
面端部に電極端子が存在することにより、パッケージの
スタックが可能となり、生産性を向上させることが可能
になる。 （３）一つのパッケージで電極端子の配列がエリアアレ
イタイプ（ＢＧＡ又はＬＧＡ）の実装及び周辺タイプ
（ＱＦＮ又はＳＯＮ）の実装が可能であり、実装基板の
設計自由度が高くなる。(2) The presence of the electrode terminals at the back end of the package and the end of the top surface of the package enables stacking of the packages, thereby improving productivity. (3) With one package, the array of electrode terminals can be mounted in an area array type (BGA or LGA) and in a peripheral type (QFN or SON), which increases the degree of freedom in designing a mounting board.
【図１】本発明に係わる第１の具体例を示す図である。FIG. 1 is a diagram showing a first specific example according to the present invention.
【図２】本発明に係わる第２の具体例を示す図である。FIG. 2 is a diagram showing a second specific example according to the present invention.
【図３】従来の半導体装置を示す図である。FIG. 3 is a diagram showing a conventional semiconductor device.
１ 半田ボール ２ リードフレーム ３ 第１の凸部 ４ パッケージ ４ａ パッケージの裏面 ４ｂ パッケージの裏面の外周部 ４ｃ パッケージの側面 ４ｄ パッケージの上面 ５ 半導体装置 ６ 第２の凸部 ７ ボンディング部 ８ ハーフエッチ １１ 絶縁性接着剤 １２ 半導体チップ １３ ワイヤー １４ 樹脂 ２１ リード DESCRIPTION OF SYMBOLS 1 Solder ball 2 Lead frame 3 First convex part 4 Package 4a Backside of package 4b Peripheral part of backside of package 4c Side surface of package 4d Upper surface of package 5 Semiconductor device 6 Second convex part 7 Bonding part 8 Half etch 11 Insulation Adhesive 12 Semiconductor chip 13 Wire 14 Resin 21 Lead
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/31 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/31
Claims (8)
ムに形成した第１の凸部をパッケージ裏面に露出するよ
うにした半導体装置において、 前記リードフレームに半田ボールを搭載しない第２の凸
部を形成し、この凸部を前記パッケージ裏面に露出する
ように構成したことを特徴する半導体装置。1. A semiconductor device in which a first protrusion formed on a lead frame for mounting a solder ball is exposed on the back surface of a package, wherein a second protrusion on which no solder ball is mounted is formed on the lead frame. A semiconductor device characterized in that the projection is exposed on the back surface of the package.
の外周部に配設されることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein said second convex portion is provided on an outer peripheral portion of a back surface of said package.
等しいことを特徴とする請求項１叉は２記載の半導体装
置。3. The semiconductor device according to claim 1, wherein a thickness of the first convex portion is equal to a thickness of the second convex portion.
ていることを特徴とする請求項１乃至３の何れかに記載
の半導体装置。4. The semiconductor device according to claim 1, wherein said first convex portion and said second convex portion are connected to each other.
周部の一辺に少なくとも二つ形成されていることを特徴
とする請求項１乃至４の何れかに記載の半導体装置。5. The semiconductor device according to claim 1, wherein at least two second protrusions are formed on one side of an outer peripheral portion of a back surface of the package.
レームのリードが導出され、この導出されたリードがパ
ッケージに沿って成形され、且つ、リードの端部がパッ
ケージ上面に配設されていることを特徴とする請求項１
乃至５の何れかに記載の半導体装置。6. The lead of the lead frame is led out from a side surface of the package, the lead is formed along the package, and an end of the lead is provided on a top surface of the package. Claim 1
6. The semiconductor device according to any one of claims 1 to 5.
であって、 半田ボールを搭載するランドとなる第１の凸部と、前記
第１の凸部を囲むように形成された第２の凸部とを少な
くとも含むことを特徴とするリードフレーム。7. A lead frame for mounting a semiconductor chip, comprising: a first protrusion serving as a land for mounting a solder ball; and a second protrusion formed to surround the first protrusion. A lead frame comprising at least:
をエッチングにより製造する方法であって、 前記エッチングを行う際、半田ボールを搭載するランド
となる第１の凸部を形成すると共に、前記第１の凸部を
囲むように第２の凸部を形成することを特徴とするリー
ドフレームの製造方法。8. A method for manufacturing a lead frame on which a semiconductor chip is mounted by etching, wherein, when the etching is performed, a first protrusion serving as a land on which a solder ball is mounted is formed, and the first protrusion is formed. A method for manufacturing a lead frame, comprising forming a second projection so as to surround the projection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28095298A JP3109490B2 (en) | 1998-10-02 | 1998-10-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28095298A JP3109490B2 (en) | 1998-10-02 | 1998-10-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000114449A true JP2000114449A (en) | 2000-04-21 |
| JP3109490B2 JP3109490B2 (en) | 2000-11-13 |
Family
ID=17632199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28095298A Expired - Fee Related JP3109490B2 (en) | 1998-10-02 | 1998-10-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3109490B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768191B2 (en) | 2001-08-10 | 2004-07-27 | Infineon Technologies Ag | Electronic component with stacked electronic elements |
| KR100631939B1 (en) * | 2002-07-16 | 2006-10-04 | 주식회사 하이닉스반도체 | A semiconductor device which is formed by stacking a bga package and a tsop package |
| KR101146973B1 (en) * | 2005-06-27 | 2012-05-22 | 페어차일드코리아반도체 주식회사 | Package frame and semiconductor package using the same |
-
1998
- 1998-10-02 JP JP28095298A patent/JP3109490B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768191B2 (en) | 2001-08-10 | 2004-07-27 | Infineon Technologies Ag | Electronic component with stacked electronic elements |
| KR100631939B1 (en) * | 2002-07-16 | 2006-10-04 | 주식회사 하이닉스반도체 | A semiconductor device which is formed by stacking a bga package and a tsop package |
| KR101146973B1 (en) * | 2005-06-27 | 2012-05-22 | 페어차일드코리아반도체 주식회사 | Package frame and semiconductor package using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3109490B2 (en) | 2000-11-13 |
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