JP2000091309A - Device and method for forming semiconductor pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately form a fine pattern, when silylation is used for the formation of a semiconductor pattern. SOLUTION: After well known novolac is rotationgly applied to a substrate (a) which is to be worked as a lower-layer resist 2, the resist 2 is head-baked (b) at a high temperature and a resist for silylation is applied so as (c) to have the head-baked novalac resist from into a thin film as an upper-layer resist 3. Then the structure of the silylated resist which is the the upper-layer resist 3 is changed by exposing the silylated resist 3 (d). Thereafter, an upper-layer silylated pattern is formed, by utilizing the fact that only the upper-layer resist 3 is selectively silylated through silylation (e), so that the lower-layer resist 2 is developed (f) with oxygen plasma in a dry state by using the silylated pattern as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor pattern forming apparatus and method for forming a fine pattern in semiconductor manufacturing.

[0002]

2. Description of the Related Art In general, as a method of forming a fine pattern in the manufacture of semiconductors, a method of forming a resist pattern by applying a photosensitive material as a resist on a substrate to be processed, and performing exposure and wet development processing is common. Was. However, in recent years, with the miniaturization of patterns, Journal
f Photopolymer Science Tec
hnology Volume11, Number4
As disclosed in (1998) 613-618, after exposure, a treatment (silylation treatment) is performed in an organic gas atmosphere containing silicon (Si) as a constituent element, and a Si element is selectively applied only to a desired portion of the resist. A method has been studied in which oxygen plasma resistance is imparted by being introduced, and then a fine pattern is formed by dry (dry) development with oxygen plasma.

A conventional example will be described with reference to the drawings. FIG. 5 shows a schematic diagram of the process. FIG. 6 shows a flowchart of the process. 5A shows a substrate to be processed, 1 is a Si substrate (silicon substrate), and 9 is a silicon oxide (SiO ₂ ) film. It is assumed that the SiO ₂ film 9 is formed on the Si substrate 1 by S11 in FIG. Next, as shown in FIG.
A resist 8 is spin-coated on the iO ₂ film 9 (S12).
After that, prebaking is performed (S13). Next, as shown in (c), the resist 8 is cross-linked by exposing a desired portion of the resist 8 to form a cross-linked portion 4 of the resist 8 (S14). The exposure method here is a well-known ultraviolet ray,
An exposure method capable of irradiation with high energy such as X-rays and electron beams can be applied. Then, post-baking is performed (S15).
Next, a resist 8 including a crosslinked portion 4 crosslinked by exposure
Is exposed to an organic gas atmosphere containing a Si element, for example, a dimethylsilyldimethylamine (DMSDMA) atmosphere for a desired time to perform a silylation treatment (S16). As shown in (d) by this silylation treatment, the resist 8 in the uncrosslinked portion 5 excluding the crosslinked portion 4 due to the above-mentioned exposure reacts the phenolic hydroxyl group contained in the structure with DMSDMA by the silylation reaction. Then, the Si element is taken into the resist 8. In FIG. 5, the silylated portion is the portion indicated by oblique lines, and is hereinafter referred to as a silylated layer. Next, as shown in (e), the entire surface is etched by oxygen plasma to selectively remove the resist 8 by etching (dry development) only in the cross-linking portions 4 into which Si atoms do not enter. Further, by etching with CF-based gas such as CF ₄ or F-based gas, SiO
_{The two} films are removed (S17). Thus, the fine pattern 6 can be formed. Finally, as shown in (f), the resist 8 is stripped (S18).

[0004]

In a conventional pattern forming method involving a silylation treatment, a resist is applied on a substrate to be processed in a thick film of about 0.5 μm to 1.0 μm (micrometer), and the resist is formed. Is subjected to exposure and silylation processing, and as shown in FIG. 7, only a portion having a desired depth L in the resist is selectively silylated to control the thickness of the silylated layer (hatched portion). Is difficult,
The pattern dimension controllability was poor. In addition, as shown in FIG. 8, when the silylated layer (shaded portion) is formed thick, the silylated layer swells and comes into contact with an adjacent pattern, thereby reducing the resolution of the pattern. Further, as shown in FIG. 9, the heat resistance of the resist was poor, so that the micropattern was thermally deformed during dry development treatment with oxygen plasma. In addition, since the depth of the silylated layer cannot be controlled, it is difficult to remove the silylated layer and the resist. And other issues.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an apparatus and method for accurately forming a fine pattern when a silylation process is used for forming a semiconductor pattern. The purpose is to obtain. In particular, it is an object of the present invention to provide an apparatus and a method capable of controlling the depth of a silylated layer.

[0006]

A semiconductor pattern forming apparatus according to the present invention comprises: means for forming a lower resist on a substrate; means for forming an upper resist on the lower resist; means for exposing the upper resist; It is characterized by comprising means for silylating the upper layer resist, and means for etching the silylated substrate.

The means for forming the lower resist is characterized in that the lower resist is heat-treated so that the lower resist does not react to the formation and silylation treatment of the upper resist.

The semiconductor pattern forming apparatus according to the present invention is characterized in that a material having a high dry etching resistance with respect to the substrate is used as a material of the lower resist.

The above semiconductor pattern forming apparatus is further characterized by further comprising means for forming an antireflection film layer between the lower resist and the upper resist.

The semiconductor pattern forming apparatus according to the present invention is characterized in that a material transparent to exposure light is used as a material for the upper layer resist.

In the semiconductor pattern forming apparatus according to the present invention, a material having a desired transmittance by adding an opaque material to the exposure light to a material transparent to the exposure light is used as the material of the upper layer resist. It is characterized by the following.

[0012] A semiconductor pattern forming method according to the present invention is a method for forming a semiconductor pattern in forming a fine pattern, the method comprising a step of forming a multilayer resist structure comprising a lower resist and an upper resist, and a step of silylating the upper resist. It is characterized by the following.

According to the semiconductor pattern forming method of the present invention, when a material transparent to exposure light is used as an upper resist, reflection of exposure light by the lower resist is prevented between the lower resist and the upper resist. The step of providing an anti-reflection film.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 will be described with reference to the drawings. FIG. 1 is a schematic diagram of the process. FIG.
FIG. 4 is a flowchart of the process. On the left side of FIG. 2,
The names of the devices used in each step are shown. Hereinafter, the points different from the related art will be mainly described. FIG. 1A shows a substrate to be processed manufactured as a result of S11, 1 is a Si substrate, and 9 is a SiO ₂ film. First, as shown in (b), S
A novolak resist (hereinafter, a resist based on a novolak resin is referred to as a novolak resist; for example, an i-line resist PFI-38 manufactured by Sumitomo Chemical Co., Ltd.) as the lower resist 2 is spin-coated to a thickness of about 0.5 μm on the iO ₂ film 9. Then, hard baking is performed at a temperature of about 200 to 300 ° C. to thermally crosslink (S22). Thermal crosslinking is an example of the case where the material is baked by heat. Alternatively, a cured resin that is cured by irradiation with light or ultraviolet light (UV) may be used as the resist.

Thereafter, as shown in (c), a polyvinyl phenol resin or a silylation resist (for example, NTS4 manufactured by Sumitomo Chemical Co., Ltd.) is formed on the hard-baked novolak resist as an upper layer resist 3 for silylation. ) Is applied on a thin film of about 0.05 μm by a spin coating method (S23). Here, since the lower resist 2 applied as the lower layer is thermally crosslinked at a high temperature, the upper resist 3
Can be satisfactorily applied without being mixed with the lower resist 2.

Next, pre-baking (S13), (d)
By exposing a desired portion of the upper resist in such a manner, the upper resist is crosslinked to form a crosslinked portion 4 of the upper resist (S14). As the exposure method here, a known exposure method capable of irradiating high energy such as ultraviolet rays, X-rays, and electron beams can be applied.
rF) When exposing with an excimer laser, the irradiation amount is about 200 to 300 mJ / cm ² when a polyvinyl phenol resin is used as the upper resist, and
When the silylation resist NTS4 manufactured by Sumitomo Chemical Co., Ltd. is used, it is preferably about 5 to 10 mJ / cm ² . here,
Sumitomo Chemical's silylation resist NTS4 is a chemically amplified resist, and is post-baked after exposure to 110-110.
It is necessary to perform heat treatment at a temperature of 130 ° C. for about 1 minute (S
15).

Next, as shown in (e), the silylated resist (upper layer resist) including the crosslinked portion 4 crosslinked by exposure is exposed to an organic gas atmosphere containing Si element, for example, dimethylsilyldimethylamine (DMSDMA). The silylation treatment is performed by exposing the film to the atmosphere for a desired time (S1).
6). Due to this silylation treatment, as shown in (e), the silylated resist in the uncrosslinked portion 5 (the portion indicated by oblique lines) except for the crosslinked portion 4 due to the aforementioned exposure is included in the structure by the silylation reaction. Phenolic hydroxyl groups and DMSD
MA reacts and Si element is taken into the resist. In the present invention, the novolak resist thermally crosslinked does not show a silylation reaction. in this way,
On the novolak resist thermally crosslinked so as not to show a silylation reaction, a thin silylated resist (0.05 μm
Since the coating is applied, the silylation region, that is, the penetration depth of the Si element does not diffuse too much in the depth direction due to the variation of the silylation condition, and the penetration depth is determined by the coating thickness of the silylated resist ( (About 0.05 μm), it is very easy to control the silylation region and to control the size. In other words, an upper layer resist having the same thickness as the silylation depth may be formed.

Next, as shown in (f), the entire surface is etched by oxygen plasma to selectively etch away (dry-develop) the lower resist only at a portion where Si atoms do not enter, thereby obtaining a fine pattern. The pattern 6 can be formed. Here, since the lower resist is hard baked at a high temperature and thermally crosslinked, it is hardly damaged by oxygen plasma, and a good pattern without pattern deformation or the like as shown in FIG. 9 can be formed. Further, the silylation treatment is performed so that Si
Since the region to which the element is added is limited in the upper resist, there is also an advantage that the processing time can be easily controlled even when ashing removal (ash removal) is performed in stripping and removing the silylated resist.

In this embodiment, the positive type process in which the exposed area is removed by dry development without being silylated has been described. However, the area other than the exposed area is removed by dry development without being silylated. It is clear that the present invention is also effective in a negative type process.

In the first embodiment, the Si substrate 1 and the SiO ₂
On the substrate to be processed composed of the film 9, as the lower layer resist 2,
A known novolak resist is spin-coated, hard-baked at a high temperature, and a resist for silylation is applied as a thin film as an upper resist 3 on the hard-baked novolak resist. By exposing the silylated resist, which is the upper resist 3 applied with a thin film, the structure of the silylated resist alone is changed. Thereafter, only the upper resist is selectively silylated by the silylation treatment. Utilizing this, an upper layer silylation pattern is formed, and then the lower layer resist is dry-developed with oxygen plasma using the silylation pattern as a mask.

The required characteristics of the upper resist (silylated resist) and the lower resist according to the first embodiment will be described below. 1. Required properties of upper layer resist (silylated resist) (1) Silylation reaction. (2) Do not mix with and react with the lower resist during application and baking of the upper resist (incompatibility). 2. Required properties of lower layer resist (1) No silylation reaction. (2) Do not mix with the upper layer resist during the application and baking of the upper layer resist. In addition, it does not react with the upper layer resist (incompatible). (3) High etching resistance when removing the SiO ₂ film by etching. (4) High heat resistance and rigidity. Conventionally, it has been necessary to use a resist that uses both characteristics of performing a silylation reaction and having high etching resistance at the time of removing the SiO ₂ film by etching. However, according to the present invention, the upper layer resist (silylated resist) is used. Since the etching resistance to the substrate to be processed (SiO ₂ ) is not required as a required characteristic, the silylation reaction can be performed without being limited to the above-mentioned etching-resistant material as the silylated resist. Any material can be applied.

Embodiment 2 FIG. Embodiment 2 will be described with reference to the drawings. FIG. 3 is a schematic diagram of the process. FIG. 4 is a flowchart of the process. FIG. 3A shows a substrate to be processed. First, as in the first embodiment, a novolak resist (for example, an i-line resist PFI-3 manufactured by Sumitomo Chemical Co., Ltd.) is formed on the SiO ₂ film 9 as the lower resist 2 as shown in FIG.
8) is spin-coated to a thickness of about 0.5 μm (S21),
Hard baking is performed at a temperature of about 200 to 300 ° C. to thermally crosslink (S22). Thereafter, as shown in (c), as an anti-reflection film 7 on the hard-baked novolak resist, for example, d made by Brewer science
-Apply UV30 to a thickness of 0.1 μm (S31),
Thermal crosslinking is performed at a temperature of about 80 ° C. for about 1 minute (S32), and thereafter, an upper resist 3 for silylation is applied (S2).
3). Here, in the second embodiment, a polyvinyl alcohol resin is applied as a silylated resist of the upper layer to a thin film having a thickness of about 0.05 μm by a spin coating method.
Thereafter, prebaking is performed (S13), and as shown in (e), the polyvinyl alcohol resin, which is the silylated resist, is exposed to crosslink the exposed portion of the upper resist (S14). The exposure method here is a well-known ultraviolet ray, X
Exposure methods that can irradiate high energy rays such as X-rays and electron beams can be applied. When used, about 400 to 500 mJ / cm ² is suitable.
Here, the polyvinyl alcohol resin is transparent to an argon fluoride (ArF) excimer laser beam, which is exposure light, and does not lower the optical contrast even in the exposure of a fine pattern as compared with the case of the first embodiment. A good pattern can be formed. Since the upper resist is transparent to the exposure light and is strongly affected by the reflection from the surface of the lower resist, the antireflection film 7 is important for controlling the dimension of the pattern. Reflection from the lower resist surface causes a standing wave of light due to multiple interference in the upper resist, causing a dimensional shift and, consequently, a pattern deterioration. The antireflection film 7 prevents reflection of exposure light from the upper surface of the lower resist.

In place of the method of applying an antireflection film to reduce the influence of reflection, polyvinyl alcohol resin is made of a material having high absorption for exposure light, for example,
By adding a desired amount of the novolak resin, the method of applying the transmittance of the upper silylated resist to a desired value and applying the same can also improve the dimensional controllability.

By the above-described exposure, as shown in (e), the high-energy-ray exposure-irradiated portion can be crosslinked as the crosslink portion 4. Next, similarly to the first embodiment, post-baking is performed (S15), and as shown in (f), the silylated resist including the cross-linked portion cross-linked by exposure is exposed to Si.
Is exposed to a gas atmosphere containing, for example, dimethylsilyldimethylamine (DMSDMA) atmosphere for a desired time (S1).
6). By this silylation treatment, as shown in (f), the uncrosslinked portion 5 (the portion indicated by oblique lines) excluding the crosslinked portion 4 due to the above-mentioned exposure is converted into a hydroxyl group contained in the structure by a well-known silylation reaction. Reacts with Si to form Si in the resist.
Atoms will be incorporated. In the present invention, a thin (approximately 0.05 .mu.m) silylated resist is applied on the thermally crosslinked antireflection film and the novolak resist so as not to cause a silylation reaction. The coating thickness of the upper resist (0.05 μm
Control) is very easy.

Next, as in the first embodiment, as shown in (g), the entire surface is etched by oxygen plasma to select only a portion into which Si atoms do not enter (a non-silylated region). The antireflection film and the lower resist are etched away. Further, the SiO ₂ film 9 is removed by etching with a CF-based gas (S17). Thus, the fine pattern 6 can be formed. In the present embodiment, the case where a polyvinyl alcohol resin is applied as the transparent upper layer resist has been described, but it is obvious that the present invention can be applied to any material that is transparent to exposure light that can be silylated. .

As described above, the present invention is characterized in that in a method for forming a silylation pattern in forming a fine pattern, a resist is applied in multiple layers and only the upper layer resist formed in a thin film is silylated. Further, a pattern is formed on the upper layer silylated resist by a known exposure and development method, and thereafter, the upper layer resist is silylated. Further, in the method for forming a silylation pattern in the formation of a fine pattern, a desired transmittance can be obtained by adding a material that is opaque to exposure light to a material that is transparent to exposure light, as a silylated layer applied and formed on the upper layer. It is characterized by using a material as described above. Further, in the case where a material transparent to exposure light is used for the upper layer, an anti-reflection film is provided on the lower resist for correct exposure of the upper resist.

In the present invention, the terms “upper layer” and “lower layer” of the upper resist and the lower resist mean that the layer closer to the substrate is the “lower layer” and the layer farther from the substrate is the “upper layer”. Meaning. Therefore, another layer may exist above, below, or between the upper resist and the lower resist. Further, pre-bake and post-bake are optional, and are performed if necessary. In addition, SiO
_{The two} films are examples, and other films may be used. Further, the Si substrate is an example, and another semiconductor substrate may be used. Further, the thermal cross-linking by hard baking is an example, and any processing may be used as long as the upper resist and the lower resist become insoluble.

[Brief description of the drawings]

FIG. 1 is a process schematic diagram of Embodiment 1 of the present invention.

FIG. 2 is a flowchart of the first embodiment of the present invention.

FIG. 3 is a process schematic diagram of Embodiment 2 of the present invention.

FIG. 4 is a flowchart of a second embodiment of the present invention.

FIG. 5 is a schematic view of a conventional process.

FIG. 6 is a conventional flowchart.

FIG. 7 is a diagram showing a conventional problem.

FIG. 8 is a diagram showing a conventional problem.

FIG. 9 is a diagram showing a conventional problem.

[Explanation of symbols]

1 substrate, 2 lower layer resist, 3 upper layer resist, 4
Crosslinked portion, 5 Uncrosslinked portion, 6 Fine pattern, 7 Antireflection film, 8 Resist.

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[Procedure amendment]

[Submission Date] July 16, 1999 (1999.7.1)
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 7

[Correction method] Change

[Correction contents]

Claims (8)

[Claims] A means for forming a lower resist on the substrate; a means for forming an upper resist on the lower resist; a means for exposing the upper resist; a means for silylating the upper resist; A semiconductor pattern forming apparatus, comprising: means for etching a substrate. 2. A semiconductor pattern forming method according to claim 1, wherein said means for forming the lower resist is heat-treated so that the lower resist does not react to the formation and silylation of the upper resist. apparatus. 3. The semiconductor pattern forming apparatus according to claim 1, wherein a material having high dry etching resistance with respect to the substrate is used as a material of the lower layer resist. 4. The semiconductor pattern forming apparatus according to claim 1, further comprising:
2. The semiconductor pattern forming apparatus according to claim 1, further comprising means for forming an antireflection film layer between the lower resist and the upper resist. 5. The semiconductor pattern forming apparatus according to claim 4, wherein a material transparent to exposure light is used as a material of the upper layer resist. 6. A material having a desired transmittance by adding a material opaque to exposure light to a material transparent to exposure light, as a material of the upper layer resist. The semiconductor pattern forming apparatus according to the above. 7. A semiconductor pattern forming method for forming a fine pattern, comprising: a step of forming a multilayer resist structure including a lower resist and an upper resist; and a step of silylating the upper resist. Method. 8. A step of providing an antireflection film between the lower resist and the upper resist in order to prevent reflection of the exposure light by the lower resist when using a material transparent to the exposure light as the upper resist. 8. The method according to claim 7, further comprising the step of: