JP2004530922A - Process for forming sublithographic photoresist features - Google Patents

Abstract

A process for forming sublithographic features in an integrated circuit. This process involves altering the photoresist layer (16) after patterning and pattern development and before patterning the underlayer. The altered photoresist layer (16) has different etch rates in the vertical and lateral directions. The modified photoresist layer (16) is trimmed by plasma etching. The features included in the trimmed photoresist layer (16) have a sublithographic size in the lateral direction.

Description

[Display of related application]
[0001]
No. 09 / 819,692 (Attorney Docket No. 39153/404 (F0943)) filed by Okoroanyanwu et al., "Process for Preventing Patterned Shape Destruction by Electron Beam Stabilization". (Process for Preventing Deformation of Pattered Photoresist Features by Electron Beam stabilization), and U.S. Application No. 09 / 820,143 (Attorney Docket No. 39153/405 (F0945)) "SEM inspection of patterned photoresist features and "Improving SEM Inspection and Analysis of Paterned Photoresist Features" and U.S. Ser. No. 09 / 819,344 (Attorney Docket No. 39153/406 (F1061)) "Reducing the critical dimension size of integrated circuit device features." "Process for reducing the Critical Dimensions of Intergrated Circuit" and U.S. Application No. 09 / 819,343 filed by Gabriel et al. (Attorney Docket No. 39153/298 (F0785)) "Selective Photoresist Hardening to Faciliate Lateral Trimming" and U.S. Ser. No. 09 / 819,552 (Attorney Docket No. 39153/310 (F0797)) "Ultra Thin Film" These applications are based on "Process for Improving the Etch Stability of Ultra-Thin Photoresist", the contents of which are incorporated herein by reference.
【Technical field】
[0002]
The present invention generally relates to integrated circuit (IC) manufacturing. More specifically, the present invention relates to the fabrication of IC features having sub-lithographic levels in width dimension using a modified photoresist surface.
[Background Art]
[0003]
In the semiconductor or integrated circuit (IC) industry, there is a need to produce ICs with higher device densities and smaller chips to achieve higher performance ICs and to reduce manufacturing costs. The purpose is. This intent for large circuits requires further miniaturization of circuit size and device features. This ability to reduce structure size, such as gate length and conductor width, in field-effect transistors (FETs) is driven by lithographic performance.
[0004]
In an IC manufacturing technique, a photomask (also called a mask) or a reticle is often used. Radiation is applied through a mask or reticle or irradiated remotely to form an image on a semiconductor wafer. Generally, the aforementioned image is projected and patterned onto a layer of material, such as a photoresist material on a wafer. The patterned photoresist material described above is then used to define doping, deposition, etching, and / or other areas of the IC structure. The aforementioned patterned photoresist material also limits the area of the conductor or the conductor pad associated with the metal layer of the IC. Further, the patterned photoresist material can define isolation regions, transistor gates, or other device structures and components.
[0005]
A lithographic system for transferring an image or pattern onto the aforementioned photoresist material includes a light source configured to emit electromagnetic radiation or light at one or more wavelengths. This light source emits radiation at wavelengths of 365 nanometers (hereinafter nm), 248 nm, and / or 193 nm. The photoresist material patterned by such radiation is selected to correspond to the wavelength of the radiation. Preferably, in the area of the photoresist material where the radiation is projected, a photochemical modification occurs such that it becomes properly soluble or insoluble in the next development process step.
DISCLOSURE OF THE INVENTION
[Problems to be solved by the invention]
[0006]
As the size of IC devices has decreased, it has become necessary to make features smaller than possible with conventional lithographic techniques. One method for achieving sublithographic device sizes, i.e., smaller than the size of devices formed by conventional lithography, is to use features formed on the patterned photoresist material on an underlying layer. Shrinking or "trimming" before being patterned into a pattern. This method, commonly referred to as a resist trim or trimming process, allows the size of the trimmed features to be smaller than the original features lithographically patterned using a mask or reticle.
In this method, a portion of the patterned photoresist material is removed using plasma etching. In a conventional resist trimming process, plasma is applied to the entire surface of the patterned photoresist material so that the top surface as well as the side or lateral surface of the patterned photoresist material is etched. Is done.
Therefore, the trimming time is increased (ie, the patterned photoresist is further reduced) to further reduce the widthwise size (ie, to further etch the sides and reduce the width of features such as contact lines). The material is exposed to plasma etching for a longer period of time), and the thickness of the patterned photoresist material is also reduced. Unfortunately, sufficient shrinkage of the patterned photoresist material does not leave a film of the photoresist or a subsequent process, such as transferring to the underlying layer through an etching process. A film thickness sufficient for implementation is not left.
[0007]
In order to address such a problem of thinning the photoresist, a thicker photoresist material film has been used. The thickness of the photoresist material is increased in order to resist the thinning of the resist that occurs during the trimming process.However, when the thickness of the photoresist material is increased, pattern deformation and / or incomplete pattern transfer are likely to occur. Become. Since the feature resolution is to some extent inversely proportional to the exposure or lithography wavelength, it is desirable to have a shorter exposure wavelength (eg, 157 nm, 126 nm, or 13.4 nm) in patterning the photoresist material. At present, there is no photoresist material specifically suited for such a short exposure wavelength. Instead, photoresist materials conventionally used in 265 nm, 248 nm, or 193 nm lithography are used. These longer wavelength photoresist materials have greater light absorption per unit thickness as the exposure wavelength is reduced. As noted above, thickening the photoresist material becomes increasingly opaque as the emitted wavelength is reduced, and does not produce the required photochemical change over the entire thickness of the material. As the thickness of the photoresist material increases, incomplete pattern transfer tends to occur throughout the thickness of the material.
[0008]
On the other hand, even if a complete pattern transfer is performed, prolonged trimming (to achieve fairly narrow gauge features in the aforementioned photoresist material) may result in pattern shape breakage, pattern bending, or pattern breakage. There is a possibility of causing significant pattern deformation. Since the pattern deformation in the patterned features is a function of the aspect ratio (ie, the height-to-width ratio of the patterned features), the thicker the photoresist material, the higher the resulting pattern deformation Easy to cause. Accordingly, when the thickness of the photoresist material is set to the conventional thickness, the amount of trimming in the horizontal direction is reduced due to the consumption of the thickness in the vertical direction. The trimming process requires a patterned, sufficiently thick layer to be deposited in a subsequent process (e.g., polysilicon), especially as the plasma etching also causes the photoresist to become thinner as the patterned features become narrower. It must be stopped before the lateral thickness is barely reduced to ensure that it remains for the etching process that transfers the pattern to the underlying layer, such as gate formation. On the other hand, when the photoresist material layer at the start of trimming is made thicker to enable trimming for a long time, there is a problem that pattern transfer becomes incomplete and / or pattern deformation occurs.
[0009]
Therefore, there is a need for a process for maximizing the use of conventional photoresist trimming processes. In addition, the photoresist material can be used for subsequent lithographic processes to remove features that have been patterned on the photoresist material without being associated with pattern deformation, incomplete transfer, or the formation of films with insufficient thickness in the vertical plane. Further processing is needed to perform the lateral trimming. Still further, there is a need for a process for forming sublithographic features without significant modifications to conventional lithographic photo techniques, means, materials, or equipment, and without substantially reducing throughput. is there.
[Means for Solving the Problems]
[0010]
One aspect of the invention relates to a method of trimming a patterned feature on a photoresist layer. The aforementioned photoresist layer is disposed on a substrate, and the aforementioned features have a top and side surfaces. The method includes altering a top of a feature patterned on the aforementioned photoresist layer to form an altered top. The method further includes trimming the patterned features on the photoresist layer to form the trimmed features. The vertical trimming speed and the side trimming speed are related to the aforementioned features. Since the uppermost portion is modified, the trimming speed on the vertical surface is lower than the trimming speed on the side surface.
[0011]
Another aspect relates to an integrated circuit manufacturing process. The process includes developing the patterned photoresist layer to alter the aforementioned photoresist layer to form a top and a bottom of at least one feature. The patterned photoresist layer includes at least one feature. The etching rate at the top is different from the etching rate at the bottom. The process is further performed to modify the at least one feature to have a sublithographic size in the lateral dimension and to have a sufficient thickness in the vertical plane to maintain pattern integrity. Etching the patterned photoresist layer.
[0012]
Yet another aspect relates to an integrated circuit having sublithographic features. The features are formed by a process of patterning features on a photoresist layer disposed on a substrate, developing the features patterned on the photoresist layer, and altering at least a portion of the photoresist layer. . The aforementioned features are patterned according to radiation at the lithographic wavelength and a pattern applied to the mask or reticle. The top of the features on the photoresist layer is altered to have a different etch rate than the bottom of the features patterned on the photoresist layer. The process further includes trimming the features patterned in the photoresist layer to a sublithographic size and transferring the trimmed features on the photoresist layer to a substrate.
BEST MODE FOR CARRYING OUT THE INVENTION
[0013]
The above aspects will be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals.
FIG. 1 shows a wafer 13 in a lithography system 10. The lithography system 10 includes a chamber 50, a light source 22, a condenser lens assembly 24, a mask or reticle 18, an objective lens assembly 26, and the stage 11. Lithographic system 10 may be a lithographic camera or a stepper unit. For example, the lithography system 10 may be a PAS5000 / 900 series instrument manufactured by ASML, a microscan DUV system manufactured by Silicon Valley Group, or an XLS family manufactured by the Korean company Integrated Solutions Company. It may be a microlithography system.
[0014]
The wafer 13 has a substrate 12, a layer 14, and a photoresist layer 16. A photoresist layer 16 is disposed on layer 14, which is disposed on substrate 12. Wafer 13 may be the entire integrated (IC) circuit wafer or a portion of an IC wafer. Wafer 13 may be part of an IC such as a memory, process unit, input / output device, and the like. Substrate 12 may be a semiconductor substrate such as silicon, gallium arsenide, germanium, or other substrate material. Substrate 12 may have one or more layers of materials and / or features, such as lines, interconnects, biases, doped regions, etc., and may further include transistors, microactuators, microsensors, capacitors, resistors, diodes, etc. Device.
[0015]
Layer 14 may be an insulating layer, a conductor layer, a barrier layer, or another layer of material to be etched, doped, or layered. According to one embodiment, layer 14 is comprised of one or more layers of material, for example, alternating alternating organic or non-organic anti-reflective coatings (ARCs) on doped or undoped polysilicon. It is constituted by the formed polysilicon stack. According to another example, layer 14 is a hard mask layer, such as a silicon nitride layer, a metal layer. This hard mask layer can be used as a pattern layer for processing the substrate 12 or a layer on the substrate 12. According to yet another example, layer 14 is an anti-reflective coating (ARC). Substrate 12 and layer 14 are not disclosed for purposes of limiting the invention, and may each include a conductor, semiconductor, or insulator material.
[0016]
Photoresist layer 16 can include various chemical photoresists suitable for lithographic applications. Photoresist layer 16 is selected to have a photochemical reaction in response to electromagnetic radiation emitted from light source 22. The material comprising the photoresist layer 16 can include, among other things, a matrix material or resin, a sensitizer or inhibitor, and a solvent. Photoresist layer 16 is preferably chemically amplified and is an organic-based photoresist, whether positive or negative. For example, layer 16 may include PAR700 photoresist manufactured by Sumitomo Chemical Co., Ltd. Photoresist layer 16 is deposited, for example, by spin coating on layer 14. The photoresist layer 16 has a thickness smaller than 1.0 μm.
[0017]
The chamber 50 of the lithography system 10 may be a vacuum or low pressure chamber for use in a vacuum ultraviolet (VUV) lithography process. The chamber 50 may contain any gas in the atmosphere, such as nitrogen. In other forms, the lithographic system 10 may be used in various lithographic processes, including lithography using electromagnetic radiation at any wavelength width.
[0018]
The light source 22 irradiates the photoresist layer 16 with light or electromagnetic radiation through the condenser lens assembly 24, the mask or reticle 18, and the objective lens assembly 26. In one embodiment, light source 22 is an excimer laser and has a wavelength of 365 nm, 248 nm, 193 nm, or 157 nm. In other embodiments, the light source 22 comprises various other light sources capable of emitting radiation having a wavelength in the ultraviolet (UV), vacuum ultraviolet (VUV), deep ultraviolet (DUV), or extreme ultraviolet (EUV). You can also.
[0019]
Assemblies 24 and 26 include lenses for properly focusing on the photoresist layer 16 in pattern radiation (ie, radiation from a light source 22 modified by a pattern or image illuminated on a mask or reticle 18); Includes mirrors, collimators, beam splitters, and / or other optical components. The stage 11 supports the wafer 13 and moves the wafer 13 with respect to the assembly 26.
[0020]
In one embodiment, mask or reticle 18 is a binary mask. The mask or reticle 18 has a translucent substrate 21 (eg, glass or quartz) with an opaque or patterned layer 20 (eg, chromium or chromium oxide) thereon. Opaque layer 20 provides a pattern or image associated with a suitable circuit pattern, feature or device to be projected onto photoresist layer 16. In other embodiments, mask or reticle 18 may be an attenuated phase shift mask, an alternative phase shift mask, or another type of mask or reticle.
[0021]
A pattern or image on a mask or reticle 18 is patterned on the photoresist layer 16 using the lithography system 10. After the patterned photoresist layer 16 has been developed, but before such a pattern has been transferred onto an underlayer, such as layer 14, the electron beam exposure process shown in FIG. 2 is performed. It is understood that the wafer 13 is removed from the chamber 50 during the electron beam exposure process and is disposed in a different chamber and / or a different external environment by means such as a diffused electron beam light source (flood electron beam: not shown). Let's do it.
[0022]
The wafer 13 is exposed to the electron beam 52 in a floodlight manner in an electron beam exposure process also called an electron beam curing process or a resist curing process. FIG. 2 shows a cross-sectional view of a portion of the wafer 13, specifically, a cross-sectional view of the curing process of the line features 54 patterned on the layer 16. According to one embodiment, line features 54 have an initial or nominal lateral size of about 150 nm for 193 nm lithography system 10.
[0023]
The electron beam 52 is preferably a uniform collimated beam emanating from an extended area electron source (not shown) and being flood exposed onto the entire wafer 13. The extended area electron source has a cold cathode type, and generates an electron beam 52 by ion collision energy. One example of an extended area electron source suitable for producing the electron beam 52 is manufactured by Electron Vision Corporation.
[0024]
When an electron beam 52 having sufficient energy is applied to the molecules that make up the polymer material of layer 16, the molecules undergo a chemical reaction, ie, cross-linking, until the functional groups of the polymer material are completely decomposed. The completely disassembled portion of the line feature 54 is shown in oblique lines and has a top portion 58 (see FIG. 2). The portions of the line feature 54 that have not been penetrated or driven by the electron beam 52, ie, the bottom 60, remain unaffected by the irradiation (ie, cross-linking until the polymer functional groups in the bottom 60 are completely degraded). Is not done). The bottom 60 is located just below the top 58.
[0025]
The top 58 has different electrical, optical, and material properties than the bottom 60. When the functional groups of the polymer material are completely degraded, the electrical and optical properties of the top 58 will be different, increasing the density of the top 58 and decreasing the porosity of the top 58 compared to the bottom 60. The cured top 58 is more resistant to etch (equivalent to a slower erosion or etch rate) than the uncured bottom 60. Accordingly, in the resist trimming process (see FIGS. 3 and 4) following the electron beam exposure or curing process (FIG. 2), the lateral trimming amount of the feature in the layer 16 can be made larger than before, and the layer 16 does not become too thin.
[0026]
FIG. 3 is a cross-sectional view of a part of the wafer 13 during the resist trimming process. The resist trimming process is preferably a plasma etching process. Wafer 13 is exposed to a plasma etchant 62 to trim or reduce the size of the features patterned on layer 16. The plasma etching agent 62 is O_Two, HBr / O_Two  Or Cl_Two/ O_TwoAnd various plasma chemical etchings. In one embodiment, the wafer 13 is in a different process environment (eg, a different chamber) as compared to the e-beam curing process of FIG. Various etching systems can be used to provide the plasma etchant 62, such as those manufactured by Applied Materials, Inc. of Santa Clara, Calif., Or Lam Research of Fremont, CA.
[0027]
The plasma etchant 62 etches all exposed surfaces on layer 16, including the top and sides. However, the dimensions of layer 16 are not reduced on all sides of layer 16 because the etch rate during the e-beam curing process varies from site to site (e.g., top 58 and bottom 60). As shown in FIG. 3, the amount of decrease in the vertical direction of the line feature 54 is smaller than the amount of decrease in the transverse direction. Specifically, the vertical trimming speed of the uppermost portion 58 is lower than the trimming speed of the side surface on the bottom portion 60 side, so that the line feature 54 temporarily becomes a T-shaped feature. The dotted line in FIG. 3 shows the line feature 54 before the resist trimming process starts.
[0028]
Preferably, the thickness of top 58 is selected such that substantially the entire top 58 is depleted or etched away upon completion of the desired amount of lateral trimming of bottom 60. The thickness of the uppermost portion 58 is determined by the depth of the electron beam 52 implanted into the layer 16. The beam penetration thickness of the electron beam 52 can be controlled by changing the energy, acceleration voltage, amount of current of the electron beam 52, and / or by changing the processing gas or wafer temperature associated with the electron beam curing process. Yes, in other words, the thickness of the uppermost portion 58 can be selected. Approximately, the thickness of the uppermost portion 58 is a function of the acceleration voltage of the electron beam 52, and the relationship is expressed as follows.
Rg = (0.046V_a ^1.75) / D
Rg is the beam penetration thickness (unit: microns), and V_aIs the aforementioned acceleration voltage or energy (unit: KeV), and d is the density of the target material, for example, the layer 16 (unit: g / cm)³).
[0029]
The erosion or etching rate of the cured portion of layer 16 is determined by the dose of electron beam 52. Layer 16 is dosed at about 1000 μC / cm.²When cured by an electron beam 52, the etch rate at the cured portion (eg, top 58) of layer 16 using a polysilicon etch or an oxidized etch plasma chemistry may be an uncured or untreated layer 16 It is about 35% to 50% slower than the part (eg, bottom 60). The polysilicon etch is typically HBr / Cl₂/ O₂Or HBr / O₂Including the use of chemical etchants. Oxide etching typically involves C₄F₈/ Ar / O₂And fluorine-based chemical etching.
[0030]
The decrease in the etching rate is caused by the fact that the dose amount is about²When it becomes larger, it becomes saturated and does not change much after that. FIG. 6 shows the etching rate when the PAR700 photoresist is cured with various doses of the electron beam. The PAR700 photoresist shown in FIG. 6 is formed on a silicon substrate. Each of plot lines 100, 102, 104 and 106 shows the etch rate as a function of the electron beam dose. Plot line 100 is HBr / O₂Shows the etch rate of PAR700 photoresist when exposed to chemical etching. Plot line 102 is HBr / Cl₂/ HeO₂Shows the etch rate of PAR700 photoresist when exposed to chemical etching. Plot line 106 represents C₄F₈/ Ar / O₂Shows the etch rate of PAR700 photoresist when exposed to chemical etching. According to one embodiment, the chemical etching parameters are as follows:
1. HBr / O₂Chemical etching (plot line 100): 15 mT, 100/20 W (source / bias), HBr / O₂Ratio = 15/25 sccm
2. HBr / Cl₂/ HeO₂Chemical etching (plot line 102): 20mT, 100 / 20W (source / bias), HBr / Cl2 / HeO₂Ratio = 150/30/15
3. HBr / HeO₂Chemical etching (plot line 104): 60 mT, 200/90 (source / bias), HBr / HeO₂/ He ratio = 200/10/100 sccm.
4. C₄F₈/ Ar / O₂Chemical etching (plot line 106): 60 mT, 1700 W, C₄F₈/ Ar / O₂Ratio = 7/500/2 sccm.
[0031]
FIG. 4 is a sectional view of the wafer 13 when the resist trimming process (FIG. 3) is completed. The line feature 54 has a bottom 60 that is laterally trimmed and a top portion 58 that is completely etched away with a plasma etchant. After the plasma etching, the line feature 54 has a size 64 in the lateral direction and a thickness of the vertical film after the trimming process. For example, if the initial or nominal lateral size 56 is 150 nm, the trimmed lateral size 64 may be approximately 70 nm or less, and the vertical film thickness 66 may range from 1000 to 6000.
[0032]
Conventionally, features having a nominal lateral size of about 150 nm patterned with 193 nm lithography without curing with an electron beam are reduced to about 110 nm or less without causing feature destruction in subsequent processes such as etching processes. Trimming could not be performed (that is, the thickness of the remaining layer 16 was insufficient). On the other hand, the resulting feature patterned on layer 16 is altered or modified by altering or modifying the top portion of layer 16 so that the rate of thinning of the resist film in the vertical direction during the resist trimming process is reduced. Can achieve the trimming in the lateral size in the same manner as can be achieved by the conventional resist trimming process, and can leave a resist film thicker than before. In other embodiments, the resulting features patterned on layer 16 can have a resist thickness similar to conventional ones, and can have a smaller lateral size. . The increased resist thickness increases the probability that the trimmed features will be undamaged in subsequent processes and will be steadily patterned on the underlayer.
[0033]
In FIG. 5, the aforementioned trimmed line features 54 shown in FIG. 4 are patterned on layer 14 by an etching process. Due to the sufficient vertical thickness 66 remaining in the line feature 54, the shape of the line feature 54 (having a reduced lateral size) remains after a subsequent lithography process such as an etching process. And a pattern of pattern features 68 is formed in layer 14. The feature 68 has a shape similar to that of the line feature 54, and its horizontal size is the same as the trimmed horizontal size 64. The features 68 may be, but are not limited to, wires, transistor gates, insulated wires, and the like.
[0034]
In this manner, integrated circuit (IC) features having sublithographic characteristics can be formed using conventional photoresist materials, conventional photoresist thicknesses, and / or conventional resist trimming processes. At this time, there is no problem such as pattern deformation or shape destruction when transferring the pattern to the underlying layer. Further, it is possible to perform more intense resist trimming (for example, to extend the trimming time) without causing a situation in which the pattern is decomposed due to an insufficient resist film thickness. . In the developed photoresist layer 16, by appropriately modifying the surface of the photoresist layer 16, curing is performed by an electron beam selected to have a specific beam characteristic, so that the feature size is reduced by a mask or a mask. It is reduced by about half from the size formed on the reticle 18.
[0035]
The surface of layer 16 can be modified by various other treatments to slow down the resist thickness in the vertical direction during the resist trimming process. For example, layer 16 may be exposed, after patterning and development, and prior to trimming, to ultraviolet light (UV) at a wavelength at which the material comprising layer 16 becomes opaque. In another example, layer 16 comprises N₂, H₂, Ar, or anisotropic plasma such as bromine containing various fluorine, chlorine, and gas mixtures. In yet other examples, layer 16 may be coated before exposure to a developer solution or when layer 16 is N₂, B, P, As, etc., before exposure to low energy implantation.
[0036]
While the preferred embodiments and specific examples have been given, they are for the purpose of explanation and are not limited to the exact details described above. Various modifications may be made in the details within the scope of the claims without departing from the scope of the claims.
[Brief description of the drawings]
[0037]
FIG. 1 is a schematic block diagram of a lithography system for patterning a wafer.
FIG. 2 is a schematic sectional view of the wafer according to FIG. 1 in an electron beam curing step.
FIG. 3 is a schematic sectional view of the wafer according to FIG. 2 in a partial resist trimming step.
FIG. 4 is a schematic sectional view of the wafer according to FIG. 3 in an entire resist trimming step.
FIG. 5 is a schematic sectional view of the wafer according to FIG. 4 in an etching step.
FIG. 6 is an explanatory diagram of a plot showing an etching rate of a photoresist material obtained by performing curing while changing the dose of an electron beam for each type of chemical etching.

Claims (10)

A method for trimming features (54) patterned in a layer of photoresist (16) disposed on a substrate (12), said features including a top (58) and side surfaces. ,
Altering a top portion (58) of the feature (54) patterned on the photoresist layer to form an altered top portion;
Trimming the patterned features on the photoresist to form trimmed features.
The method wherein the top trimming causes a vertical trimming speed at the feature to be lower than a lateral trimming speed. The method of claim 1, wherein the vertical trimming speed is a function of the dose of the electron beam (52), and the altered top vertical thickness is a function of the current or acceleration voltage of the electron beam. . The method of claim 1, wherein the lateral size (64) of the trimmed features is a sublithographic size. An integrated circuit manufacturing method,
Developing a patterned photoresist layer (16) comprising at least one feature,
Altering the patterned photoresist layer (16) to form a top (58) and a bottom (60) of the at least one feature (54), wherein the top (58) Etching rate is different from the etching rate of the bottom,
The photoresist layer (16) is etched to expose the at least one feature (54) to a vertical film whose lateral size is sublithographic (64) and sufficient to maintain pattern integrity. Changing to a thickness. The method according to claim 1 or 4, wherein the step of altering comprises the step of causing a cross-linking reaction at the top (58) until the functional groups of the material constituting the top (58) are decomposed. The method of claim 1 or 4, wherein the altering comprises flood exposing the photoresist layer (16) to an electron beam. The method of claim 4, wherein etching the patterned photoresist layer comprises etching the top (58) and laterally etching the bottom (60). The method of claim 4 including selecting parameters related to the electron beam according to at least one of an etch rate and a film thickness of the uppermost portion (58). An integrated circuit having features (54) of sublithographic size (69), said features (54) comprising:
Forming a pattern of said features (54) on a photoresist layer (16) disposed on a substrate (12) by patterning with a mask or reticle (18) and radiation at a wavelength used in lithography;
Developing the features (54) patterned on the photoresist layer (16);
At least a portion of the photoresist layer (16) is altered such that a top portion (58) of the features (54) patterned on the photoresist layer (16) is overlaid on the photoresist layer (16). Having a different etch rate from the bottom (160) of the patterned feature (54);
Trimming the features (54) patterned on the photoresist layer (16) to a sublithographic size (64);
Transferring the patterned and trimmed features (54) on the photoresist layer (16) to the substrate (14). 68) is an integrated circuit that is sublithographic. 17. The method of claim 16, wherein the altering further comprises curing the photoresist layer (16) with an electron beam (52) to form the top (58).

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