JP2000077789A - Manufacture of semiconductor laser - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor laser to be lessened in series resistance and improved in high-temperature characteristics and high-current injection characteristics. SOLUTION: A selective growth buried layer 4 is provided on each side of a stripe-like mesa 3 using a dielectric layer provided to the top of a stripe- like mesa 3 as a mask, and a P-type InP clad layer 7 is grown on all the surface at temperatures lower than 580 deg.C through an organic metal vapor growth method where chlorine compound is added. It is preferable that the uppermost surface of the selective growth buried layer 4 is set higher than the top of the stripe-like mesa 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor laser, and more particularly to a method of manufacturing a semiconductor laser characterized by a manufacturing condition for reducing series resistance in an InGaAsP-based buried heterojunction structure (BH) semiconductor laser. It is about the method.

[0002]

2. Description of the Related Art In recent years, the development of optical communication technology based on semiconductor lasers and optical fibers has been remarkable, and optical fibers have almost completely replaced metal cables in trunk-line communication paths. It is predicted that optical fibers will extend to each home with the increase in the amount of communication information in Japan.

In order to realize FTTH (Fiber To The Home) based on use on an individual basis, it is required to establish a technique for producing a large number of semiconductor laser modules at a low cost and a semiconductor. In order to reduce the cost of the laser module, a semiconductor laser having good temperature characteristics that does not require a cooling device is required.

Here, referring to FIG. 7, a typical example of a conventional semiconductor laser having a BH structure used as a semiconductor laser for optical communication is an FBH (Flat-Buried).
-Heterostructure) semiconductor laser will be described. Referring to FIG. 7, this FBH semiconductor laser has a (100) plane n-type I
On an nP substrate 31, an n-type InP serving also as an n-side cladding layer
Buffer layer 32, n-type InGaAsP light guide layer and I
After the light emitting region 33 composed of an nGaAsP active layer and the p-type InP cladding layer 34 are sequentially grown by MOVPE (metal organic chemical vapor deposition), a dielectric mask (not shown) such as a SiO ₂ mask is used. To form a stripe-shaped mesa 35 extending in the <011> direction.

Next, using this dielectric mask as a selective growth mask, a stripe-shaped mesa 35 is buried with a p-type InP burying layer 36 by MOVPE, and then an n-type InP current block layer 37 is formed on the upper surface. The mesa 35 is grown so as to be higher than the top surface.

Next, the dielectric mask is removed, and p
After growing the p-type InP cladding layer 38 and the p-type InGaAsP contact layer 39, an isolation groove 40 parallel to the stripe direction is formed. Finally, a p-side electrode 42 is provided on the p-type InGaAsP contact layer 39, and n Type I
The FBH structure semiconductor laser is completed by providing the n-side electrode 41 on the back surface of the nP substrate 31. The separation groove 40 is provided to narrow the range of current flow and reduce parasitic capacitance based on the pn junction.

[0007]

One of the factors that limit the operation of a semiconductor laser at a high temperature is the series resistance of a device (series resistance). When the series resistance of a device increases, the joule during high current injection is reduced. It is desirable to reduce the series resistance as much as possible because heat is generated by heat to limit the operating temperature or to increase the voltage applied to the entire device, leading to an increase in leakage current.

In the conventional FBH semiconductor laser, the p-type InP cladding layer 3 having a small carrier mobility is used.
The resistances of 4, 38 are the main series resistance components.
The uppermost p-type InP cladding layer 34 of the stripe-shaped mesa 35 has a problem of diffusion of the p-type impurity into the active layer, so that the doping concentration is limited.
It is desired that the nP cladding layer 38 be as high as possible of p-type and as thin as possible from the viewpoint of reducing the resistance.

However, the p-type InP cladding layer 38 is grown on a growth layer whose surface is not flat. In order to improve the surface morphology at that time and to make the entire surface flat, the p-type InP cladding layer 38 must be at least 600 ° C. Is grown at a growth temperature of a certain thickness, and as a result, the p-type InP cladding layer 3 is formed.
8 has a problem that the series resistance of the element is large due to the layer thickness of 8.

Therefore, the present invention is characterized in that the series resistance of the device is reduced, the characteristics at high operating temperatures are improved, and the characteristics at high current injection are improved.

[0011]

FIG. 1 is an explanatory view of the basic structure of the present invention, and FIG. 2 is a graph showing the dependence of the efficiency of taking impurities on the growth temperature and the plane orientation for explaining the operation of the present invention. FIG. 3 is an explanatory diagram of the dependency, and means for solving the problem in the present invention will be described with reference to FIGS. 1 and 2. FIG. See FIG. 1. (1) The present invention relates to a method for manufacturing a semiconductor laser, wherein n
After the growth layer including the active layer 2 provided on the InP substrate 1 is mesa-etched to form a stripe-shaped mesa 3, the side portion of the stripe-shaped mesa 3 is formed by using a dielectric mask provided on the top of the stripe-shaped mesa 3 as a mask. Is buried in the selective growth buried layer 4 and then the dielectric mask is removed.
When the nP clad layer 7 is grown on the entire surface, the growth is performed at a growth temperature of 580 ° C. or less by a metal organic chemical vapor deposition method to which a chlorine compound is added.

As described above, the p-type InP clad layer 7 is formed on the top surface of the stripe-shaped mesa 3 and on the selective growth buried layer 4 composed of, for example, the p-type InP buried layer 5 and the n-type InP current block layer 6. Is grown at a growth temperature of 580 ° C. or less by a metalorganic vapor phase epitaxy method to which a chlorine compound is added, so that the surface becomes flat with a relatively thin thickness and the surface morphology is good. Therefore, no thickness is required to make the surface of the p-type InP cladding layer 7 flat, so that the series resistance of the device can be reduced.

(2) According to the present invention, in the above (1), the uppermost surface of the selective growth buried layer 4 is a stripe-shaped mesa 3
Characterized by being higher than the top surface.

When doping the InP layer with a p-type impurity,
Although the incorporation efficiency of the impurity depends on the growth temperature and the plane orientation, the uppermost surface of the selective growth buried layer 4 is made higher than the top surface of the stripe-shaped mesa 3 so that the stripe of the selective growth buried layer 4 can be formed. Since the slope on the side of the mesa 3 can be a (111) B plane or the like, the plane orientation dependency of the impurity incorporation efficiency on the flat face and the slope of the selective growth buried layer 4 can be positively utilized. .

(3) In the present invention according to the above (1) or (2), the p-type impurity concentration in the vicinity of the top surface of the stripe-shaped mesa 3 of the p-type InP cladding layer 7 is increased by selectively growing the buried layer 4. The p-type InP clad layer 7 on the flat surface has a p-type impurity concentration higher than that of the p-type InP clad layer 7.

As shown in FIG. 2, when the growth temperature is set to 580 ° C. or lower, the p-type InP cladding layer 7 can be doped at a higher concentration than in the conventional case, and the impurity incorporation efficiency can be reduced. Due to the plane orientation dependence, the p-type impurity concentration in the vicinity of the top surface of the stripe-shaped mesa 3 of the p-type InP cladding layer 7 is changed to the p-type impurity concentration of the p-type InP cladding layer 7 on the flat surface of the selective growth buried layer 4. It can be about six times larger.

(4) In the present invention according to (3), the p-type impurity concentration in the vicinity of the top surface of the stripe-shaped mesa 3 of the p-type InP cladding layer 7 is 2.5 × 10 ¹⁸ cm ^−3.
It is characterized by the above.

As apparent from FIG. 2, the slope of the selective growth buried layer 4 on the side of the stripe-shaped mesa 3 is (111) B
The p-type impurity concentration in the vicinity of the top surface of the stripe-shaped mesa 3 of the p-type InP cladding layer 7 can be set to 2.5 × 10 ¹⁸ which was impossible under the conventional manufacturing conditions.
The impurity concentration can be set to not less than cm ⁻³ , thereby also reducing the series resistance of the element.

(5) The present invention is characterized in that in any one of the above (1) to (4), Zn is used as a p-type impurity for forming the p-type InP clad layer 7.

As described above, Zn is a typical p-type impurity having a remarkable dependence on the growth temperature and the plane orientation of the impurity incorporation efficiency.

(6) Further, according to the present invention, in the method of manufacturing a semiconductor laser, the growth layer including the active layer 2 provided on the n-type InP substrate 1 is mesa-etched to form the stripe-shaped mesa 3, and then the stripe-shaped mesa 3 is formed. Using the dielectric mask provided on the top of the mesa 3 as a mask, the side portions of the stripe-shaped mesa 3 are buried with the selective growth burying layer 4, and after removing the dielectric mask, the p-type InP cladding layer 7 is grown on the growth surface. After growing the entire surface until the surface becomes flat, a part of the p-type InP cladding layer 7 is removed by etching to make the p-type InP cladding layer 7 thinner.

As described above, the p-type InP cladding layer 7 may be grown thick until it becomes flat, and then thinned by etching to obtain a device with the conventional growth conditions of the p-type InP cladding layer 7. Can be reduced.

(7) Further, according to the present invention, in the method of manufacturing a semiconductor laser, the growth layer including the active layer 2 provided on the n-type InP substrate 1 is mesa-etched to form the stripe-shaped mesa 3, and then the stripe-shaped mesa 3 is formed. Using the dielectric mask provided on the top of the mesa 3 as a mask, the side portions of the stripe-shaped mesa 3 are buried with the selective growth burying layer 4, and after removing the dielectric mask, the p-type InP cladding layer 7 is grown on the growth surface. After growing the entire surface until the surface becomes flat, a part of the p-type InP cladding layer 7 is removed by etching to completely remove the p-type InP cladding layer 7 on the flat surface of the selective growth buried layer 4. And

As described above, after the p-type InP cladding layer 7 is grown thick until it becomes flat, when it is removed by etching, the p-type InP cladding layer 7 on the flat surface of the selective growth buried layer 4 is completely removed. By removing the p-type InP cladding layer 7, the thickness of the p-type InP cladding layer 7 on the top of the stripe-shaped mesa 3 can be made thinner. Reduction becomes possible.

(8) In the present invention, in the above (6) or (7), the step of removing the p-type InP cladding layer 7 may be performed by directly performing the metal organic chemical vapor deposition after the growth of the p-type InP cladding layer 7. It is characterized by a step of etching by supplying a chlorine compound gas in the apparatus.

As described above, by performing the etching step of the p-type InP cladding layer 7 by supplying the chlorine compound gas into the metal organic chemical vapor deposition apparatus, a series of steps are performed continuously and as a dry step. Therefore, the throughput is improved.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a manufacturing process according to a first embodiment of the present invention will be described with reference to FIGS. Referring to FIG. 3 (a), first, TMI (trimethyl indium) and PH ₃ are used as raw material gases on an n-type InP substrate 11 having a (100) plane as a main surface at a substrate temperature of 620 ° C. By flowing SiH ₄ as an impurity source, n serving as an n-side cladding layer having a thickness of 200 to 1000 nm, for example, 500 nm and an impurity concentration of 5.0 × 10 ¹⁷ cm ⁻³ is used.
A type InP buffer layer 12 is grown.

Next, with the substrate temperature also set to 620 ° C., TMI, TEG (triethyl gallium), As
Using H ₃ and PH ₃ , the thickness is, for example, 6 nm.
By alternately growing a non-doped InGaAsP well layer having a compression strain of 1% and a non-strained non-doped InGaAsP barrier layer having a thickness of, for example, 10 nm and a PL wavelength of 1.1 μm. The wavelength is 1.
After growing the InGaAsPMQW active layer 13 of 3 μm, supply of TEG and AsH ₃ is stopped,
By supplying DMZn (dimethylzinc) as a p-type impurity source, the thickness is 100 to 500 nm, for example,
A p-type InP cladding layer 14 having a thickness of 300 nm and an impurity concentration of 5.0 × 10 ¹⁷ cm ⁻³ is sequentially grown.

Then, a thickness of 0.3 μm
After depositing a SiO ₂ film of
11>, a stripe-shaped SiO ₂ mask 15 having a width of 2.0 μm is formed. Then, using this SiO ₂ mask 15 as an etching mask, RIE (reaction) using an ethane-based gas consisting of ethane + hydrogen + trace oxygen is performed. Mesa etching is performed by a method (active ion etching) to form a stripe-shaped mesa 16 having a height of, for example, 2.5 μm and a substantially (011) side surface.

Next, at a growth temperature of 600 ° C., TMI and PH ₃ are used as source gases, DMZn is used as a dopant, and a 2.5 μm-thick SiO ₂ mask 15 is used as a selective growth mask. , With an impurity concentration of 1.0 × 10 ¹⁸ cm ⁻³
After growing the InP buried layer 17, the dopant is
Switching to iH ₄ , an n-type InP current blocking layer 18 having a thickness of, for example, 0.5 μm and an impurity concentration of 2.0 × 10 ¹⁸ cm ⁻³ is grown.

The p-type InP buried layer 17 and the n-type InP
When the selective growth buried layer composed of the current block layer 18 is grown, the conventional selective growth buried layer growth step
The flow rate of I was set to 1.0 sccm, PH ₃ and TM
The flow ratio of I, ie, V / III is 50-200, for example,
120 and a growth rate of 2.0 μm / hour, and monochloromethane (CH ₃ Cl)
The flow rate is set to 10 sccm so that the flow rate ratio to MI, that is, monochloromethane / III becomes 1 to 20, for example, 10.

In this case, the growth in the <01-1> direction is suppressed by the addition of monochloromethane, so that the p-type InP buried layer 17 and the n-type InP current block layer 18 are formed.
Grows almost in parallel with the (100) plane, enabling flat embedding, and the end face of the n-type InP current blocking layer 18 grown higher than the top surface of the SiO ₂ mask 15 is (11)
1) It becomes a slope composed of the B surface.

Next, after removing the SiO ₂ mask 15 by etching, the growth temperature is set to 580 ° C. or less, for example, 560 ° C.
And TMI, PH ₃ , and
Using DMZn as a dopant, a striped mesa 1
6 has a thickness at the top of 0.7-1.5 μm, for example
A 1.0 μm p-type InP cladding layer 19 is grown to flatten the surface.

Also in this case, the flow rate of the TMI is set to 1.0 scc.
m, and the flow rate ratio between PH ₃ and TMI, ie, V /
In a state where the growth rate is set to 2.0 μm / hour by setting III to 50 to 200, for example, 120, CH
₃ Cl is added to the TMI at a flow rate ratio of 50 to 100 so that the monochloromethane / III becomes 20 to 100, for example, 50.
The flow of sccm allows flattening even with a thickness of about 1.0 μm.

When a p-type InP layer is grown on an uneven surface at a growth temperature of 560 ° C. under a growth condition in which monochloromethane is not added as in the conventional case, the recesses are completely buried, but electron micrographs When observed in the above, convex hillocks are distributed over the entire surface, resulting in poor morphology.

It is considered that such deterioration in morphology is caused by insufficient migration of In atoms on the substrate surface at a low growth temperature, and such deterioration in morphology is caused by a semiconductor laser. Therefore, such low-temperature growth has not been performed for actual production, since this leads to a reduction in manufacturing yield or a reduction in reliability.

However, as a result of the research conducted by the present inventors, it has been found that when the growth is performed at a low temperature under the growth conditions to which monochloromethane is added, good surface morphology is exhibited. It was confirmed that almost no convex hillocks were observed on the whole and the surface morphology was very good.
00) It is considered that migration of In atoms on the substrate is promoted.

Referring again to FIG. 2, at the growth temperature of 560 ° C., the Zn incorporation efficiency near the (111) B plane is higher than the incorporation rate in the (100) plane. Is 4.0 × 10 ¹⁸ cm ⁻³ in other regions, and 1.2 × 10 ¹⁸ cm ⁻³ in other regions, and the I concentration at the conventional growth temperature of 600 to 650 ° C.
Approximately 2. known as the saturation concentration of Zn incorporation into nP.
Doping of 0 × 10 ¹⁸ cm ⁻³ or more has become possible.

Next, with the substrate temperature set at 620 ° C., the TMI, T
By using EG, AsH ₃ , and PH ₃ and flowing DMZn as an impurity source, the thickness of the flattened p-type InP cladding layer 19 is, for example, 0.2 μm.
After growing a p-type InGaAsP intermediate layer 20 having an impurity concentration of 1.0 × 10 ¹⁸ cm ^-3 and a PL wavelength of 1.3 μm, the substrate temperature was set to 550 ° C.
By flowing DMZn as an impurity source using I, TEG, and AsH ₃ , for example, a thickness of 0.6
μm, p-type In with an impurity concentration of 1.0 × 10 ¹⁹ cm ⁻³
A GaAs contact layer 21 is grown.

Referring to FIG. 4E, the range of current flow is reduced, and the n-type InP
In order to reduce the parasitic capacitance due to the pn junction caused by the current block layer 18, wet etching
Two separation grooves 22 are formed in parallel with the stripe-shaped mesas 16.

Next, a Ti / Pt / Au electrode is provided on the p-type InGaAs contact layer 21 as a p-side electrode 24, and
Au · G as an n-side electrode 23 on the back surface of the type InP substrate 11
By providing the e / Au electrode, a semiconductor laser having an FBH structure is completed.

The series resistance of the FBH semiconductor laser of the present invention is 5.5 when the resonator length is 300 μm.
Ω, and the thickness of the p-type InP cladding layer 19 is 2.0 μm.
As compared with the conventional semiconductor laser having a serial resistance of 6.0 m, an improvement of about 0.5 Ω, that is, an improvement of about 8% was observed.

This is because, in the step of growing the p-type InP cladding layer 19 as described above, by adding Cl into the growth atmosphere and performing low-temperature growth, the surface can be flattened with a smaller thickness than before. In addition, in low-temperature growth, the Zn incorporation efficiency shows a tendency opposite to that of the conventional growth at around 620 ° C., and the doping over the conventional saturation concentration becomes possible. Due to both effects, the series resistance of the p-type InP cladding layer 19 could be reduced.

[0044] Thus, it is possible to improve the manufacturing yield by low-temperature growth with the addition of Cl in the growth atmosphere, it is possible to reduce the series resistance of the device, the characteristic temperature T ₀ with it than the conventional Can be improved.

Next, the manufacturing process of the second embodiment of the present invention will be described with reference to FIG. 5, but up to the step of growing the n-type InP current blocking layer 19, the above-described first embodiment will be described. Since it is completely the same as the mode, the growth method will be briefly described. See FIG. 5A. Under the same conditions as in the first embodiment, (10
An n-type InP buffer layer 12 also serving as an n-side cladding layer and an InGaAs
sPMQW active layer 13 and p-type InP clad layer 1
4 are sequentially grown, a striped SiO ₂ mask 15 is formed, and then a mesa etching is performed using the SiO ₂ mask 15 as an etching mask to form a striped mesa 16. With monochloromethane added, p-type InP
The buried layer 17 and the n-type InP current block layer 18 are grown.

Next, after the SiO ₂ mask 15 is removed by etching, TMI and PH _{3 are used} as source gases and DMZn as a dopant at a growth temperature of 620 ° C., as in the prior art. The thickness at the top of the stripe-shaped mesa 16 is 1.5 to 3.0 μm, for example, 2.5 μm.
An m-type InP clad layer 19 is grown to planarize the surface.

Next, after the supply of TMI, PH ₃ , and DMZn is stopped, monochloromethane is supplied.
The p-type InP cladding layer 19 is removed by dry chemical etching so that the thickness at the top of the stripe-shaped mesa 16 is 2.0 μm or less, for example, 1.0 μm.

Hereinafter, although not shown, the first
Under exactly the same conditions as in the embodiment of FIG.
After a p-type InGaAsP intermediate layer 20 and a p-type InGaAs contact layer 21 are sequentially grown on the surface of the P-cladding layer 19, two separation grooves 22 are formed, and then a p-side is formed on the p-type InGaAs contact layer 21. By providing a Ti / Pt / Au electrode as the electrode 24 and providing an Au.Ge/Au electrode as the n-side electrode 23 on the back surface of the n-type InP substrate 11, a semiconductor laser having an FBH structure is completed.

In the second embodiment of the present invention, since the p-type InP cladding layer 19 is thinned by etching, even if the p-type InP cladding layer 19 is formed thick under conventional growth conditions, The final series resistance can be reduced.

Next, the manufacturing process of the third embodiment of the present invention will be described with reference to FIG. 6. Except for the etching process of the n-type InP current blocking layer 19, the above-described second embodiment will be described. Since it is completely the same as the mode, the growth method will be briefly described. See FIG. 6A. Under the same conditions as in the first embodiment, (10
An n-type InP buffer layer 12 also serving as an n-side cladding layer and an InGaAs
sPMQW active layer 13 and p-type InP clad layer 1
4 are sequentially grown, a stripe-shaped SiO ₂ mask (not shown) is formed, and then a mesa etching is performed by using the SiO ₂ mask as an etching mask to form a stripe-shaped mesa 16 and then a growth gas. With monochloromethane added to the atmosphere, p-type I
After growing the nP buried layer 17 and the n-type InP current block layer 18, and then removing the SiO ₂ mask by etching, TMI and PH are used as source gases at a growth temperature of 620 ° C. as in the prior art. ₃ , and the thickness at the top of the stripe-shaped mesa 16 is 1.5 to 3.0 μm, for example, 2.
A 5 μm p-type InP cladding layer 19 is grown to flatten the surface.

Next, referring to FIG. 6B, the supply of TMI, PH ₃ and DMZn is stopped, and then monochloromethane is supplied.
The p-type InP cladding layer 19 is subjected to dry chemical etching to remove the p-type InP cladding layer 19 until the n-type InP current blocking layer 18 is exposed. Embed in the recess at the top.

Next, referring to FIG. 6C, under the same conditions as in the first embodiment,
P-type InP cladding layer 19 embedded in recess and n-type I
On the surface of the nP current blocking layer 18, p-type InGaAsP
After sequentially growing the intermediate layer 20 and the p-type InGaAs contact layer 21, two separation grooves 22 are formed, and then the p-side electrode 2 is formed on the p-type InGaAs contact layer 21.
4, a Ti / Pt / Au electrode is provided, and an n-type I
Au · Ge / as the n-side electrode 23 on the back surface of the nP substrate 11
By providing the Au electrode, a semiconductor laser having the FBH structure is completed.

In the third embodiment of the present invention, the p-type InP cladding layer 19 is
Is thinned so as to be buried in the concave portion at the top, and even if the p-type InP clad layer 19 is formed thick under the conventional growth conditions, the final series resistance can be reduced. The resistance can be further reduced as compared with the second embodiment.

The embodiments of the present invention have been described above. However, the present invention is not limited to the FBH semiconductor laser, and a selective growth buried layer is formed on the side surface of the stripe-shaped mesa by selective growth. The present invention can be applied to various buried heterojunction structure semiconductor lasers on which an InP cladding layer is grown on the entire surface, and the selectively grown buried layer provided on the side surface of the stripe-shaped mesa is a p-type InP buried layer and n
The present invention is not limited to the combination of the type InP current blocking layers. For example, an Fe-doped InP high resistance layer may be provided as at least a part of the selective growth buried layer.

In the first embodiment, p-type InP grown at a low temperature in a growth gas containing Cl is used.
Although the clad layer is left as it is, a thinning process or an embedding process may be performed as in the second and third embodiments. In this case, although the number of steps is increased, The series resistance of the element can be further reduced, and
Compared with the above-described second and third embodiments, since the dependence of the efficiency of taking in impurities on the growth temperature is used, the resistance can be further reduced.

In each of the above embodiments, the components
Monochloromethane as a gas added to a long gas atmosphere
(CH_ThreeCl), but monochloroethane (C
_TwoH _FiveCl) or carbon tetrachloride (CCl_Four)
Is also good.

In each of the above embodiments, n
Although the InP buffer layer 12 is used, the InGaAs PMQW active layer 13 may be provided directly on the n-type InP substrate 11.
1 itself becomes the n-side cladding layer.

In each of the above embodiments, no light guide layer is provided. However, an InGaAsP light guide layer may be provided between the active layer, the buffer layer and the cladding layer. The active layer is not limited to the MQW active layer, but may be a bulk InGaAsP active layer.

In each of the above embodiments, p
In forming the type InP cladding layer 19, Zn is used as a p-type impurity.
g or Cd may be used, and the same impurity incorporation characteristics as Zn can be seen.

In the second and third embodiments, dry chemical etching is used when the thickness of the p-type InP clad layer 19 is reduced in order to simplify the manufacturing process. Alternatively, normal wet etching may be used.

[0061]

According to the present invention, after the selective growth buried layer is formed, the p-type InP cladding layer is grown thereon by growing it at a low temperature in a growth gas containing Cl, or By etching the thick and flat p-type InP cladding layer, the thickness of the p-type InP cladding layer can be reduced, thereby reducing the series resistance of the semiconductor laser and improving the temperature characteristics. Therefore, it greatly contributes to further development and spread of optical fiber communication technology.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of the dependence of the efficiency of taking in impurities on the growth temperature and the plane orientation.

FIG. 3 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention after FIG. 3;

FIG. 5 is an explanatory diagram of a manufacturing process partway through a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process according to a third embodiment of the present invention.

FIG. 7 is a sectional view of a conventional FBH semiconductor laser.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 n-type InP substrate 2 active layer 3 striped mesa 4 selective growth buried layer 5 p-type InP buried layer 6 n-type InP current blocking layer 7 p-type InP cladding layer 11 n-type InP substrate 12 n-type InP buffer layer 13 InGaAs PMQW active layer 14 p-type InP clad layer 15 SiO ₂ mask 16 striped mesa 17 p-type InP buried layer 18 n-type InP current block layer 19 p-type InP clad layer 20 p-type InGaAsP intermediate layer 21 p-type InGaAs contact layer 22 Separation groove 23 n-side electrode 24 p-side electrode 31 n-type InP substrate 32 n-type InP buffer layer 33 light-emitting region 34 p-type InP clad layer 35 stripe-shaped mesa 36 p-type InP buried layer 37 n-type InP current block layer 38 p InP cladding layer 39 p-type InGaAsP contact layer 40 separation groove 41 n-side electrode 42 p-side electrode

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Takayuki Watanabe 1000th Azagami Azagami, Showa-cho, Nakakoma-gun, Yamanashi Prefecture F-term in Fujitsu Quantum Devices Co., Ltd. 5F045 AA04 AB12 AB17 AB18 AB32 AC01 AC08 AC09 AC19 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AF04 AF13 AF20 BB07 BB08 BB16 BB19 CA12 DA53 DA55 DA60 DA66 DB02 EE12 HA13 HA14 5F073 AA22 AA51 AA74 BA02 CA12 DA05 EA29

Claims (8)

[Claims] 1. A mesa-etched growth layer including an active layer provided on an n-type InP substrate to form a stripe-shaped mesa, and then using a dielectric mask provided on the top of the stripe-shaped mesa as a mask. After burying the side portions with a selective growth burying layer, and then removing the dielectric mask, when growing a p-type InP cladding layer over the entire surface,
580 by metalorganic chemical vapor deposition with a chlorine compound added
A method for manufacturing a semiconductor laser, wherein the growth is performed at a growth temperature of not more than ° C. 2. The method according to claim 1, wherein an uppermost surface of the selective growth buried layer is higher than a top surface of the stripe-shaped mesas. 3. The p-type impurity concentration in the vicinity of the top surface of the stripe-shaped mesa of the p-type InP cladding layer is higher than the p-type impurity concentration of the p-type InP cladding layer on the flat surface of the selective growth buried layer. 3. The method according to claim 1, wherein
3. The method for manufacturing a semiconductor laser according to item 1. 4. A p-type impurity concentration in the vicinity of a top surface of a stripe-shaped mesa of the p-type InP cladding layer is 2.5 ×
^{4. The} method for manufacturing a semiconductor laser according to claim 3, wherein the density is 10 ¹⁸ cm ^-3 or more. 5. The method of manufacturing a semiconductor laser according to claim 1, wherein Zn is used as a p-type impurity for forming said p-type InP cladding layer. 6. A stripe-shaped mesa is formed by mesa-etching a growth layer including an active layer provided on an n-type InP substrate, and then a stripe-shaped mesa is formed using a dielectric mask provided on the top of the stripe-shaped mesa as a mask. After burying the side portions with a selective growth buried layer, removing the dielectric mask, growing a p-type InP cladding layer over the entire surface until the growth surface becomes flat, and then removing one side of the p-type InP cladding layer. A method for manufacturing a semiconductor laser, comprising thinning the p-type InP cladding layer by removing a portion by etching. 7. A stripe-shaped mesa is formed by mesa-etching a growth layer including an active layer provided on an n-type InP substrate, and then forming a stripe-shaped mesa by using a dielectric mask provided on the top of the stripe-shaped mesa as a mask. After burying the side portions with a selective growth buried layer, removing the dielectric mask, growing a p-type InP cladding layer over the entire surface until the growth surface becomes flat, and then removing one side of the p-type InP cladding layer. A method of manufacturing a semiconductor laser, wherein a p-type InP clad layer on a flat surface of the selective growth buried layer is completely removed by etching a portion. 8. The step of removing the p-type InP cladding layer is a step of, after growing the p-type InP cladding layer, directly supplying a chlorine compound gas in a metal organic chemical vapor deposition apparatus to perform etching. The method for manufacturing a semiconductor laser according to claim 6.